CN114328350B - AXI bus-based communication method, device and medium - Google Patents
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Abstract
The application discloses a communication method, a device and a medium based on an AXI bus, which are characterized in that a bus signal is received through the AXI bus, then the bus signal is converted into an RAM interface signal, the address signal in the RAM interface signal is converted into a reduced address adapting to each peripheral device according to the address of each peripheral device, and finally each peripheral device is informed to execute corresponding actions according to the reduced address of each peripheral device and corresponding data signals. After the technical scheme is adopted, after the bus signal of the AXI bus is received, the bus signal is analyzed, and the bus signal is converted into the RAM interface signal suitable for the RAM interface, so that more peripheral devices can realize communication with the processor through the AXI bus without additionally developing the AXI bus interface, and the waste of resources is reduced. And the total address signals are optimized, so that the size of the signals is reduced, data can be quickly saved, and the release speed of bus permission is improved.
Description
Technical Field
The present application relates to the field of SOC technologies, and in particular, to a communication method, device, and medium based on an AXI bus.
Background
The SOC is referred to as a system-on-chip, also called a system-on-chip, meaning that it is a product that is an integrated circuit with dedicated targets, containing the complete system and having the entire contents of embedded software. The bus, which is a connector in the SOC, enables communication between the processor and the various peripheral devices. High performance SOCs have increasingly high performance requirements on buses. The AXI bus is a multi-channel transmission on-chip bus with high performance, high bandwidth and low delay, address, control and data phases are separated, unaligned data transmission and disordered access are supported, and SOC can be enabled to obtain more excellent performance with smaller area and lower power consumption, so that the AXI bus is widely applied.
However, most of interfaces of peripheral devices are usually RAM interfaces, and are not provided with AXI bus interfaces, so that when the SOC uses the AXI bus, the peripheral devices need to additionally develop the AXI bus interfaces to enable the processor and the peripheral devices to perform data interaction, and this method causes resource waste.
Therefore, how to reduce the resource waste without developing an AXI bus interface when the processor and the peripheral device use the AXI bus for communication is a problem to be solved by those skilled in the art.
Disclosure of Invention
The application aims to provide an AXI bus-based communication method, an AXI bus-based communication device and a AXI bus-based communication medium, which are used for reducing the waste of resources without additionally developing an AXI bus interface when a processor and peripheral equipment use the AXI bus for communication.
In order to solve the technical problem, the present application provides a communication method based on AXI bus, which is characterized in that the method includes:
Receiving a bus signal of an AXI bus, the bus signal including an address channel signal and a data channel signal;
Analyzing the bus signal, and converting the bus signal into a RAM interface signal, wherein the RAM interface signal comprises an address signal and a data signal;
converting the address signals in the RAM interface signals into reduced addresses suitable for the peripheral devices according to the addresses of the peripheral devices;
And notifying each peripheral device to execute corresponding actions according to the reduced address of each peripheral device and the corresponding data signal.
Preferably, after the step of converting the address signal into the reduced address, the method further comprises:
associating the simplified address of each peripheral device with the corresponding data signal, and storing the simplified address and the corresponding data signal in a queue to be processed in sequence;
further, said notifying each of said peripheral devices to perform a corresponding action based on said reduced address of each of said peripheral devices and corresponding said data signal comprises:
And notifying each peripheral device to execute corresponding actions according to the reduced address and the sequence of the corresponding data signals in the to-be-processed queue.
Preferably, before the step of notifying each peripheral device to perform a corresponding action according to the reduced address and the sequence of the corresponding data signal in the pending queue, the method further includes:
judging whether the peripheral equipment corresponding to the current data of the queue to be processed is in an idle state or not;
If yes, entering a step of informing the peripheral equipment to execute corresponding actions according to the reduced address and the sequence of the corresponding data signals in the to-be-processed queue;
If not, storing the simplified address of the peripheral device and the corresponding data signal into an unresponsive queue.
Preferably, the method further comprises:
If the peripheral equipment corresponding to the reduced address and the corresponding data signal in the non-response queue is detected to be in an idle state, the reduced address and the corresponding data signal in the non-response queue are preferentially executed.
Preferably, before the step of associating the reduced address of each peripheral device with the corresponding data signal and storing the reduced address in the pending queue in sequence, the method further comprises:
Judging whether the queue to be processed is full;
If not, entering a step of associating the simplified address of each peripheral device with the corresponding data signal and storing the simplified address and the corresponding data signal in a queue to be processed in sequence;
if yes, stopping analyzing the bus signal.
Preferably, before the step of storing the reduced address of the peripheral device and the corresponding data signal in an unresponsive queue, the method further includes:
Judging whether the unresponsive queue is not full and the queue to be processed is not empty;
If yes, the step of storing the simplified address of the peripheral device and the corresponding data signal into an unresponsive queue is entered.
Preferably, if the data signal is a read signal, after notifying each peripheral device to execute the corresponding action, the method further includes:
And converting the data returned by the peripheral equipment into a read data path format of the AXI bus and outputting the read data path format to a processor.
In order to solve the technical problem, the present application further provides a communication device based on an AXI bus, where the device includes:
The receiving module is used for receiving bus signals of the AXI bus, wherein the bus signals comprise address channel signals and data channel signals;
The analysis module is used for analyzing the bus signal, converting the bus signal into a RAM interface signal, wherein the RAM interface signal comprises an address signal and a data signal;
The conversion module is used for converting the address signals in the RAM interface signals into reduced addresses suitable for the peripheral devices according to the addresses of the peripheral devices;
and the scheduling module is used for notifying each peripheral device to execute corresponding actions according to the reduced address of each peripheral device and the corresponding data signal.
In order to solve the above technical problem, the present application further provides another AXI bus-based communication device, which includes:
A memory for storing a computer program;
And a processor for implementing the steps of the AXI bus-based communication method as described above when executing the computer program.
To solve the above technical problem, the present application further provides a computer readable storage medium, where a computer program is stored, where the computer program, when executed by a processor, implements the steps of the AXI bus-based communication method as described above.
The communication method based on the AXI bus provided by the application receives a bus signal through the AXI bus, wherein the bus signal comprises an address channel signal and a data channel signal, then analyzes the bus signal, converts the bus signal into an RAM interface signal, the RAM interface signal comprises an address signal and a data signal, converts the address signal in the RAM interface signal into a reduced address which is matched with each peripheral according to the address of each peripheral, and finally informs each peripheral to execute corresponding actions according to the reduced address of each peripheral and the corresponding data signal. Compared with the prior art, the AXI bus interface needs to be additionally developed on the peripheral equipment, so that the resource waste is caused. By adopting the technical scheme, after the bus signal of the AXI bus is received, the bus signal is converted into the RAM interface signal suitable for the RAM interface, so that more peripheral devices can realize communication with the processor through the AXI bus without additionally developing the AXI bus interface, and the waste of resources is reduced. And the total address signals are converted into the simplified addresses adapting to the peripheral devices according to the addresses of the peripheral devices, so that the address signals are optimized, the size of the signals is reduced, the data can be quickly saved, and the release speed of the bus permission is improved.
In addition, the AXI bus-based communication device and the medium provided by the application correspond to the AXI bus-based communication method, and have the same effects.
Drawings
For a clearer description of embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a flow chart of a communication method based on an AXI bus according to the embodiment of the application;
fig. 2 is a block diagram of a communication device based on AXI bus according to an embodiment of the present application;
Fig. 3 is a block diagram of another AXI bus-based communication device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present application.
The embedded system is a hot spot of the development of the current computer industry, with the rapid development of ultra-large scale integrated circuits, the semiconductor industry enters into the deep submicron age, the feature size of devices is smaller and smaller, the chip scale is larger and millions to hundreds of millions of transistors can be integrated on a single chip. Such a dense integration level enables us to integrate the functions previously implemented by several chips, such as a CPU and several I/O interfaces, on a small chip, and to form a powerful, complete system from a monolithic integrated circuit, which is what we refer to as a system on chip SOC.
AXI (Advanced eXtensible Interface) is an on-chip bus that is high performance, high bandwidth, low latency oriented. The address/control and the data phase are separated, the misaligned data transmission is supported, meanwhile, in burst transmission, only the first address is needed, meanwhile, the separated read-write data channel is supported, the obvious transmission access and the disordered access are supported, the timing sequence convergence is easier, and the requirements of ultra-high performance and complex SOC design can be met.
However, the interfaces of most peripheral devices on the SOC are usually RAM interfaces and do not have AXI bus interfaces, and when the SOC uses the AXI bus, the peripheral devices need to additionally develop the AXI bus interfaces to enable the processor and the peripheral devices to perform data interaction, and this method causes resource waste.
The core of the application is to provide a communication method, a device and a medium based on an AXI bus, which are used for reducing the waste of resources without additionally developing an AXI bus interface when a processor and peripheral equipment use the AXI bus for communication.
In order to better understand the aspects of the present application, the present application will be described in further detail with reference to the accompanying drawings and detailed description.
Fig. 1 is a flowchart of a communication method based on AXI bus according to an embodiment of the present application, as shown in fig. 1, where the method includes:
S10: bus signals of an AXI bus are received, the bus signals including address channel signals and data channel signals.
AXI enables SOCs to achieve more excellent performance with smaller area, lower power consumption. One of the main reasons AXI achieves such excellent performance is its unidirectional channel architecture. The unidirectional channel architecture enables the on-chip information stream to be transmitted in only one direction, reducing latency. In addition to reducing latency, the AXI bus defines a handshake protocol before and after entering and exiting the low power saving mode. It is specified how to inform to enter the low power mode, when to turn off the clock, when to turn on the clock, and how to exit the low power mode. This allows all IPs to be easily integrated into a unified system, depending on the design of the power consumption control. AXI is characterized as follows:
Unidirectional channel architecture: the information flow is transmitted in one direction only, so that bridging between clock domains is simplified, and the number of gates is reduced. Delay is reduced as the signal passes through complex systems on chip.
Support for multiple data exchanges: by executing burst operation in parallel, the data throughput capacity is greatly improved, tasks can be completed in a shorter time, and the power consumption is reduced while the high performance requirement is met.
Independent address and data channels: the address and data channels are separated, each channel can be optimized independently, the time sequence channel can be controlled according to the requirement, the clock frequency is raised to the highest value, and the time delay is reduced to the lowest value.
Enhanced flexibility: AXI technology has a symmetrical master-slave interface, and can be used very conveniently, both in point-to-point and in multi-layer systems.
The AXI bus has 5 channels, namely a read address channel, a write address channel, a read data channel, a write data channel, and a write response channel. Each channel is unidirectional. The address channel carries control information for describing the attribute of the transmitted data, the data transmission uses a write channel to realize the transmission from the master to the slave, and the slave uses a write response channel to complete the write-once transmission; the read channel is used to effect the transfer of data from "slave" to "master".
In this embodiment, the address channel signals are a read address channel signal and a write address channel signal, and the data channel signals are a read data channel signal and a write data channel signal.
S11: and analyzing the bus signal, and converting the bus signal into a RAM interface signal, wherein the RAM interface signal comprises an address signal and a data signal.
In step S11, the bus signal is converted into a RAM interface signal according to reading and writing, including a read address signal, a write address signal, a read data signal, and a write data signal.
It will be appreciated that when the RAM interface signal is a read signal, the data returned by the peripheral device also needs to be converted to a mode of an AXI bus signal, which is returned to the processor via the AXI bus.
S12: according to the address of each peripheral device, address signals in the RAM interface signals are converted into reduced addresses which are suitable for each peripheral device.
In a specific implementation, the address channel signal obtained from the processor by the AXI bus is a total address signal for controlling the actions of each peripheral device, and when each peripheral device is controlled, the corresponding peripheral device needs to be found by reading the total address signal. Repeated reading of the total address signal may cause redundancy of signals and may delay the response time of the peripheral device, slowing the speed at which the processor releases bus permissions.
In this embodiment, the total address signal is simplified according to the address of each peripheral device, and the total address signal with a larger bit width is converted into a simplified address adapted to each peripheral device. It can be understood that the optimized simplified address and the corresponding data signal are stored on the bus together, and the process is based on the high-frequency clock of the bus, so that the bus can quickly store data, and the release speed of the bus permission is improved.
S13: and notifying each peripheral device to execute corresponding actions according to the reduced address of each peripheral device and the corresponding data signals.
In step S13, according to the reduced address of each peripheral device, each peripheral device is notified to execute the corresponding data reading or writing action.
According to the AXI bus-based communication method provided by the embodiment of the application, bus signals are received through the AXI bus, the bus signals comprise address channel signals and data channel signals, then the bus signals are analyzed, the bus signals are converted into RAM interface signals, the RAM interface signals comprise address signals and data signals, the address signals in the RAM interface signals are converted into reduced addresses which are matched with the peripheral devices according to the addresses of the peripheral devices, and finally the peripheral devices are informed to execute corresponding actions according to the reduced addresses of the peripheral devices and the corresponding data signals. Compared with the prior art, the AXI bus interface needs to be additionally developed on the peripheral equipment, so that the resource waste is caused. By adopting the technical scheme, after the bus signal of the AXI bus is received, the bus signal is converted into the RAM interface signal suitable for the RAM interface, so that more peripheral devices can realize communication with the processor through the AXI bus without additionally developing the AXI bus interface, and the waste of resources is reduced. And the total address signals are converted into the simplified addresses adapting to the peripheral devices according to the addresses of the peripheral devices, so that the address signals are optimized, the size of the signals is reduced, the data can be quickly saved, and the release speed of the bus permission is improved.
On the basis of the embodiment, in order to increase the data transmission rate, process a large number of data streams and match systems with different transmission rates, the continuous data streams are buffered, so that the data is prevented from being lost during the incoming and storage operations, frequent bus operations are avoided, the burden of a processor is reduced, and the data is processed in a first-in first-out mode.
Specifically, in this embodiment, after the step of converting the address signal into the reduced address, the method further includes:
Associating the simplified address of each peripheral device with the corresponding data signal, and storing the simplified address and the corresponding data signal in a queue to be processed in sequence;
further, notifying each peripheral device to perform a corresponding action based on the reduced address of each peripheral device and the corresponding data signal includes:
and notifying each peripheral device to execute corresponding actions according to the reduced address and the sequence of the corresponding data signals in the queue to be processed.
According to the AXI bus-based communication method provided by the embodiment of the application, the reduced addresses of the peripheral devices and the corresponding data signals are stored in the FIFO memory, and the data is processed in a first-in first-out mode, so that the data transmission rate can be increased, the burden of a processor is reduced, and the bus permission releasing speed is improved.
In a specific implementation, sometimes, the peripheral device corresponding to the new data signal is still executing the action corresponding to the last data signal, and cannot respond to the new data signal timely, which may cause other data signals to fail to continue to execute tasks or cause the new data signal to be lost if no processing is performed.
Therefore, on the basis of the above embodiment, in this embodiment, before the step of notifying each peripheral device to perform the corresponding action according to the reduced address and the sequence of the corresponding data signal in the pending queue, the method further includes:
judging whether peripheral equipment corresponding to current data of a queue to be processed is in an idle state or not;
If yes, entering a step of informing peripheral equipment to execute corresponding actions according to the reduced address and the sequence of the corresponding data signals in the queue to be processed;
If not, the simplified address of the peripheral device and the corresponding data signal are stored in an unresponsive queue.
It will be appreciated that in this embodiment, if the peripheral device is in an idle state, then the action corresponding to the current data of the pending queue is performed. If not in the idle state, the current data is stored in the unresponsive queue, and similarly, the data in the unresponsive queue is stored in a first-in first-out manner. In the subsequent task execution, the data in the unresponsive queue can be preferentially processed; or after all the data in the queue to be processed are processed, the data in the unresponsive queue are processed; or when the peripheral equipment corresponding to the current data in the non-response queue is detected to be idle, the current data in the non-response queue can be immediately processed.
According to the AXI bus-based communication method provided by the embodiment of the application, the reduced address and the corresponding data signal which are not responded in time by the peripheral equipment are stored into the non-responding queue, so that the loss of the signal or the delay of data processing caused by no response is avoided.
In the above embodiment, there is no limitation on when to process the data in the unresponsive queue, and on the basis of the above embodiment, in this embodiment, the method further includes:
If the peripheral equipment corresponding to the reduced address and the corresponding data signal in the non-response queue is detected to be in an idle state, the reduced address and the corresponding data signal in the non-response queue are preferentially executed.
It should be noted that, in this embodiment, the execution speed of the unresponsive queue is higher than that of the queue to be processed, and if the peripheral device corresponding to the current data of the unresponsive queue and the current data of the queue to be processed are the same device and are in an idle state, the peripheral device preferentially executes the action corresponding to the current data of the unresponsive queue.
According to the AXI bus-based communication method provided by the embodiment of the application, when the peripheral equipment corresponding to the current data in the unresponsive queue is idle, the current data in the unresponsive queue is preferentially processed, so that the delay of a task caused by the fact that the peripheral equipment does not respond to the current data in time is avoided.
In implementations, since the memory space of the bus is limited, the queue to be processed can only store part of the signal when the bus signal is too many.
Therefore, on the basis of the above embodiment, in this embodiment, before the step of associating the reduced address of each peripheral device with the corresponding data signal and sequentially storing the reduced address and the corresponding data signal in the pending queue, the method further includes:
Judging whether the queue to be processed is full;
If not, entering a step of associating the simplified address of each peripheral device with the corresponding data signal and storing the simplified address and the corresponding data signal in a queue to be processed in sequence;
if yes, stopping analyzing the bus signal.
According to the AXI bus-based communication method provided by the embodiment of the application, according to the storage space of the queue to be processed, the analysis of the bus signal is stopped when the queue to be processed is full, so that the system breakdown caused by excessive data is avoided.
The pending queue has a memory space limitation, and likewise, the unresponsive queue has a memory space limitation.
Therefore, on the basis of the above embodiment, in this embodiment, before the step of storing the reduced address of the peripheral device and the corresponding data signal in the unresponsive queue, the method further includes:
Judging whether the unresponsive queue is not full and the queue to be processed is not empty;
If yes, the step of storing the simplified address of the peripheral device and the corresponding data signal into an unresponsive queue is entered.
It can be understood that, in this embodiment, when the peripheral device corresponding to the current data of the queue to be processed is not in an idle state, the current data is stored in the unresponsive queue, and before the storing, it is required to determine whether the unresponsive queue has a storage space, and when the unresponsive queue is not full, the current data can be stored. And if no other data signals need to be processed in the queue to be processed, the current data also does not need to be transferred into the unresponsive queue. Of course, in other embodiments, if the peripheral device is unable to return to the idle state late, the current data may also be stored in the unresponsive queue in order to avoid affecting the processing speed of the subsequent newly added data signal.
According to the AXI bus-based communication method provided by the embodiment of the application, when the unresponsive queue is not full and the waiting queue is not empty, the current data of the waiting queue is transferred to the unresponsive queue, and under other conditions, the transfer is not performed, so that the processing amount of the data is reduced.
On the basis of the above embodiment, in this embodiment, if the data signal is a read signal, after notifying each peripheral device to execute the corresponding action, the method further includes:
And converting the data returned by the peripheral device into a read data path format of the AXI bus and outputting the read data path format to the processor.
It can be understood that when the bus signal is a write channel signal, the RAM interface signal is parsed into a write signal, and the processor implements control of peripheral devices according to the write signal. When the bus signal is a read channel signal, the read channel signal is analyzed into a RAM interface signal, the processor realizes control of peripheral equipment according to the read signal and acquires read data from the peripheral equipment, and the data needs to be converted into a read data path format of an AXI bus and can be returned to the processor through the AXI bus.
In the foregoing embodiments, the detailed description is given to the AXI bus-based communication method, and the present application further provides a corresponding embodiment of the AXI bus-based communication device. It should be noted that the present application describes an embodiment of the device portion from two angles, one based on the angle of the functional module and the other based on the angle of the hardware.
Fig. 2 is a block diagram of a communication device based on AXI bus according to an embodiment of the present application, as shown in fig. 2, where the device includes:
a receiving module 10, configured to receive a bus signal of an AXI bus, where the bus signal includes an address channel signal and a data channel signal;
the parsing module 11 is configured to parse the bus signal, convert the bus signal into a RAM interface signal, and the RAM interface signal includes an address signal and a data signal;
a conversion module 12, configured to convert address signals in the RAM interface signals into reduced addresses adapted to the peripheral devices according to the addresses of the peripheral devices;
The scheduling module 13 is configured to notify each peripheral device to perform a corresponding action according to the reduced address of each peripheral device and the corresponding data signal.
Since the embodiments of the apparatus portion and the embodiments of the method portion correspond to each other, the embodiments of the apparatus portion are referred to the description of the embodiments of the method portion, and are not repeated herein.
The communication device based on AXI bus provided by the embodiment of the application receives the bus signal through the AXI bus, the bus signal comprises the address channel signal and the data channel signal, then analyzes the bus signal, converts the bus signal into the RAM interface signal, the RAM interface signal comprises the address signal and the data signal, converts the address signal in the RAM interface signal into the reduced address adapting to each peripheral according to the address of each peripheral, and finally notifies each peripheral to execute the corresponding action according to the reduced address of each peripheral and the corresponding data signal. Compared with the prior art, the AXI bus interface needs to be additionally developed on the peripheral equipment, so that the resource waste is caused. By adopting the technical scheme, after the bus signal of the AXI bus is received, the bus signal is converted into the RAM interface signal suitable for the RAM interface, so that more peripheral devices can realize communication with the processor through the AXI bus without additionally developing the AXI bus interface, and the waste of resources is reduced. And the total address signals are converted into the simplified addresses adapting to the peripheral devices according to the addresses of the peripheral devices, so that the address signals are optimized, the size of the signals is reduced, the data can be quickly saved, and the release speed of the bus permission is improved.
Fig. 3 is a block diagram of another AXI bus-based communication device according to an embodiment of the present application, as shown in fig. 3, where the device includes:
a memory 20 for storing a computer program;
a processor 21 for implementing the steps of the AXI bus based communication method of the above embodiment when executing a computer program.
The AXI bus-based communication device provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.
Processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The Processor 21 may be implemented in at least one hardware form of a digital signal Processor (DIGITAL SIGNAL Processor, DSP), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 21 may also include a main processor and a coprocessor, the main processor being a processor for processing data in an awake state, also referred to as a central processor (Central Processing Unit, CPU); a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with an image processor (Graphics Processing Unit, GPU) for rendering and rendering of content to be displayed by the display screen. In some embodiments, the processor 21 may also include an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) processor for processing computing operations related to machine learning.
Memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used for storing a computer program 201, where the computer program, when loaded and executed by the processor 21, is capable of implementing the relevant steps of the AXI bus-based communication method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may further include an operating system 202, data 203, and the like, where the storage manner may be transient storage or permanent storage. Operating system 202 may include Windows, unix, linux, among other things. The data 203 may include, but is not limited to, address signals, data signals, reduced addresses, and the like.
In some embodiments, the AXI bus-based communication device may further include a display 22, an input/output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.
It will be appreciated by those skilled in the art that the architecture shown in fig. 3 is not limiting of AXI bus based communication devices and may include more or fewer components than shown.
The communication device based on the AXI bus provided by the embodiment of the application comprises a memory and a processor, wherein the processor can realize the following method when executing a program stored in the memory: receiving a bus signal of an AXI bus, wherein the bus signal comprises an address channel signal and a data channel signal; analyzing the bus signal, converting the bus signal into a RAM interface signal, wherein the RAM interface signal comprises an address signal and a data signal; according to the address of each peripheral device, converting the address signal in the RAM interface signal into a simplified address adapting to each peripheral device; and notifying each peripheral device to execute corresponding actions according to the reduced address of each peripheral device and the corresponding data signals.
The communication device based on AXI bus provided by the embodiment of the application receives the bus signal through the AXI bus, the bus signal comprises the address channel signal and the data channel signal, then analyzes the bus signal, converts the bus signal into the RAM interface signal, the RAM interface signal comprises the address signal and the data signal, converts the address signal in the RAM interface signal into the reduced address adapting to each peripheral according to the address of each peripheral, and finally notifies each peripheral to execute the corresponding action according to the reduced address of each peripheral and the corresponding data signal. Compared with the prior art, the AXI bus interface needs to be additionally developed on the peripheral equipment, so that the resource waste is caused. By adopting the technical scheme, after the bus signal of the AXI bus is received, the bus signal is converted into the RAM interface signal suitable for the RAM interface, so that more peripheral devices can realize communication with the processor through the AXI bus without additionally developing the AXI bus interface, and the waste of resources is reduced. And the total address signals are converted into the simplified addresses adapting to the peripheral devices according to the addresses of the peripheral devices, so that the address signals are optimized, the size of the signals is reduced, the data can be quickly saved, and the release speed of the bus permission is improved.
Finally, the application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps as described in the method embodiments above.
It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium for performing all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RandomAccess Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The computer readable storage medium provided by the embodiment of the application receives a bus signal through an AXI bus, wherein the bus signal comprises an address channel signal and a data channel signal, then analyzes the bus signal, converts the bus signal into a RAM interface signal, the RAM interface signal comprises an address signal and a data signal, converts the address signal in the RAM interface signal into a reduced address adapted to each peripheral according to the address of each peripheral, and finally notifies each peripheral to execute a corresponding action according to the reduced address of each peripheral and the corresponding data signal. Compared with the prior art, the AXI bus interface needs to be additionally developed on the peripheral equipment, so that the resource waste is caused. By adopting the technical scheme, after the bus signal of the AXI bus is received, the bus signal is converted into the RAM interface signal suitable for the RAM interface, so that more peripheral devices can realize communication with the processor through the AXI bus without additionally developing the AXI bus interface, and the waste of resources is reduced. And the total address signals are converted into the simplified addresses adapting to the peripheral devices according to the addresses of the peripheral devices, so that the address signals are optimized, the size of the signals is reduced, the data can be quickly saved, and the release speed of the bus permission is improved.
The communication method, the device and the medium based on the AXI bus provided by the application are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (9)
1. A method of AXI bus-based communication, comprising:
Receiving a bus signal of an AXI bus, the bus signal including an address channel signal and a data channel signal;
Analyzing the bus signal, and converting the bus signal into a RAM interface signal, wherein the RAM interface signal comprises an address signal and a data signal;
simplifying the total address signal according to the address of each peripheral device, converting the total address signal with larger bit width into a simplified address which is suitable for each peripheral device, so that the simplified address and the data signal are stored on a bus together;
notifying each peripheral device to execute a corresponding action according to the reduced address of each peripheral device and the corresponding data signal;
After the step of converting the address signals to the reduced address, further comprising:
associating the simplified address of each peripheral device with the corresponding data signal, and storing the simplified address and the corresponding data signal in a queue to be processed in sequence;
further, said notifying each of said peripheral devices to perform a corresponding action based on said reduced address of each of said peripheral devices and corresponding said data signal comprises:
And notifying each peripheral device to execute corresponding actions according to the reduced address and the sequence of the corresponding data signals in the to-be-processed queue.
2. The AXI bus-based communication method of claim 1, further including, prior to said step of notifying each of said peripheral devices to perform a corresponding action in an order of said pending queues according to said reduced address and corresponding said data signal:
judging whether the peripheral equipment corresponding to the current data of the queue to be processed is in an idle state or not;
If yes, entering a step of informing the peripheral equipment to execute corresponding actions according to the reduced address and the sequence of the corresponding data signals in the to-be-processed queue;
If not, storing the simplified address of the peripheral device and the corresponding data signal into an unresponsive queue.
3. The AXI bus-based communication method of claim 2, further including:
If the peripheral equipment corresponding to the reduced address and the corresponding data signal in the non-response queue is detected to be in an idle state, the reduced address and the corresponding data signal in the non-response queue are preferentially executed.
4. The AXI bus-based communication method of claim 1, wherein said step of associating said reduced address of each said peripheral device with a corresponding said data signal, sequentially storing said reduced address and corresponding said data signal in a pending queue, further includes:
Judging whether the queue to be processed is full;
If not, entering a step of associating the simplified address of each peripheral device with the corresponding data signal and storing the simplified address and the corresponding data signal in a queue to be processed in sequence;
if yes, stopping analyzing the bus signal.
5. The AXI bus based communication method of claim 2, further including, prior to said step of storing said reduced address and corresponding said data signals of said peripheral device in an unresponsive queue:
Judging whether the unresponsive queue is not full and the queue to be processed is not empty;
If yes, the step of storing the simplified address of the peripheral device and the corresponding data signal into an unresponsive queue is entered.
6. The AXI bus-based communication method according to any one of claims 1 to 5, wherein if said data signal is a read signal, after said step of notifying each of said peripheral devices to perform a corresponding action, further comprising:
And converting the data returned by the peripheral equipment into a read data path format of the AXI bus and outputting the read data path format to a processor.
7. An AXI bus-based communication device, comprising:
The receiving module is used for receiving bus signals of the AXI bus, wherein the bus signals comprise address channel signals and data channel signals;
The analysis module is used for analyzing the bus signal, converting the bus signal into a RAM interface signal, wherein the RAM interface signal comprises an address signal and a data signal;
The conversion module is used for simplifying the total address signals according to the addresses of the peripheral devices, converting the total address signals with larger bit width into simplified addresses suitable for the peripheral devices, and storing the simplified addresses and the data signals on a bus together; after the address signals are converted into the reduced addresses, associating the reduced addresses of the peripheral devices with the corresponding data signals, and sequentially storing the reduced addresses and the corresponding data signals in a queue to be processed;
and the scheduling module is used for notifying each peripheral device to execute corresponding actions according to the reduced address of each peripheral device and the sequence of the corresponding data signals in the to-be-processed queue.
8. An AXI bus-based communication device, comprising a memory for storing a computer program;
processor for implementing the steps of the AXI bus based communication method according to any one of claims 1 to 6 when executing the computer program.
9. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the AXI bus based communication method according to any of claims 1 to 6.
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