CN109445753B - Data acquisition and active synchronous framing system based on interactive caching technology - Google Patents
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Abstract
A data acquisition and active synchronous framing system based on an interactive cache technology relates to the field of data communication; the system comprises n sensors, a collector and a data acquisition synthesizer; n is a positive integer greater than 0; the collector comprises a power supply module, a first data buffer area and a second data buffer area; the invention adopts ping-pong interactive caching technology, solves the problem of pointer offset of a data caching area caused by the inconsistency of the data acquisition rate and the data transmission rate of a heterogeneous clock, avoids data coverage or repeated transmission, and realizes the pipeline processing of seamless buffering and real-time access of data stream; the accumulation of time errors of a different source clock is actively eliminated through a data synchronization signal, and address pointers of a current sending data area and a current storage area are synchronized in each cache period, so that the offset of the pointers of the cache area caused by asynchronous data transmission is avoided; data coverage or repeated sending is avoided, and the pipelined processing of seamless buffering and real-time access of data streams is realized.
Description
Technical Field
The invention relates to the field of data communication, in particular to a data acquisition and active synchronous framing system based on an interactive cache technology.
Background
In the development and test flight of aircrafts such as spacecrafts, carrier rockets and the like, the data acquisition and transmission system is used for acquiring working state parameters and environmental data of each system in the aircrafts, and provides a basis for evaluating the performance of the aircrafts and analyzing faults. The performance of the data acquisition and transmission system directly affects the development process and cost of the aircraft, and the improvement and improvement of the performance of the aircraft.
In a distributed data acquisition and transmission architecture, different clocks are respectively adopted for data acquisition of an acquisition device and data transmission of a data acquisition synthesizer, errors caused by a heterogeneous clock can not cause data acquisition and transmission errors in a short time, but in the long-time data acquisition and transmission process, the errors caused by the heterogeneous clock can cause the pointer of a data cache region to be offset, so that the data output by the acquisition device is covered or repeatedly transmitted; too long distance between the collector and the data acquisition synthesizer can cause the data acquisition synthesizer not to sample at the optimal time of the data output by the collector, and the code element offset improves the data transmission error rate.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a data acquisition and active synchronous framing system based on an interactive cache technology, which solves the problem of pointer offset of a buffer area for acquiring data and transmitting data of a heterogeneous clock, avoids data coverage or repeated transmission, and realizes pipeline processing of seamless buffering and real-time access of data streams.
The above purpose of the invention is realized by the following technical scheme:
a data acquisition and active synchronous framing system based on ping-pong interactive caching technology comprises n sensors, an acquisition unit and a data acquisition synthesizer; n is a positive integer greater than 0; the collector comprises a power supply module, a first data buffer area and a second data buffer area;
a sensor: receiving power supply of a power supply module; converting the measured physical parameters of the measured object into analog electric signals and outputting the analog electric signals to a first data buffer area and a second data buffer area;
a power supply module: supplying power to the n sensors;
a first data buffer: receiving a data synchronization instruction transmitted by a data acquisition synthesizer, and setting the address of a first data buffer zone to zero; in the ith period, receiving n analog electric signals transmitted by n sensors; sequentially filtering, amplifying and A/D converting each analog electric signal to generate n digital quantity signals; performing time sequence control on the n digital quantity signals according to preset logic to obtain n sequenced digital quantity signals; storing the n sequenced digital quantity signals according to a pre-arranged sequence; receiving a reading clock transmitted by the data acquisition synthesizer, and transmitting the stored n sequenced digital quantity signals to the data acquisition synthesizer; simultaneously generating a fetch clock; sending the access clock to a data acquisition synthesizer; i is an odd number of 1 or more;
a second data buffer: receiving a data synchronization instruction transmitted by the data acquisition synthesizer, and setting the address of the second data buffer zone to zero; in the (i + 1) th period, receiving n analog electric signals transmitted by n sensors; sequentially filtering, amplifying and A/D converting each analog electric signal to generate n digital quantity signals; performing time sequence control on the n digital quantity signals according to preset logic to obtain n sequenced digital quantity signals; storing the n sequenced digital quantity signals according to a pre-arranged sequence; receiving a reading clock transmitted by the data acquisition synthesizer, and transmitting the stored n sequenced digital quantity signals to the data acquisition synthesizer; simultaneously generating a fetch clock; sending the access clock to a data acquisition synthesizer; i is an odd number of 1 or more;
a data acquisition synthesizer: sending a data synchronization instruction to a first data buffer and a second data buffer; sending a reading clock to the first data buffer and the second data buffer; receiving n sequenced digital quantity signals transmitted from a first data buffer area and a second data buffer area; receiving access clocks transmitted from the first data buffer area and the second data buffer area; comparing the fetching clock with the reading clock to generate a latched digital quantity signal; and converting the latched digital quantity signal into a serial signal and sending the serial signal to an external modulation transmitting device.
In the above data acquisition and active synchronization framing system based on the ping-pong interaction caching technology, the n sensors include four types, namely a temperature sensor, an impact sensor, a vibration sensor and a pressure sensor; the temperature sensor measures the temperature of a measured object; the impact sensor measures and obtains the impact acceleration of the measured object; the vibration sensor measures and obtains the vibration acceleration of the measured object; the pressure sensor measures the pressure of the measured object.
In the above data acquisition and active synchronization framing system based on the ping-pong interaction caching technology, the voltage of the analog electrical signal generated by the sensor is greater than 0V and less than or equal to 5V.
In the data acquisition and active synchronous framing system based on the ping-pong interaction caching technology, the predetermined logic is to sequence the data according to the temperature digital quantity signal, the impact acceleration digital quantity signal, the vibration acceleration digital quantity signal and the pressure digital quantity signal in sequence.
In the data acquisition and active synchronous framing system based on the ping-pong interaction cache technology, the pre-arrangement sequence is the sequence of the sequenced temperature digital quantity signal, the sequenced impact acceleration digital quantity signal, the sequenced vibration acceleration digital quantity signal and the sequenced pressure digital quantity signal in sequence.
In the above data acquisition and active synchronization framing system based on ping-pong interaction caching technology, the frequency of the fetch clock is the same as the frequency of the reading clock.
In the data acquisition and active synchronous framing system based on the ping-pong interaction caching technology, the data sending addresses of the first data buffer area and the first data buffer area are set to be zero, so that the first data buffer area and the second data buffer area receive or send data at the same time and at the same address.
In the above data acquisition and active synchronization framing system based on the ping-pong interaction caching technology, the method for comparing the reading clock with the access clock by the data acquisition synthesizer is as follows: when the phases of the reading clock and the fetching clock are consistent, the sequenced digital quantity signals are latched by the falling edge of the reading clock to generate latched digital quantity signals; and when the phases of the reading clock and the fetching clock are not consistent, the sequenced digital quantity signals are latched by the falling edge of the fetching clock pulse.
Compared with the prior art, the invention has the following advantages:
(1) the invention adopts ping-pong interactive caching technology, solves the problem of pointer offset of a data caching area caused by the inconsistency of the data acquisition rate and the data transmission rate of a heterogeneous clock, avoids data coverage or repeated transmission, and realizes the pipeline processing of seamless buffering and real-time access of data stream;
(2) the invention actively eliminates the time error accumulation of the heterogeneous clock through the data synchronization signal, synchronizes the address pointers of the current sending data area and the storage area in each cache period, and avoids the offset of the cache area pointers caused by asynchronous data transmission;
(3) the invention designs a module for eliminating clock phase reversal to latch data, solves the problem of reading clock phase reversal caused by overlong distance of a data acquisition system, avoids code element bias caused by data transmission and reduces the error rate of data transmission;
(4) the invention adds the preset insert words into the data frame format, strengthens the data integrity judgment criterion by detecting the preset insert words at the appointed positions, avoids the phenomenon that the data is insufficient and abnormal phenomena are not found, and improves the accuracy rate of judging the data integrity.
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FIG. 1 is a schematic diagram of a data acquisition and active synchronization framing system according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the following figures and specific examples:
the invention adopts ping-pong interactive caching technology to actively eliminate the time error accumulation of the heterogeneous clock, designs the access clock to latch the data, solves the problem of pointer offset of a data cache region caused by the inconsistency of the data acquisition rate and the data transmission rate of the heterogeneous clock, realizes the pipeline processing of seamless buffering and real-time access of data flow, and reduces the error rate of data transmission.
As shown in fig. 1, which is a schematic diagram of a data acquisition and active synchronous framing system, it can be known that a data acquisition and active synchronous framing system based on a ping-pong interaction caching technology includes n sensors, an acquisition unit and a data acquisition synthesizer; n is a positive integer greater than 0; the collector comprises a power supply module, a first data buffer area and a second data buffer area; the n sensors comprise four types of temperature sensors, impact sensors, vibration sensors and pressure sensors; the temperature sensor measures the temperature of a measured object; the impact sensor measures and obtains the impact acceleration of the measured object; the vibration sensor measures and obtains the vibration acceleration of the measured object; the pressure sensor measures the pressure of the measured object.
A sensor: receiving power supply of a power supply module; converting the measured physical parameters of the measured object into analog electric signals and outputting the analog electric signals to a first data buffer area and a second data buffer area; the voltage of the analog electric signal is greater than 0V and less than or equal to 5V.
A power supply module: and supplying power to the n sensors.
A first data cache region and a second data cache region which are independent of each other are configured inside the collector, and in a first cache period, an input data stream is cached into the first data cache region; in the second cache cycle, through the switching of the input data selection unit, the input data stream is cached to the second data cache region, and meanwhile, the data previously stored in the first data cache region is sent to a subsequent module through the output data selection unit for processing; in the third cache cycle, switching the data input and output data selection unit again, caching the input data stream to the first data cache region, and simultaneously sending the data previously stored in the second data cache region to a subsequent module for processing through the output data selection unit; and then, repeatedly carrying out alternate switching operation according to the flow.
A first data buffer: receiving a data synchronization instruction transmitted by a data acquisition synthesizer, and setting the address of a first data buffer zone to zero; in the ith period, receiving n analog electric signals transmitted by n sensors; sequentially filtering, amplifying and A/D converting each analog electric signal to generate n digital quantity signals; performing time sequence control on the n digital quantity signals according to preset logic to obtain n sequenced digital quantity signals; the preset logic is that the temperature digital quantity signal, the impact acceleration digital quantity signal, the vibration acceleration digital quantity signal and the pressure digital quantity signal are sequentially sequenced. Storing the n sequenced digital quantity signals according to a pre-arranged sequence; the prearranged sequence is the sequence of the sequenced temperature digital quantity signal, the sequenced impact acceleration digital quantity signal, the sequenced vibration acceleration digital quantity signal and the sequenced pressure digital quantity signal in turn. Receiving a reading clock transmitted by the data acquisition synthesizer, and transmitting the stored n sequenced digital quantity signals to the data acquisition synthesizer; simultaneously generating a fetch clock; sending the access clock to a data acquisition synthesizer; i is an odd number of 1 or more.
A second data buffer: receiving a data synchronization instruction transmitted by the data acquisition synthesizer, and setting the address of the second data buffer zone to zero; the address of the first data buffer and the address of the first data buffer for sending data are set to zero, so that the first data buffer and the second data buffer can receive or send data at the same address at the same time. In the (i + 1) th period, receiving n analog electric signals transmitted by n sensors; sequentially filtering, amplifying and A/D converting each analog electric signal to generate n digital quantity signals; performing time sequence control on the n digital quantity signals according to preset logic to obtain n sequenced digital quantity signals; storing the n sequenced digital quantity signals according to a pre-arranged sequence; receiving a reading clock transmitted by the data acquisition synthesizer, and transmitting the stored n sequenced digital quantity signals to the data acquisition synthesizer; simultaneously generating a fetch clock; the frequency of the fetch clock is the same as the frequency of the read clock. Sending the access clock to a data acquisition synthesizer; i is an odd number of 1 or more.
The collector eliminates the time error accumulation of the crystal oscillator of the data acquisition synthesizer and the crystal oscillator of the collector according to the received data synchronization signal, resets and clears the address pointers of the first data cache region and the second data cache region together after detecting the rising edge of the data synchronization signal, synchronizes the address pointers of the current data sending region and the current storage region in each cache period, selects the proper first data cache region and the proper second data cache region as the current storage region and the sending region for acquiring data, and clears the data of the data sending cache region after the data sending is finished; when the collector outputs data, the data acquisition clock which is synchronous with the phase of the data and has the same code rate is simultaneously output, and the frequency of the data acquisition clock is the same as that of the reading clock.
The collector utilizes a data synchronization instruction to actively eliminate the time error accumulation of a heterogeneous clock at regular time, and resets and clears the address pointers of the current data sending area and the current storage area in each cache period, and the specific working flow is as follows:
firstly, a data acquisition synthesizer sends data synchronization signals to an acquisition device at regular time according to a self crystal oscillator clock in each working period;
secondly, the collector judges whether the first cache cycle is the first cache cycle, if the first cache cycle is the first cache cycle, the collector eliminates the time error accumulation of the crystal oscillator of the data acquisition synthesizer and the crystal oscillator of the collector according to the received data synchronization signal, after the collector detects the rising edge of the data synchronization signal, the collector resets and clears the address pointers of the first data cache region and the second data cache region together, at the moment, the first data cache region is used as the storage region of the current acquired data, and the collector does not output the data;
thirdly, in each cache cycle after the second cache cycle, the collector eliminates the time error accumulation of the crystal oscillator and the crystal oscillator of the data acquisition synthesizer according to the received data synchronization signal, after the rising edge of the data synchronization signal is detected, the address pointers of the first data cache region and the second data cache region are reset and cleared together, the data capacity of the first data cache region and the data capacity of the second data cache region are judged at the same time, if data exist in the data cache 1 and the second data cache region does not have the data, the first data cache region is selected as a sending region of the current data, the second data cache region is selected as a storage region of the current data, and the data of the first data cache region is cleared after the data sending is finished; if the data buffer 1 has no data and the second data buffer area has data, the second data buffer area is selected as a sending area of the current data, the first data buffer area is selected as a storage area of the current collected data, and the data in the second data buffer area is emptied after the data sending is finished.
A data acquisition synthesizer: sending a data synchronization instruction to a first data buffer and a second data buffer; sending a reading clock to the first data buffer and the second data buffer; receiving n sequenced digital quantity signals transmitted from a first data buffer area and a second data buffer area; receiving access clocks transmitted from the first data buffer area and the second data buffer area; comparing the fetching clock with the reading clock, and latching the sequenced digital quantity signals by the falling edge of the reading clock when the phases of the reading clock and the fetching clock are consistent to generate latched digital quantity signals; when the phases of the reading clock and the fetching clock are not consistent, the sequenced digital quantity signals are latched by the falling edge of the fetching clock pulse; generating a latched digital quantity signal; and converting the latched digital quantity signal into a serial signal and sending the serial signal to an external modulation transmitting device.
The data acquisition synthesizer controls the time sequence of the acquisition device through the control bus, compares the phase of the reading clock generated by the crystal oscillator with the phase of the acquisition clock after receiving the acquisition clock, selects the falling edge of the reading clock or the acquisition clock pulse to latch data, reads the output data of the acquisition device at the moment, frames the data according to a specified format, converts the parallel signals into serial signals and outputs the serial signals to the modulation and transmission equipment, and eliminates the clock phase reversal module.
The data acquisition synthesizer of the invention designs a fetch clock to latch data, and the specific process of eliminating the clock phase reversal module is as follows:
after receiving the access clock, the data acquisition synthesizer compares the phases of the reading clock and the access clock generated by the crystal oscillator, if the phases of the reading clock and the access clock are consistent, the data is latched on the falling edge of the reading clock pulse, the output data of the acquisition device at the moment is read, 8-bit data is synthesized into 1 byte, the high bit of the byte is transmitted firstly and the low bit of the byte is transmitted secondly in transmission, and then the continuous bytes are framed for data according to a specified format; if the phases of the reading clock and the fetching clock are not consistent, data are latched on the falling edge of the fetching clock pulse, the output data of the collector at the moment are read, 8-bit data are combined into 1 byte, the high bit of the byte is transmitted firstly and the low bit of the byte is transmitted secondly finally during transmission, and then the continuous bytes are framed for data framing according to a specified format and the data is framed according to a specified format.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Claims (5)
1. A data acquisition and active synchronization framing system based on ping-pong interaction caching technology is characterized in that: the system comprises n sensors, a collector and a data acquisition synthesizer; n is a positive integer greater than or equal to 4; the collector comprises a power supply module, a first data buffer area and a second data buffer area;
a sensor: receiving power supply of a power supply module; converting the measured physical parameters of the measured object into analog electric signals and outputting the analog electric signals to a first data buffer area and a second data buffer area;
a power supply module: supplying power to the n sensors;
a first data buffer: receiving a data synchronization instruction transmitted by a data acquisition synthesizer, and setting the address of a first data buffer zone to zero; in the ith period, receiving n analog electric signals transmitted by n sensors; sequentially filtering, amplifying and A/D converting each analog electric signal to generate n digital quantity signals; performing time sequence control on the n digital quantity signals according to preset logic to obtain n sequenced digital quantity signals; storing the n sequenced digital quantity signals according to a pre-arranged sequence; receiving a reading clock transmitted by the data acquisition synthesizer, and transmitting the stored n sequenced digital quantity signals to the data acquisition synthesizer; simultaneously generating a fetch clock; sending the access clock to a data acquisition synthesizer; i is an odd number of 1 or more;
a second data buffer: receiving a data synchronization instruction transmitted by the data acquisition synthesizer, and setting the address of the second data buffer zone to zero; in the (i + 1) th period, receiving n analog electric signals transmitted by n sensors; sequentially filtering, amplifying and A/D converting each analog electric signal to generate n digital quantity signals; performing time sequence control on the n digital quantity signals according to preset logic to obtain n sequenced digital quantity signals; storing the n sequenced digital quantity signals according to a pre-arranged sequence; receiving a reading clock transmitted by the data acquisition synthesizer, and transmitting the stored n sequenced digital quantity signals to the data acquisition synthesizer; simultaneously generating a fetch clock; sending the access clock to a data acquisition synthesizer; i is an odd number of 1 or more;
a data acquisition synthesizer: sending a data synchronization instruction to a first data buffer and a second data buffer; sending a reading clock to the first data buffer and the second data buffer; receiving n sequenced digital quantity signals transmitted from a first data buffer area and a second data buffer area; receiving access clocks transmitted from the first data buffer area and the second data buffer area; comparing the fetching clock with the reading clock to generate a latched digital quantity signal; converting the latched digital quantity signal into a serial signal and sending the serial signal to external modulation transmitting equipment;
the n sensors comprise four types of temperature sensors, impact sensors, vibration sensors and pressure sensors; the temperature sensor measures the temperature of a measured object; the impact sensor measures and obtains the impact acceleration of the measured object; the vibration sensor measures and obtains the vibration acceleration of the measured object; the pressure sensor measures the pressure of the measured object;
the preset logic is that the temperature digital quantity signal, the impact acceleration digital quantity signal, the vibration acceleration digital quantity signal and the pressure digital quantity signal are sequentially sequenced;
the prearranged sequence is the sequence of the sequenced temperature digital quantity signal, the sequenced impact acceleration digital quantity signal, the sequenced vibration acceleration digital quantity signal and the sequenced pressure digital quantity signal in sequence.
2. The ping-pong interaction caching technology based data acquisition and active synchronization framing system as claimed in claim 1, wherein: the voltage of the analog electric signal generated by the sensor is greater than 0V and less than or equal to 5V.
3. The ping-pong interaction caching technology based data acquisition and active synchronization framing system as claimed in claim 2, wherein: the frequency of the fetching clock is the same as that of the reading clock.
4. The ping-pong interaction caching technology based data acquisition and active synchronization framing system as claimed in claim 3, wherein: the address of the first data buffer and the address of the first data buffer for sending data are set to zero, so that the first data buffer and the second data buffer can receive or send data at the same address at the same time.
5. The ping-pong interaction caching technology based data acquisition and active synchronization framing system as claimed in claim 4, wherein: the method for comparing the reading clock with the access clock by the data acquisition synthesizer comprises the following steps: when the phases of the reading clock and the fetching clock are consistent, the sequenced digital quantity signals are latched by the falling edge of the reading clock to generate latched digital quantity signals; and when the phases of the reading clock and the fetching clock are not consistent, the sequenced digital quantity signals are latched by the falling edge of the fetching clock pulse.
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| CN111555791B (en) * | 2020-03-31 | 2022-04-08 | 北京控制工程研究所 | High-reliability high-frequency satellite wireless data acquisition system and method |
| CN112073460B (en) * | 2020-08-03 | 2022-08-09 | 国网山东省电力公司电力科学研究院 | Data acquisition unit, data transmission method and comprehensive energy monitoring system |
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