CN101175225A - Test system of digital video data and semiconductor device - Google Patents
Test system of digital video data and semiconductor device Download PDFInfo
- Publication number
- CN101175225A CN101175225A CNA2007101666452A CN200710166645A CN101175225A CN 101175225 A CN101175225 A CN 101175225A CN A2007101666452 A CNA2007101666452 A CN A2007101666452A CN 200710166645 A CN200710166645 A CN 200710166645A CN 101175225 A CN101175225 A CN 101175225A
- Authority
- CN
- China
- Prior art keywords
- mentioned
- code
- video data
- digital video
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
- H04N17/04—Diagnosis, testing or measuring for television systems or their details for receivers
- H04N17/045—Self-contained testing apparatus
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
- H04N17/004—Diagnosis, testing or measuring for television systems or their details for digital television systems
Landscapes
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Biomedical Technology (AREA)
- General Health & Medical Sciences (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
Abstract
The digital video data test system includes a semiconductor device to be tested and a digital video data test device. In the semiconductor device, a clock frequency division section divides the frequency of a digital video clock to generate a frequency-divided clock. A timing signal generation section generates a timing signal synchronizing with the frequency-divided clock using a sync signal in digital video data. A code holding section outputs a generated code generated by a code generation section to the digital video data test device in synchronization with the timing signal and the frequency-divided clock. A method for generating various signals to be supplied from a semiconductor device to a digital video data test device is specifically established.
Description
Technology neck field
The test system of digital video data that the present invention relates to the semiconductor device of fast acquisition of digital video data and detect its electric fault.
Background technology
In TOHKEMY 2006-128905 communique, as in the past test system of digital video data and testing apparatus following technology being disclosed: generates by the well-determined generated code of digital of digital video data (generated code) in the inside of the semiconductor device that becomes tested object, in the inside of above-mentioned semiconductor device or outside by above-mentioned generated code and expected value code are compared the test of carrying out above-mentioned semiconductor device.
Figure 16 is the integrally-built block diagram of the existing test system of digital video data of expression.
In Figure 16, the 19th, the flow data generating means of output stream data 26.The 4th, become the semiconductor device of tested object, portion comprises and handles flow data 26 and generate the Video Decoder 18 of digital of digital video data 2 and generate sign indicating number generating unit 11 by above-mentioned digital of digital video data 2 well-determined generated codes within it.
In addition, the 1st, the digital of digital video data testing apparatus comprises that image according to above-mentioned digital of digital video data 2 expressions of above-mentioned generated code 21 tests the image change point test section 14 of situation that timeliness changes and output image change point detection signal 22 has taken place, stored the desired value storage part 12 of expected value code 24 and the comparing section 13 that above-mentioned generated code 21 and above-mentioned expected value code 24 is compared and keep or export this comparative result 3.
Below, the method for testing of the digital of digital video data that adopted above-mentioned digital of digital video data testing apparatus is described.
At first, to the flow data 26 of semiconductor device 4 inputs, in Video Decoder 18, handle and output digital video data 2 from 19 outputs of flow data generating means.Then, generate generated code 21, from the above-mentioned generated code 21 of above-mentioned semiconductor device 4 outputs by sign indicating number generating unit 11.
Then, to the above-mentioned generated code 21 of digital of digital video data testing apparatus 1 input, and be input to image change point test section 14 and comparing section 13.In above-mentioned image change point test section 14, observe the timeliness of above-mentioned generated code 21 change, the moment output image change point detection signal 22 that changes has taken place and be input to above-mentioned comparing section 13 at image.And input has the expected value code 24 that is stored in desired value storage part 12 in above-mentioned comparing section 13.
And in above-mentioned comparing section 13, more above-mentioned successively generated code 21 and above-mentioned expected value code 24 keep or export its comparative result 3 to the outside.
Figure 17 is the integrally-built block diagram of existing another test system of digital video data of expression.
Existing another digital video test macro shown in Figure 17 only is with the difference of the existing test system of digital video data of Figure 16: comprise in the inside of digital of digital video data testing apparatus 1 storage moment of beginning to test designated code 23 designated code storage part 15 and detect the whether consistent situation of generated code 21 and designated code 23 and export the designated code test section 16 of designated code detection signal 25.Other structures are the same with the existing test system of digital video data of Figure 16, therefore omit its explanation.
In the test system of digital video data of Figure 17, employing replaces the image change point test signal 22 of Figure 16, more above-mentioned successively generated code 21 and above-mentioned expected value code 24 in above-mentioned comparing section 13 by designated code storage part 15 detecting designated code 23 and the designated code detection signal 25 that the 21 consistent moment of generated code export.
Figure 18 and Figure 19 are the integrally-built block diagrams of the existing another test system of digital video data of expression.
The difference of the test system of digital video data of Figure 18 and test system of digital video data shown in Figure 19 and Figure 16 and Figure 17 only is: digital of digital video data testing apparatus 1 is included in the inside of semiconductor device 5.Other structures are identical with the digital video test macro of Figure 16 and Figure 17, therefore omit its explanation.
Yet, in Figure 16 and existing test system of digital video data shown in Figure 17, need clearly determine to make the generated code 21 low speed output that generates by sign indicating number generating unit 11 method, generate and be used to make the clock signal of digital of digital video data testing apparatus 1 action and the method for various timing signals.
In addition, need regularly carry out initialization by each test to sign indicating number generating unit 11, but in the past, carry out initialization with fixed value, therefore there is following problem, the digital of digital video data 2 in needed 1 cycle of initialization is not reflected in the next generated code 21, the mistake that can not test digital of digital video data 2 when the mistake of digital of digital video data 2 is consistent with initialization timing.
And then, for the detected image change point, needing to generate with the video field is the generated code 21 of unit, detected image change point or carry out comparison with designated code, so the video field that need carry out with low precision is the comparison of the above-mentioned generated code 21 of unit, perhaps determine with the unit littler than video field unit based on the detection method for testing of the image change point of above-mentioned generated code or the designation method of above-mentioned designated code.
And, in Figure 18 and test system of digital video data shown in Figure 19, need special circuit be installed in the inside of semiconductor device 5, so be expected to reduce the special circuit area.
For example, when the generated code 21 that regularly generated by test and desired value 24 are compared, need be used for temporarily keeping in advance the memory element of " generated code length * digital of digital video data highway width " big or small data, be 16 in generated code length, when the digital of digital video data highway width is 30, need the memory element of " 16 * 30=480 position ".
Summary of the invention
The objective of the invention is to clearly to determine the generation method of the various signals that the semiconductor device from test system of digital video data provides to the digital of digital video data testing apparatus.
In addition, another purpose is and can as required measuring accuracy, testing time sets test cell neatly.
And, the increase of the circuit area when another purpose is to reduce to the semiconductor device installation testing that becomes tested object with special circuit.
In order to achieve the above object, the present invention adopts and in the inside of semiconductor device clock division portion is set newly, the structure of the frequency-dividing clock of exportable low speed, generated code and timing signal.
Above-mentioned clock division portion regularly carries out initialization to the phase place of above-mentioned frequency-dividing clock by measuring unit, and makes and do not produce the pulse signal shorter than the half period of above-mentioned frequency-dividing clock, thereby the length of measuring unit is not limited to the length of above-mentioned frequency-dividing clock arbitrarily.
In addition, the sign indicating number generating unit has is regularly synchronously using the value of the digital of digital video data that has reflected initialization timing to carry out initialized sign indicating number generating unit initialization section during initialization with test, even also can carry out error detection under the consistent situation of initialization timing and wrong timing.
And, generating regularly by the sign indicating number of each digital of digital video data that staggers, dual-purpose temporarily keeps the memory element of usefulness between each digital video data signal, carries out the reduction significantly of memory element.
And, also have regularly will be regularly relative by the border, field with the border, field the initialized test timing of test phase place regularly initialization section, can compare the expected value code of data length arbitrarily.
And, also have the situation that generated code test pattern that use regularly generates by test changes image change point test section, detect designated code test section with the specified field of designated code, can determine to begin to test from the generated code that is regularly generated by test.
And, use is installed in the built-in miniature computer in the semiconductor device, execution is read in or the comparison of generated code and expected value code or read in and compare both from the expected value code of exterior storage element, thereby reduces the special circuit that will be installed in semiconductor device.
In addition, not only semiconductor device is tested, also can be tested the substrate that semiconductor device has been installed.
And, also have expected value code input part that can long-range input expected value code and carry out the test control part of test, but become the system of autodiagnosis in the timing of appointment.
Particularly, test system of digital video data of the present invention is characterized in that, comprises semiconductor device and digital of digital video data testing apparatus, and above-mentioned semiconductor device comprises the sign indicating number generating unit of generation by the well-determined generated code of digital of digital video data that is transfused to; The clock division portion of the frequency-dividing clock behind the frequency division is carried out in generation to clock; Use the synchronizing signal of above-mentioned digital of digital video data to generate timing signal generating unit with the synchronous timing signal of above-mentioned frequency-dividing clock; And synchronously export the sign indicating number maintaining part of above-mentioned generated code with above-mentioned timing signal and above-mentioned frequency-dividing clock, above-mentioned semiconductor device is exported above-mentioned timing signal, above-mentioned generated code and above-mentioned frequency-dividing clock to the outside, above-mentioned digital of digital video data testing apparatus receives timing signal, generated code and the frequency-dividing clock from above-mentioned semiconductor device, comprise image change point test section, analyze the image change point that detects the represented image time of origin variation of above-mentioned digital of digital video data by the above-mentioned sign indicating number generated code that generating unit generated; The desired value storage part, the storage expected value code; And comparing section, from testing the moment of above-mentioned image change point, beginning above-mentioned generated code and above-mentioned expected value code are compared, above-mentioned digital of digital video data testing apparatus is handled above-mentioned generated code and is tested above-mentioned semiconductor device.
In an embodiment of test system of digital video data of the present invention, above-mentioned semiconductor device also has at each carries out initialized phase place initialization section by the determined specific timing of above-mentioned timing signal to the phase place of above-mentioned frequency-dividing clock, the signal level during at least half clock cycle of above-mentioned phase place initialization section after with the firm initialization of above-mentioned frequency-dividing clock be set at be about to initialization before the identical level of signal level.
In an embodiment of test system of digital video data of the present invention, above-mentioned semiconductor device also has with above-mentioned timing signal synchronously carries out initialized sign indicating number generating unit initialization section to above-mentioned sign indicating number generating unit, and above-mentioned sign indicating number generating unit initialization section is carried out initialization with the initial value that has reflected the digital of digital video data in the initialization cycle to above-mentioned sign indicating number generating unit.
In an embodiment of test system of digital video data of the present invention, above-mentioned semiconductor device also has the generated code maintaining part that keeps above-mentioned generated code during till export above-mentioned generated code, above-mentioned generated code maintaining part, when having a plurality of above-mentioned sign indicating number generating unit, the generated code that synchronously keeps each yard generating unit to generate successively with above-mentioned timing signal and above-mentioned sub-frequency clock signal.
In an embodiment of test system of digital video data of the present invention, above-mentioned semiconductor device also has regularly initialization section of test, each indication in above-mentioned timing signal with the field be unit timing the field regularly, initialization is regularly carried out in the test generation regularly of the timing of more above-mentioned generated code of the indication in the above-mentioned timing signal and above-mentioned expected value code.
In an embodiment of test system of digital video data of the present invention, above-mentioned digital of digital video data testing apparatus also comprises a special code generating unit, and each the test timing at above-mentioned timing signal generates a special code from the above-mentioned generated code that is transfused to; An and special code comparing section, compare to field special code in the field special code that is generated by above-mentioned special code generating unit, that generate in current place with at the field special code that generates when back several second place, front court, above-mentioned comparing section begins to carry out the comparison of above-mentioned generated code and above-mentioned expected value code from detecting above-mentioned two inconsistent moment of field special code.
In an embodiment of test system of digital video data of the present invention, above-mentioned semiconductor device is installed on the substrate, transmits above-mentioned generated code from above-mentioned semiconductor device to above-mentioned digital of digital video data testing apparatus via above-mentioned substrate.
In an embodiment of test system of digital video data of the present invention, also comprise transmission arbitrarily above-mentioned expected value code the expected value code dispensing device, import the expected value code input part of above-mentioned expected value code and the test control part of carrying out test in the timing of appointment from the outside.
Test system of digital video data of the present invention is characterized in that, comprises semiconductor device and digital of digital video data testing apparatus, and above-mentioned semiconductor device comprises the sign indicating number generating unit of generation by the well-determined generated code of digital of digital video data that is transfused to; The clock division portion of the frequency-dividing clock behind the frequency division is carried out in generation to clock; Use the synchronizing signal of above-mentioned digital of digital video data to generate timing signal generating unit with the synchronous timing signal of above-mentioned frequency-dividing clock; And synchronously export the sign indicating number maintaining part of above-mentioned generated code with above-mentioned timing signal and above-mentioned frequency-dividing clock, above-mentioned semiconductor device is exported above-mentioned timing signal, above-mentioned generated code and above-mentioned frequency-dividing clock to the outside, above-mentioned digital of digital video data testing apparatus receives timing signal, generated code and the frequency-dividing clock from above-mentioned semiconductor device, comprise the designated code storage part, the storage designated code; Whether the designated code test section detects by the above-mentioned sign indicating number generated code that generating unit generated consistent with above-mentioned designated code; The desired value storage part, the storage expected value code; And comparing section, from testing out the above-mentioned generated code moment consistent, beginning above-mentioned generated code and above-mentioned expected value code are compared with above-mentioned designated code, above-mentioned digital of digital video data testing apparatus is handled above-mentioned generated code and is tested above-mentioned semiconductor device.
In an embodiment of test system of digital video data of the present invention, above-mentioned semiconductor device also is included in each and by the determined specific timing of above-mentioned timing signal the phase place of above-mentioned frequency-dividing clock is carried out initialized phase place initialization section, the signal level during at least half clock cycle of above-mentioned phase place initialization section after with the firm initialization of above-mentioned frequency-dividing clock be set at be about to initialization before the identical level of signal level.
In an embodiment of test system of digital video data of the present invention, above-mentioned semiconductor device also comprises with above-mentioned timing signal synchronously carries out initialized sign indicating number generating unit initialization section to above-mentioned sign indicating number generating unit, and above-mentioned sign indicating number generating unit initialization section is carried out initialization with the initial value of the digital of digital video data that has reflected initialization cycle to above-mentioned sign indicating number generating unit.
In an embodiment of test system of digital video data of the present invention, above-mentioned semiconductor device also comprise to output till the above-mentioned generated code during keep the generated code maintaining part of above-mentioned generated code, above-mentioned generated code maintaining part, when having a plurality of above-mentioned sign indicating number generating unit, the generated code that synchronously keeps each yard generating unit to be generated successively with above-mentioned timing signal and above-mentioned sub-frequency clock signal.
In an embodiment of test system of digital video data of the present invention, above-mentioned semiconductor device also comprises regularly initialization section of test, each indication in above-mentioned timing signal is the field timing of the timing of unit with the field, and initialization is regularly carried out in the test generation regularly of more above-mentioned generated code of the indication in the above-mentioned timing signal and above-mentioned expected value code.
In an embodiment of test system of digital video data of the present invention, above-mentioned digital of digital video data testing apparatus also comprises a special code generating unit, and each the test timing at above-mentioned timing signal generates a special code from the above-mentioned generated code that is transfused to; And specify a special code maintaining part, and keeping specifying a special code, above-mentioned comparing section begins to carry out the comparison of above-mentioned generated code and above-mentioned expected value code from detecting above-mentioned special code with the above-mentioned appointment field consistent moment of special code.
In an embodiment of test system of digital video data of the present invention, above-mentioned semiconductor device is installed on the substrate, transmits above-mentioned generated code from above-mentioned semiconductor device to above-mentioned digital of digital video data testing apparatus via above-mentioned substrate.
In an embodiment of test system of digital video data of the present invention, also comprise the transmission expected value code dispensing device of above-mentioned expected value code arbitrarily; Import the expected value code input part of above-mentioned expected value code from the outside; And the test control part of carrying out test in the timing of appointment.
Semiconductor device of the present invention is characterized in that, comprises the sign indicating number generating unit of generation by the well-determined generated code of digital of digital video data that is transfused to; The clock division portion of the frequency-dividing clock of generation after to clock division; Use the synchronizing signal of above-mentioned digital of digital video data to generate timing signal generating unit with the synchronous timing signal of above-mentioned frequency-dividing clock; Synchronously export the sign indicating number maintaining part of above-mentioned generated code with above-mentioned timing signal and above-mentioned frequency-dividing clock; Image change point test section is analyzed by the above-mentioned sign indicating number generated code that generating unit generated, and detects the image change point of the represented image time of origin variation of above-mentioned digital of digital video data; The desired value storage part of storage expected value code; Above-mentioned desired value storage part is carried out the built-in miniature computer that reads in of above-mentioned expected value code; And comparing section, from detecting the moment of above-mentioned image change point, begin above-mentioned generated code and above-mentioned expected value code are compared.
In an embodiment of semiconductor device of the present invention, above-mentioned comparing section is above-mentioned built-in miniature computer.
In an embodiment of semiconductor device of the present invention, above-mentioned comparing section is above-mentioned built-in miniature computer, and above-mentioned built-in miniature computer carries out the reading in of above-mentioned generated code and above-mentioned expected value code, to the comparison of above-mentioned generated code and above-mentioned expected value code.
Semiconductor device of the present invention is characterized in that, comprises the sign indicating number generating unit of generation by the well-determined generated code of digital of digital video data that is transfused to; Clock division portion to the frequency-dividing clock behind the clock division; Use the synchronizing signal of above-mentioned digital of digital video data to generate timing signal generating unit with the synchronous timing signal of above-mentioned frequency-dividing clock; Synchronously export the sign indicating number maintaining part of above-mentioned generated code with above-mentioned timing signal and above-mentioned frequency-dividing clock, the designated code storage part of storage designated code; The designated code test section, whether test is consistent with above-mentioned designated code by the above-mentioned sign indicating number generated code that generating unit generated; The desired value storage part of storage expected value code; Above-mentioned desired value storage part is carried out the built-in miniature computer that reads in of above-mentioned expected value code; And comparing section, consistent with above-mentioned designated code constantly from testing out above-mentioned generated code, begin above-mentioned generated code and above-mentioned expected value code are compared.
In an embodiment of semiconductor device of the present invention, above-mentioned comparing section is above-mentioned built-in miniature computer.
In an embodiment of semiconductor device of the present invention, above-mentioned comparing section is above-mentioned built-in miniature computer, and above-mentioned built-in miniature computer carries out the reading in of above-mentioned generated code and above-mentioned expected value code, to the comparison of above-mentioned generated code and above-mentioned expected value code.
Description of drawings
Fig. 1 is the integrally-built block diagram of the test system of digital video data of the first embodiment of the present invention.
Fig. 2 is the integrally-built block diagram of the test system of digital video data of the second embodiment of the present invention.
Fig. 3 A, Fig. 3 B are the schematic diagrames of clock phase relation of semiconductor device of the test system of digital video data of the second embodiment of the present invention.
Fig. 4 is the integrally-built block diagram of the test system of digital video data of the third embodiment of the present invention.
Fig. 5 is the integrally-built block diagram of the test system of digital video data of the fourth embodiment of the present invention.
Fig. 6 be the fourth embodiment of the present invention test system of digital video data generated code duplicate regularly schematic diagram.
Fig. 7 is the integrally-built block diagram of the test system of digital video data of the fifth embodiment of the present invention.
Fig. 8 is the field timing and the schematic diagram of testing position relation regularly of the test system of digital video data of the fifth embodiment of the present invention.
Fig. 9 is the integrally-built block diagram of the test system of digital video data of the sixth embodiment of the present invention.
Figure 10 is the integrally-built block diagram of the test system of digital video data of the seventh embodiment of the present invention.
Figure 11 is the integrally-built block diagram of the semiconductor device of the eighth embodiment of the present invention.
Figure 12 is the integrally-built block diagram of the semiconductor device of the ninth embodiment of the present invention.
Figure 13 is the integrally-built block diagram of the semiconductor device of the tenth embodiment of the present invention.
Figure 14 is the integrally-built block diagram of the test system of digital video data of the 11st embodiment of the present invention.
Figure 15 is the integrally-built block diagram of the test system of digital video data of the 12nd embodiment of the present invention.
Figure 16 is the integrally-built block diagram of existing test system of digital video data.
Figure 17 is the integrally-built block diagram of existing another test system of digital video data.
Figure 18 is the integrally-built block diagram of conventional semiconductor device.
Figure 19 is the integrally-built block diagram of existing another semiconductor device.
Embodiment
Below, preferred each embodiment of the present invention is described with reference to the accompanying drawings.The embodiment that goes out shown here is an example only, is not limited to this embodiment.
＜the first embodiment 〉
Fig. 1 is the integrally-built block diagram of the test system of digital video data of the expression first embodiment of the present invention.
In Fig. 1, the 19th, the flow data generating means of output stream data 26, the 4th, handle above-mentioned flow data 26 and the semiconductor device as tested object of output generated code 21, the 1st, handle above-mentioned generated code 21 and the digital of digital video data testing apparatus of test above-mentioned semiconductor device 4.Constitute test system of digital video data by above-mentioned semiconductor device 4 and above-mentioned digital of digital video data testing apparatus 1.
Above-mentioned semiconductor device 4 comprises the Video Decoder 18 of handling flow data 26 and generating digital of digital video data 2, generation is by the sign indicating number generating unit 11 of above-mentioned digital of digital video data 2 well-determined generated codes 211, digital video clock 31 frequency divisions are generated the clock division portion 30 of frequency-dividing clock 32, utilize the synchronizing signal 41 of above-mentioned digital of digital video data 2 to generate timing signal generating unit 40 with the synchronous timing signal 42 of above-mentioned frequency-dividing clock 32, and output makes the sign indicating number maintaining part 50 of the synchronous generated code 21 of above-mentioned generated code 211 and above-mentioned timing signal 42 and above-mentioned frequency-dividing clock 32.
Above-mentioned digital of digital video data testing apparatus 1 comprises to be handled above-mentioned generated code 21 and the test starting point test section (image change point test section) 100 of output test beginning timing signal 101, stores the desired value storage part 12 of expected value code 24 and the comparing section 13 that above-mentioned generated code 21 and above-mentioned expected value code 24 are compared in advance.
Below, the digital of digital video data method of testing of having used above-mentioned test system of digital video data is described.
At first, to the flow data of exporting from flow data generating means 19 as semiconductor device 4 inputs of tested object 26, handle and generation digital of digital video data 2 by Video Decoder 18.Then, above-mentioned digital of digital video data 2 is imported into yard generating unit 11, is output by above-mentioned digital of digital video data 2 well-determined generated codes 211.
In addition, the digital video clock 31 from above-mentioned Video Decoder 18 outputs is generated frequency-dividing clock 32 in clock division portion 30 by frequency division.
And, be imported into timing signal generating unit 40 from the synchronizing signal 41 of above-mentioned Video Decoder 18 outputs, the timing signal 42 that generation and output and above-mentioned frequency-dividing clock 32 are synchronous.
Then, above-mentioned generated code 211 is imported into yard maintaining part 50, by by above-mentioned clock signal 42 determined tests regularly, synchronously exports generated code 21 successively with above-mentioned frequency-dividing clock 32.
Then, be input to the above-mentioned generated code 21 of digital of digital video data testing apparatus 1, be imported into test starting point test section 100 and comparing section 13.Above-mentioned test starting point test section 100 detects according to 21 pairs of timings that will begin to test of above-mentioned generated code (image change point), generates test beginning timing signal 101, and is input to above-mentioned comparing section 13.
In addition, in above-mentioned comparing section 13, except above-mentioned generated code 21, also input is stored in the expected value code 24 in the desired value storage part 12, begin from receiving the moment that above-mentioned test begins timing signal 101, more above-mentioned successively generated code 21 and above-mentioned expected value code 24 carry out the distinguishing of qualified product, defective item of above-mentioned semiconductor device 4, export its comparative result 3.
In digital of digital video data testing apparatus 1, the frequency-dividing clock 32 that is transfused to is used as the signal that is equivalent to the clock signal (digital video clock) of digital of digital video data 2, and timing signal 42 conducts that are transfused to are equivalent to the vertical synchronizing signal of digital of digital video data 2 and the signal of horizontal-drive signal is used.
In addition, for example be that (CyclicRedundancy Check: cyclic redundancy check (CRC)) sign indicating number etc. may not generate identical sign indicating number by identical data, when data do not generate diverse sign indicating number simultaneously to CRC by the generated code 211 that sign indicating number generating unit 11 generated.
As mentioned above, according to the test system of digital video data of present embodiment, all low speed transmit from semiconductor device 4 to the signal of digital of digital video data testing apparatus 1 input, frequency-dividing clock 32, with synchronous timing signal 42 of above-mentioned frequency-dividing clock 32 and the generated code 21 synchronous with above-mentioned frequency-dividing clock 32.
＜the second embodiment 〉
Fig. 2 is the integrally-built block diagram of the test system of digital video data of the second embodiment of the present invention.
Be with the difference of the test system of digital video data of above-mentioned first embodiment, when the test fixed time interval is not the integral multiple of frequency-dividing clock, need be to the phase place initialization of frequency-dividing clock, but, appended phase place initialization section 33 for fear of the pulse below the half period length that before and after initialization, produces frequency-dividing clock because of signal level is different.Other structures are identical with first embodiment, but identical part is added identical symbol, only difference described.
In semiconductor device 4, clock division portion 30 has been imported timing signal 42, in above-mentioned clock division portion 30, have by each test that is included in above-mentioned timing signal 42 and regularly the phase place of clock is carried out initialized phase place initialization section 33.
Below, to the method for testing of the digital of digital video data that used above-mentioned test system of digital video data, the difference of explanation and above-mentioned first embodiment only.
Fig. 3 A, Fig. 3 B are the schematic diagrames of clock phase waveform of semiconductor device of the test system of digital video data of the second embodiment of the present invention.
120, the 121st, phase waveform before the initialization, the 130, the 131st, phase waveform after the initialization, the 140, the 141st, simple phase place switching waveform, the 150, the 151st, the frequency-dividing clock waveform that level is consistent before and after the initialization after handling.Phase place initialization section 33 is as one man carried out initialization to the phase place of frequency-dividing clock 32 with specific timing 160,161.At this, above-mentioned specific timing the 160, the 161st is contained in timing signal 42 and acceptance test timing regularly.
In Fig. 3 A, phase waveform 130 produces skew after phase waveform 120 and the initialization before initialization, when the signal level after the firm initialization is taken as " L ", only merely phase place is carried out initialization, produce the long pulse 170 of half period that is shorter than frequency-dividing clock 32.So,, keep the preceding signal level " H " of phase place initialization between the minimum half period is long-term as frequency-dividing clock waveform 150.At this moment, keeping the length of the signal level " H " before the phase place initialization, so long as the half period longly get final product during above, can certainly be the integral multiple of half period length.
In addition, in Fig. 3 B, before initialization, after phase waveform 121 and the initialization under the situation of the phase relation of phase waveform 131, not have to produce the long pulse of half period that is shorter than frequency-dividing clock 32 at simple phase place switching waveform 141, so still can use frequency-dividing clock waveform 151 yet.The time that the signal level before the phase place initialization " L " can certainly be kept at this moment, the integral multiple of above time of half period length, half period length.
As mentioned above, show the example when being " L " with the signal level after the phase place initialization, even but the signal level after the phase place initialization when being " H " also is that " H " and " L " is opposite, and identical with above-mentioned order.
As mentioned above, test system of digital video data according to present embodiment, test starting point test section 100 is a prerequisite to generate identical generated code by identical field, therefore can always make the phase place of frequency-dividing clock 32 constant to each synchronizing signal 41, and can avoid in the waveform of its frequency-dividing clock 32, producing the pulse that is shorter than half period length.
＜the three embodiment 〉
Fig. 4 is the integrally-built block diagram of the test system of digital video data of the third embodiment of the present invention.
Be with the difference of the test system of digital video data of above-mentioned first embodiment, appended with timing signal 42 and synchronously utilized the initial value that has reflected the digital of digital video data 2 in the initialization cycle, sign indicating number generating unit 11 has been carried out initialized sign indicating number generating unit initialization section 46.Other structures are identical with first embodiment, but identical part is added identical symbol, only difference described.
In semiconductor device 4, imported timing signal 42 to sign indicating number generating unit 11, in above-mentioned sign indicating number generating unit 11, have each be included in the above-mentioned timing signal 42 test regularly, utilize the initial value that has reflected the digital of digital video data 2 in the initialization cycle that above-mentioned sign indicating number generating unit 11 is carried out initialized sign indicating number generating unit initialization section 46.
Below, to the method for testing of the digital of digital video data that used above-mentioned test system of digital video data, the difference of explanation and above-mentioned first embodiment only.
Sign indicating number generating unit 11 is carried out initialization by being included in after test in the timing signal 42 regularly copies to yard maintaining part 50 with generated code 211, but this moment, replacement is as the predetermined interim initial value of fixed value, to be set at formal initial value by the generated code 211 that the digital of digital video data in the initialization cycle 2 calculates, sign indicating number generating unit 11 will be carried out initialization.
As mentioned above, according to the test system of digital video data of present embodiment, in the initialization cycle of sign indicating number generating unit 11,, also can detect the mistake of digital of digital video data 2 reliably even when in digital of digital video data 2, having comprised rub-out signal.
＜the four embodiment 〉
Fig. 5 is the integrally-built block diagram of the test system of digital video data of the fourth embodiment of the present invention.
Be with the difference of the test system of digital video data of above-mentioned first embodiment, have under the situation of code generator corresponding to the every of digital of digital video data bus, sign indicating number maintaining part 50 inside have produced test beginning timing signal 101 after, with frequency-dividing clock synchronously, successively generated code 211 is copied to the sign indicating number selector (generated code maintaining part) 51 of comparing section 13.Other structures are identical with first embodiment, but identical part is added identical symbol, only difference described.
In semiconductor device 4, has yard selector 51 in the inside of sign indicating number maintaining part 50, have under the situation of code generator corresponding to everybody of digital of digital video data bus, after having produced test beginning timing signal 101, synchronously duplicating generated code 211 successively with frequency-dividing clock 32.
Below, use Fig. 6, the method for testing of the digital of digital video data that adopted above-mentioned test system of digital video data is described.Below, the difference with above-mentioned first embodiment only is described.
Fig. 6 be the expression fourth embodiment of the present invention test system of digital video data generated code duplicate regularly schematic diagram.
After having produced test beginning timing signal 101, sign indicating number selector 51 and frequency-dividing clock 32 synchronously, will from code generator A, B in the sign indicating number generating unit 11, C corresponding to digital of digital video data everybody and the generated code of output copies to comparator 13 successively.
As mentioned above, test system of digital video data according to present embodiment, the bus that the existing sign indicating number maintaining part 50 that need prepare corresponding to the highway width of digital of digital video data is also used as a plurality of digital of digital video data can be used, therefore can reduce circuit area significantly.
＜the five embodiment 〉
Fig. 7 is the integrally-built block diagram of the test system of digital video data of the fifth embodiment of the present invention.
Be with the difference of the test system of digital video data of above-mentioned first embodiment, has regularly initialization section 47 of test in the inside of semiconductor device 4, above-mentioned test regularly initialization section 47 in above-mentioned timing signal 42, each indication with the field be unit timing the field regularly, initialization is regularly carried out in the test generation regularly that is included in the timing signal 42.Other structures are identical with first embodiment, therefore identical part added identical symbol, only difference described.
Has regularly initialization section 47 of test in the inside of the timing signal generating unit 40 of semiconductor device 4, above-mentioned test regularly initialization section 47 in above-mentioned timing signal 42, each indication with the field be unit timing the field regularly, initialization is regularly carried out in the test generation regularly that is included in the timing signal 42.
Below, use Fig. 8, the method for testing of the digital of digital video data that adopted above-mentioned test system of digital video data is described.Below, the difference with above-mentioned first embodiment only is described.
Fig. 8 is the field timing and the schematic diagram of testing position relation regularly of the test system of digital video data of expression present embodiment.
Timing signal generating unit 40, generate on each border with the synchronous field of frequency-dividing clock 32 regularly and the constant test timing of fixed time interval.At this moment, as one man be initialized as steady state value by testing regularly the counting of initialization section 47 with a timing with above-mentioned test interval regularly.
As mentioned above, according to the test system of digital video data of present embodiment, from the test timing position of each timing be not limited to this and constant, therefore can guarantee the reproducibility of generated code.
＜the six embodiment 〉
Fig. 9 is the integrally-built block diagram of the test system of digital video data of the expression sixth embodiment of the present invention.
Be with the difference of the test system of digital video data of above-mentioned first embodiment, replace test starting point test section 100 and have image measurement point test section (field special code comparing section) 14, and have a special code generating unit 60.Other structures are identical with first embodiment, but identical part is added identical symbol, only difference described.
The inside of digital of digital video data testing apparatus 1 have utilization with the field be the generated code 21 of unit generate the field special code generating unit 60 of a special code 61 and by handling above-mentioned special code 61 the image measurement point test section 14 of detected image starting point and output image starting point detection signal 22, above-mentioned image starting point detection signal 22 is imported into comparing section 13 as testing the starting point timing signal.
Below, the method for testing of the digital of digital video data that adopted above-mentioned test system of digital video data is described.Below, the difference with above-mentioned first embodiment only is described.
It is generated code 21 a generation special code 61 of unit that field special code generating unit 60 is utilized with the field.Image measurement point test section 14 is the detected image starting point by field of handling above-mentioned special code 61, and output image starting point detection signal 22, is input to comparing section 13.
As mentioned above, test system of digital video data according to present embodiment, can be the generated code 21 of unit regularly by between a continuous special code 61, comparing, distinguish that identical field begins in continuous or different fields, can have the test of reproducibility with test.
At this, when the test of the digital of digital video data of interlacing (interlaced) mode, even rest image, at front court and back court, field data is also different, so distinguishes when different fields has begun, and a field special code and the special code when back several second field, front court when the front court are compared, the detected image starting point, output image starting point detection signal 22.
＜the seven embodiment 〉
Figure 10 is the integrally-built block diagram of the test system of digital video data of the expression seventh embodiment of the present invention.
Be with the difference of the test system of digital video data of above-mentioned first embodiment, replace test starting point test section 100 and have designated code test section 16, and have a special code generating unit 60 and designated code storage part (specifying a special code maintaining part) 15.Other structures are identical with first embodiment, but identical part is added identical symbol, only difference described.
The inside of digital of digital video data testing apparatus 1 has the field special code generating unit 60 that utilization is generated code 21 a generation special code 61 of unit with the field, the designated code storage part 15 and the designated code test section 16 of storage designated code.From a designated code 23 and a special code 61 of above-mentioned designated code storage part 15 outputs, output designated code detection signal 25 is input to comparing section 13 as test starting point timing signal to above-mentioned designated code test section 16 by relatively.
Below, the method for testing of the digital of digital video data that adopted above-mentioned test system of digital video data is described.Below, the difference with above-mentioned first embodiment only is described.
It is generated code 21 a generation special code 61 of unit that field special code generating unit 60 is utilized with the field.16 pairs of field special codes 61 of handling a field of above-mentioned special code 61 and generating of designated code test section and the designated code 23 that is stored in designated code storage part 15 compare, they are judged as when consistent and detect the image starting point, output designated code test signal 25 is input to comparing section 13.
As mentioned above, test system of digital video data according to present embodiment, can be by comparing with continuous field special code 61 and designated code 15 by the generated code 21 that with test regularly is unit, distinguish that identical field begins in continuous or different fields, can have the test of reproducibility.
At this, when the test of the digital of digital video data of interlace mode, even rest image, at front court and back court, field data is also different, so distinguishes when different fields has begun, and a field special code and the special code when back several second field, front court when the front court are compared.
＜the eight embodiment 〉
Figure 11 is the integrally-built block diagram of the semiconductor device of the expression eighth embodiment of the present invention.
In Figure 11, the 19th, the flow data generating means of output stream data 26, the 5th, semiconductor device, the 80th, desired value exterior storage portion.
Above-mentioned semiconductor device 5 comprises the Video Decoder 18 of handling flow data 26 and generating digital of digital video data 2, generation is by the sign indicating number generating unit 11 of above-mentioned digital of digital video data 2 well-determined generated codes 211, digital video clock 31 frequency divisions are generated the clock division portion 30 of frequency-dividing clock 32, utilize the synchronizing signal 41 of above-mentioned digital of digital video data 2 to generate timing signal generating unit 40 with the synchronous timing signal 42 of above-mentioned frequency-dividing clock 32, output makes the sign indicating number maintaining part 50 of the synchronous generated code 21 of above-mentioned generated code 211 and above-mentioned timing signal 42 and above-mentioned frequency-dividing clock 32, handle the test starting point test section (image change point test section) 100 of above-mentioned generated code 21 and output test beginning timing signal 101, store the desired value storage part 12 of expected value code 24 in advance, and to above-mentioned generated code 21 and above-mentioned expected value code 24 comparing section 13 relatively.
Below, the method for testing of the digital of digital video data that adopted above-mentioned semiconductor device is described.
At first, to the flow data of exporting from flow data generating means 19 as semiconductor device 5 inputs of tested object 26, handle and generation digital of digital video data 2 by Video Decoder 18.Then, above-mentioned digital of digital video data 2 is imported into yard generating unit 11, and output is by above-mentioned digital of digital video data 2 well-determined generated codes 211.
In addition, from the digital video clock 31 of above-mentioned Video Decoder 18 outputs after clock division portion 30 is by frequency division, output frequency division clock 32.
And, be imported into timing signal generating unit 40 from the synchronizing signal 41 of above-mentioned Video Decoder 18 outputs, the timing signal 42 that generation and output and above-mentioned frequency-dividing clock 32 are synchronous.
Then, above-mentioned generated code 211 is imported into yard maintaining part 50, at each by above-mentioned timing signal 42 determined tests regularly, synchronously exports generated code 21 successively with above-mentioned frequency-dividing clock 32.
Then, above-mentioned generated code 21 is imported into test starting point test section 100 and comparing section 13.Above-mentioned test starting point test section 100 detects according to 21 pairs of timings that will begin to test of above-mentioned generated code (image change point), generates test beginning timing signal 101, and is input to above-mentioned comparing section 13.
In addition, in above-mentioned comparing section 13, except above-mentioned generated code 21, also input is stored in the expected value code 24 in the desired value storage part 12, begin from receiving the moment that above-mentioned test begins timing signal 101, more above-mentioned successively generated code 21 and above-mentioned expected value code 24 carry out the distinguishing of qualified product, defective item of above-mentioned semiconductor device 5, export its comparative result 3.
The expected value code that storage is read in from the desired value storage part 80 of the outside that is configured in above-mentioned semiconductor device 5 in above-mentioned desired value storage part 12.And inside is equipped with built-in miniature computer 70 in above-mentioned semiconductor device 5, from the read in control of above-mentioned desired value exterior storage portion 80 to above-mentioned desired value storage part 12, is undertaken by above-mentioned built-in miniature computer 70.
As mentioned above,, can contain the inscape of the digital of digital video data testing apparatus 1 among above-mentioned first embodiment, improve the easiness of test by the inside of semiconductor device 5 according to the semiconductor device of present embodiment.
In addition, has desired value exterior storage portion 80 in the outside of above-mentioned semiconductor device 5, and to the built-in miniature computer 70 that use also is used for the control of semiconductor device 5 that reads in of this expected value code 241, therefore, the area that can suppress above-mentioned semiconductor device 5 increases.
＜the nine embodiment 〉
Figure 12 is the integrally-built block diagram of the semiconductor device of the expression ninth embodiment of the present invention.
Be with the difference of the semiconductor device of above-mentioned the 8th embodiment, replace built-in miniature computer 70 to using desired value to read in portion 81, and the relatively use built-in miniature computer 70 of generated code 21 and expected value code 24 is replaced comparing section 13 from reading in of the expected value code 241 of desired value exterior storage portion 80.Other structures are identical with the 8th embodiment, therefore identical part added identical symbol, only difference described.
Desired value is set in the semiconductor device 5 reads in portion 80 and replace built-in miniature computer 70 among the 8th embodiment, and be provided with built-in miniature computer 70 and replace comparing section 13.
In having used the digital of digital video data method of testing of above-mentioned semiconductor device 5, read in portion 81 by above-mentioned desired value and read in expected value code 241, compare by 70 pairs of generated codes 21 of above-mentioned built-in miniature computer and expected value code 24 from above-mentioned desired value exterior storage portion 80.
As mentioned above, according to the semiconductor device of present embodiment, can improve the easiness of test by contain the inscape of the digital of digital video data testing apparatus 1 among above-mentioned first embodiment in the inside of semiconductor device 5.In addition, have desired value exterior storage portion 80 by the outside in above-mentioned semiconductor device 5, and use built-in miniature computer 70 to replace comparing section 13, the area that can suppress above-mentioned semiconductor device 5 increases.
＜the ten embodiment 〉
Figure 13 is the integrally-built block diagram of the semiconductor device of the expression tenth embodiment of the present invention.
Be with the difference of the semiconductor device of above-mentioned the 8th embodiment, use built-in miniature computer 70 to replace comparing section 13.Other structures are identical with the 8th embodiment, therefore identical part added identical symbol, only difference described.
As mentioned above, semiconductor device according to present embodiment, can be by contain the inscape of the digital of digital video data testing apparatus 1 among above-mentioned first embodiment in the inside of semiconductor device 5, improve the easiness of test, and, by outer setting desired value exterior storage portion 80 in above-mentioned semiconductor device 5, use the built-in miniature computer 70 that is provided with to replace comparing section 13, read in expected value code 24 from desired value exterior storage portion 80, compare with generated code 21, therefore, can further suppress the area increase of above-mentioned semiconductor device 5.
＜the ten one embodiment 〉
Figure 14 is the integrally-built block diagram of the test system of digital video data of the expression 11st embodiment of the present invention.
Be with the difference of the test system of digital video data of above-mentioned first embodiment, on semiconductor device installation substrate 90, semiconductor device 4 is installed, when carrying out the test of above-mentioned semiconductor device 4, comprise the test of the integral body of above-mentioned semiconductor device installation substrate 90.Other structures are identical with first embodiment, therefore identical part added identical symbol, only difference described.
In Figure 14, the 90th, semiconductor device is installed substrate, installs on the substrate 90 at semiconductor device semiconductor device 4 is installed.
In the test of the digital of digital video data that has used above-mentioned test system of digital video data, via above-mentioned semiconductor device substrate 90 is installed, to digital of digital video data testing apparatus 1 input generated code 21.Action afterwards is identical with first embodiment, therefore omits its explanation.
As mentioned above, according to the test system of digital video data of present embodiment, when carrying out the test of semiconductor device 4, can comprise the test of the transmission path of semiconductor device installation substrate 90, therefore, also can carry out the test of the product substrate of for example digital AV equipment simultaneously.
＜the ten two embodiment 〉
Figure 15 is the integrally-built block diagram of the test system of digital video data of the 12nd embodiment of the present invention.
Be to have expected value code input part 82 with the difference of the test system of digital video data of above-mentioned the 11 embodiment, and have expected value code dispensing device 300 and test control part 310 in the outside of digital of digital video data testing apparatus 1.Other structures are identical with the 11 embodiment, therefore identical part added identical symbol, only difference described.
In Figure 15, the 310th, begin to test, control the test control part of test, the 300th, can send the expected value code dispensing device of random desired value sign indicating number, the 82nd, receive the expected value code input part of the expected value code that is sent from above-mentioned expected value code dispensing device 300.
In the test of the digital of digital video data that has used above-mentioned test system of digital video data, send the expected value code that is stored in desired value storage part 12 from above-mentioned expected value code dispensing device 300, receive this expected value code and be stored in above-mentioned desired value storage part 12 by above-mentioned expected value code input part 82.The beginning that test control part 310 is tested according to the situation of system.Other actions are identical with the 11 embodiment, therefore omit its explanation.
As mentioned above, test system of digital video data according to present embodiment, for example set in the family digital AV equipment is provided with expected value code input part 82, in above-mentioned expected value code input part 82, reception is by data broadcasting, expected value code that data communication sent, this expected value code that receives is stored in the desired value storage part 12, even in product post sales, also can carry out regular autodiagnosis etc.
Claims (22)
1. a test system of digital video data is characterized in that, comprises semiconductor device and digital of digital video data testing apparatus,
Above-mentioned semiconductor device comprises
Generation is by the sign indicating number generating unit of the well-determined generated code of digital of digital video data that is transfused to;
The clock division portion of the frequency-dividing clock behind the frequency division is carried out in generation to clock;
Use the synchronizing signal of above-mentioned digital of digital video data to generate timing signal generating unit with the synchronous timing signal of above-mentioned frequency-dividing clock; And
Synchronously export the sign indicating number maintaining part of above-mentioned generated code with above-mentioned timing signal and above-mentioned frequency-dividing clock,
Above-mentioned semiconductor device is exported above-mentioned timing signal, above-mentioned generated code and above-mentioned frequency-dividing clock to the outside,
Above-mentioned digital of digital video data testing apparatus receives timing signal, generated code and the frequency-dividing clock from above-mentioned semiconductor device, comprises
Image change point test section is analyzed the image change point that is detected the represented image time of origin variation of above-mentioned digital of digital video data by the above-mentioned sign indicating number generated code that generating unit generated;
The desired value storage part, the storage expected value code; And
Comparing section from testing the moment of above-mentioned image change point, begins above-mentioned generated code and above-mentioned expected value code are compared,
Above-mentioned digital of digital video data testing apparatus is handled above-mentioned generated code and is tested above-mentioned semiconductor device.
2. test system of digital video data according to claim 1 is characterized in that:
Above-mentioned semiconductor device also has at each carries out initialized phase place initialization section by the determined specific timing of above-mentioned timing signal to the phase place of above-mentioned frequency-dividing clock,
Signal level during at least half clock cycle of above-mentioned phase place initialization section after with the firm initialization of above-mentioned frequency-dividing clock be set at be about to initialization before the identical level of signal level.
3. test system of digital video data according to claim 1 is characterized in that:
Above-mentioned semiconductor device also has with above-mentioned timing signal synchronously carries out initialized sign indicating number generating unit initialization section to above-mentioned sign indicating number generating unit,
Above-mentioned sign indicating number generating unit initialization section is carried out initialization with the initial value that has reflected the digital of digital video data in the initialization cycle to above-mentioned sign indicating number generating unit.
4. test system of digital video data according to claim 1 is characterized in that:
Above-mentioned semiconductor device also has the generated code maintaining part that keeps above-mentioned generated code during till export above-mentioned generated code,
Above-mentioned generated code maintaining part, when having a plurality of above-mentioned sign indicating number generating unit, the generated code that synchronously keeps each yard generating unit to generate successively with above-mentioned timing signal and above-mentioned sub-frequency clock signal.
5. test system of digital video data according to claim 1 is characterized in that:
Above-mentioned semiconductor device also has regularly initialization section of test, each indication in above-mentioned timing signal with the field be unit timing the field regularly, initialization is regularly carried out in the test generation regularly of the timing of more above-mentioned generated code of the indication in the above-mentioned timing signal and above-mentioned expected value code.
6. test system of digital video data according to claim 1 is characterized in that:
Above-mentioned digital of digital video data testing apparatus also comprises
Field special code generating unit, each the test timing at above-mentioned timing signal generates a special code from the above-mentioned generated code that is transfused to; And
Field special code comparing section compares to field special code in the field special code that is generated by above-mentioned field special code generating unit, that generate in current place with at a field special code of working as front court back several second place generation,
Above-mentioned comparing section begins to carry out the comparison of above-mentioned generated code and above-mentioned expected value code from testing out above-mentioned two inconsistent moment of field special code.
7. test system of digital video data according to claim 1 is characterized in that:
Above-mentioned semiconductor device is installed on the substrate, transmits above-mentioned generated code from above-mentioned semiconductor device to above-mentioned digital of digital video data testing apparatus via above-mentioned substrate.
8. test system of digital video data according to claim 7 is characterized in that:
Also comprise the transmission expected value code dispensing device of above-mentioned expected value code arbitrarily; Import the expected value code input part of above-mentioned expected value code from the outside; And the test control part of carrying out test in the timing of appointment.
9. a test system of digital video data is characterized in that, comprises semiconductor device and digital of digital video data testing apparatus,
Above-mentioned semiconductor device comprises
Generation is by the sign indicating number generating unit of the well-determined generated code of digital of digital video data that is transfused to;
The clock division portion of the frequency-dividing clock behind the frequency division is carried out in generation to clock;
Use the synchronizing signal of above-mentioned digital of digital video data to generate timing signal generating unit with the synchronous timing signal of above-mentioned frequency-dividing clock; And
Synchronously export the sign indicating number maintaining part of above-mentioned generated code with above-mentioned timing signal and above-mentioned frequency-dividing clock,
Above-mentioned semiconductor device is exported above-mentioned timing signal, above-mentioned generated code and above-mentioned frequency-dividing clock to the outside,
Above-mentioned digital of digital video data testing apparatus receives timing signal, generated code and the frequency-dividing clock from above-mentioned semiconductor device, comprises
The designated code storage part, the storage designated code;
Whether the designated code test section detects by the above-mentioned sign indicating number generated code that generating unit generated consistent with above-mentioned designated code;
The desired value storage part, the storage expected value code; And
Comparing section from testing out the above-mentioned generated code moment consistent with above-mentioned designated code, begins above-mentioned generated code and above-mentioned expected value code are compared,
Above-mentioned digital of digital video data testing apparatus is handled above-mentioned generated code and is tested above-mentioned semiconductor device.
10. test system of digital video data according to claim 9 is characterized in that:
Above-mentioned semiconductor device also is included in by determined each the specific timing of above-mentioned timing signal carries out initialized phase place initialization section to the phase place of above-mentioned frequency-dividing clock,
Signal level during at least half clock cycle of above-mentioned phase place initialization section after with the firm initialization of above-mentioned frequency-dividing clock be set at be about to initialization before the identical level of signal level.
11. test system of digital video data according to claim 9 is characterized in that:
Above-mentioned semiconductor device also comprises with above-mentioned timing signal synchronously carries out initialized sign indicating number generating unit initialization section to above-mentioned sign indicating number generating unit,
Above-mentioned sign indicating number generating unit initialization section is carried out initialization with the initial value that has reflected the digital of digital video data in the initialization cycle to above-mentioned sign indicating number generating unit.
12. test system of digital video data according to claim 9 is characterized in that:
Above-mentioned semiconductor device also be included in to output till the above-mentioned generated code during keep the generated code maintaining part of above-mentioned generated code,
Above-mentioned generated code maintaining part, when having a plurality of above-mentioned sign indicating number generating unit, the generated code that synchronously keeps each yard generating unit to be generated successively with above-mentioned timing signal and above-mentioned sub-frequency clock signal.
13. test system of digital video data according to claim 9 is characterized in that:
Above-mentioned semiconductor device also comprises regularly initialization section of test, each indication in above-mentioned timing signal with the field be unit timing the field regularly, initialization is regularly carried out in the test generation regularly of the timing of more above-mentioned generated code of the indication in the above-mentioned timing signal and above-mentioned expected value code.
14. test system of digital video data according to claim 9 is characterized in that:
Above-mentioned digital of digital video data testing apparatus also comprises
Field special code generating unit, each the test timing at above-mentioned timing signal generates a special code from the above-mentioned generated code that is transfused to; And
Specify a special code maintaining part, keep specifying a special code,
Above-mentioned comparing section begins to carry out the comparison of above-mentioned generated code and above-mentioned expected value code from detecting above-mentioned special code with the above-mentioned appointment field consistent moment of special code.
15. test system of digital video data according to claim 9 is characterized in that:
Above-mentioned semiconductor device is installed on the substrate, transmits above-mentioned generated code from above-mentioned semiconductor device to above-mentioned digital of digital video data testing apparatus via above-mentioned substrate.
16. test system of digital video data according to claim 15 is characterized in that:
Also comprise the transmission expected value code dispensing device of above-mentioned expected value code arbitrarily; Import the expected value code input part of above-mentioned expected value code from the outside; And the test control part of carrying out test in the timing of appointment.
17. a semiconductor device is characterized in that, comprises
The sign indicating number generating unit generates by the well-determined generated code of the digital of digital video data that is transfused to;
Clock division portion generates clock is carried out frequency-dividing clock behind the frequency division;
The timing signal generating unit uses the synchronizing signal of above-mentioned digital of digital video data to generate and the synchronous timing signal of above-mentioned frequency-dividing clock;
The sign indicating number maintaining part is synchronously exported above-mentioned generated code with above-mentioned timing signal and above-mentioned frequency-dividing clock,
Image change point test section is analyzed by the above-mentioned sign indicating number generated code that generating unit generated, and tests the image change point of the represented image time of origin variation of above-mentioned digital of digital video data;
The desired value storage part, the storage expected value code;
The built-in miniature computer reads in above-mentioned expected value code to above-mentioned desired value storage part; And
Comparing section from detecting the moment of above-mentioned image change point, begins above-mentioned generated code and above-mentioned expected value code are compared.
18. semiconductor device according to claim 17 is characterized in that:
Above-mentioned comparing section is above-mentioned built-in miniature computer.
19. semiconductor device according to claim 17 is characterized in that:
Above-mentioned comparing section is above-mentioned built-in miniature computer,
Above-mentioned built-in miniature computer carries out reading in of above-mentioned generated code and above-mentioned expected value code, and to the comparison of above-mentioned generated code and above-mentioned expected value code.
20. a semiconductor device is characterized in that, comprises
The sign indicating number generating unit generates by the well-determined generated code of the digital of digital video data that is transfused to;
Clock division portion generates the frequency-dividing clock behind the clock division;
The timing signal generating unit uses the synchronizing signal of above-mentioned digital of digital video data to generate and the synchronous timing signal of above-mentioned frequency-dividing clock;
The sign indicating number maintaining part is synchronously exported above-mentioned generated code with above-mentioned timing signal and above-mentioned frequency-dividing clock,
The designated code storage part, the storage designated code;
Whether the designated code test section detects by the above-mentioned sign indicating number generated code that generating unit generated consistent with above-mentioned designated code;
The desired value storage part, the storage expected value code;
The built-in miniature computer reads in above-mentioned expected value code to above-mentioned desired value storage part; And
Comparing section from detecting the above-mentioned generated code moment consistent with above-mentioned designated code, begins above-mentioned generated code and above-mentioned expected value code are compared.
21. semiconductor device according to claim 20 is characterized in that:
Above-mentioned comparing section is above-mentioned built-in miniature computer.
22. semiconductor device according to claim 20 is characterized in that:
Above-mentioned comparing section is above-mentioned built-in miniature computer,
Above-mentioned built-in miniature computer carries out reading in of above-mentioned generated code and above-mentioned expected value code and to the comparison of above-mentioned generated code and above-mentioned expected value code.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP298061/2006 | 2006-11-01 | ||
| JP2006298061A JP2008118297A (en) | 2006-11-01 | 2006-11-01 | Digital video data test system and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101175225A true CN101175225A (en) | 2008-05-07 |
Family
ID=39330104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101666452A Pending CN101175225A (en) | 2006-11-01 | 2007-11-01 | Test system of digital video data and semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20080101468A1 (en) |
| JP (1) | JP2008118297A (en) |
| CN (1) | CN101175225A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105763872A (en) * | 2015-01-07 | 2016-07-13 | 瑞萨电子株式会社 | Video Encoding/decoding System And Diagnosis Method Thereof |
| CN110545411A (en) * | 2018-05-29 | 2019-12-06 | 中强光电股份有限公司 | Projector, projection system and detection method of transmission delay thereof |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102231845A (en) * | 2011-06-14 | 2011-11-02 | 深圳市同洲电子股份有限公司 | Method and device for testing front end of digital television |
| US9697013B2 (en) * | 2015-06-10 | 2017-07-04 | Dell Products, L.P. | Systems and methods for providing technical support and exporting diagnostic data |
| KR20170007927A (en) * | 2015-07-13 | 2017-01-23 | 에스케이하이닉스 주식회사 | Semiconductor device and semiconductor system |
| US11011096B2 (en) * | 2016-08-25 | 2021-05-18 | Sharp Nec Display Solutions, Ltd. | Self-diagnostic imaging method, self-diagnostic imaging program, display device, and self-diagnostic imaging system |
| KR20180038339A (en) * | 2016-10-06 | 2018-04-16 | 에스케이하이닉스 주식회사 | Semiconductor device for executing a test method checking a cell allay failure |
| JP2019145571A (en) | 2018-02-16 | 2019-08-29 | 株式会社東芝 | Semiconductor device |
| US11438573B2 (en) * | 2019-09-25 | 2022-09-06 | Semiconductor Components Industries, Llc | Verification circuitry for row driver fault detection |
| CN112702239A (en) * | 2020-12-29 | 2021-04-23 | 中国航空工业集团公司西安飞机设计研究所 | Automatic test method of distributed test system |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3976864A (en) * | 1974-09-03 | 1976-08-24 | Hewlett-Packard Company | Apparatus and method for testing digital circuits |
| US4192451A (en) * | 1978-05-30 | 1980-03-11 | Tektronix, Inc. | Digital diagnostic system employing signature analysis |
| US4569049A (en) * | 1983-05-09 | 1986-02-04 | Digital Equipment Corp. | Diagnostic system for a digital computer |
| US4601033A (en) * | 1984-01-16 | 1986-07-15 | Siemens Corporate Research & Suppport, Inc. | Circuit testing apparatus employing signature analysis |
| US4814872A (en) * | 1987-06-04 | 1989-03-21 | Tektronix, Inc. | Digital video probe system |
| US5253070A (en) * | 1990-12-31 | 1993-10-12 | Goldstar Co., Ltd. | System and method for automatically detecting a variation of video information |
| DE69634219D1 (en) * | 1995-03-21 | 2005-03-03 | Sun Microsystems Inc | Video frame identifier detection |
| JPH10142298A (en) * | 1996-11-15 | 1998-05-29 | Advantest Corp | Testing device for ic device |
| US6370675B1 (en) * | 1998-08-18 | 2002-04-09 | Advantest Corp. | Semiconductor integrated circuit design and evaluation system using cycle base timing |
| US7647538B2 (en) * | 2007-03-21 | 2010-01-12 | Advantest Corporation | Test apparatus and electronic device for generating test signal by using repeated interval in a test instruction stream |
-
2006
- 2006-11-01 JP JP2006298061A patent/JP2008118297A/en active Pending
-
2007
- 2007-08-07 US US11/890,478 patent/US20080101468A1/en not_active Abandoned
- 2007-11-01 CN CNA2007101666452A patent/CN101175225A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105763872A (en) * | 2015-01-07 | 2016-07-13 | 瑞萨电子株式会社 | Video Encoding/decoding System And Diagnosis Method Thereof |
| CN105763872B (en) * | 2015-01-07 | 2019-06-14 | 瑞萨电子株式会社 | Encoding and decoding of video system and its diagnostic method |
| US10638148B2 (en) | 2015-01-07 | 2020-04-28 | Renesas Electronics Corporation | Video encoding/decoding system and diagnosis method thereof |
| CN110545411A (en) * | 2018-05-29 | 2019-12-06 | 中强光电股份有限公司 | Projector, projection system and detection method of transmission delay thereof |
| CN110545411B (en) * | 2018-05-29 | 2021-06-15 | 中强光电股份有限公司 | Projector, projection system and detection method of transmission delay thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| US20080101468A1 (en) | 2008-05-01 |
| JP2008118297A (en) | 2008-05-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101175225A (en) | Test system of digital video data and semiconductor device | |
| EP2147361B1 (en) | Usb based synchronization and timing system | |
| CN103777072B (en) | The method being monitored to the clock frequency of multiple clock sources | |
| CN102183695A (en) | Methods and receiver for measuring data pulses | |
| CN103618588B (en) | A kind of auto-baud-detect method and detection module | |
| CN105549379A (en) | Synchronous measurement apparatus based on high precision time reference triggering and method thereof | |
| CN101576610B (en) | Device and method for improving data sampling precision in oscillograph | |
| CN106385256A (en) | Multi-channel parallel acquisition system with storage function and synchronous recognition function | |
| CN102495912A (en) | Multi-channel high-speed data acquisition system with synchronous correction function | |
| CN100422756C (en) | Semiconductor test device | |
| CN105245203B (en) | High-precision low-speed clock duty ratio detecting system and method | |
| CN102928677A (en) | Nano pulse signal acquiring method | |
| CN101995500A (en) | Test and measurement instrument with bit-error detection | |
| CN102879641A (en) | Frequency measurement method and system | |
| CN105717851A (en) | Real Time Trigger Using A Finite State Machine Having A Counting State | |
| CN103901243B (en) | A kind of oscillograph with high triggering precision | |
| CN100366006C (en) | Method and device of embedding type self-testing for universal serial bus physical layer receiving/sending apparatus | |
| CN101268376B (en) | An apparatus and method for multi-phase digital sampling | |
| CN101534154A (en) | Error code test method of burst optical signal receiving module | |
| CN103675381A (en) | Parallel sampling oscilloscope with cycle triggering function | |
| JP2000221248A (en) | Semiconductor testing device | |
| CN115638952A (en) | Multipoint pressure data synchronous parallel acquisition system and application method | |
| CN103513103A (en) | Physical quantity measuring apparatus and physical quantity measuring method | |
| JP2011146792A (en) | Error rate measuring apparatus and method | |
| CN108737038A (en) | Communicate error code device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20080507 |