CN109444886B - Parallel computing processing method, system and medium for bistatic SAR real-time imaging - Google Patents
Parallel computing processing method, system and medium for bistatic SAR real-time imaging Download PDFInfo
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Abstract
The invention provides a parallel computing processing method, a system and a medium for high-reliability bistatic SAR real-time imaging, wherein the method comprises the steps of receiving a plurality of paths of parallel digital signals from a phase control antenna; preprocessing the parallel digital signals; dividing the preprocessed data into N paths of same preprocessed data and distributing the preprocessed data to N paths of DSP computing groups, wherein the N paths of DSP computing groups respectively and independently output a pair of images; and the terminal receives all the output real-time images, performs image matching identification processing, and sends out corresponding control instructions according to identification results. By adopting the scheme of the invention, the defects in the aspects of reliability, communication efficiency, signal processing capacity and the like are overcome on the premise of equal real-time calculability.
Description
Technical Field
The invention relates to the technical field of data processing, in particular to a parallel computing processing method, a system and a medium for high-reliability bistatic SAR real-time imaging.
Background
The working principle of the SAR (synthetic aperture radar) is that the relative motion of the radar and a target is utilized to synthesize a large radar with equivalent antenna aperture by a data processing method for a real antenna aperture with small size. The synthetic aperture radar has the characteristics of high resolution, all-weather operation and effective identification of camouflage and penetration masks. The bistatic synthetic aperture radar adopts a separation transmitter and a receiver, realizes radar imaging when flying on different platforms, and obtains a forward-looking SAR image by using a special flight track of the flying platform.
Although, the research of double-base forward-looking SAR imaging algorithm is also carried out in the scientific research institutions such as domestic electronic technology university, national defense technology university, Beijing university of science and technology, and China academy of science electronics. Through more than ten years of technical attack and customs of the electronic science and technology university, the problems of the double-base forward-looking SAR such as the system, the theoretical method, the key technology and the like are systematically solved, the double-base forward-looking SAR imaging theory and the existing problems are firstly and systematically discussed in 2009, and the double-base forward-looking SAR resolution theory and the optimal working mode are researched; aiming at the imaging modes of shift/shift invariance and the like, series of frequency domain imaging algorithms of a fourth-order RNLCS, Keystone-NLCS, 2D-omega k and the like are provided, and the problems of large migration, strong coupling, two-dimensional space variation and the like of the bistatic forward-looking SAR are effectively solved. However, the engineering research on the aspect of airborne and missile-borne double-base SAR imaging in China is less, most of the engineering research is still in the theoretical research of algorithm simulation, and a better engineering system scheme does not exist for the real-time imaging technology of the airborne double-base SAR in a high-speed and ultra-high-speed environment.
The bistatic SAR digital signal processor consists of an FPGA + DSP framework. Algorithm modules are generally deployed by adopting a 'pipeline' principle, but if a sharply increased computational task exists, the system performance is seriously reduced. In addition, strong data dependence exists among the modules, and the whole system cannot work as long as one computing module is damaged. For airborne and missile-borne double-base SAR, various technical requirements such as reliability, instantaneity and the like are further improved.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a highly reliable parallel computing method, system and medium for bistatic SAR real-time imaging. On the premise of equal real-time calculability, the defects in the aspects of reliability, communication efficiency, signal processing capacity and the like are overcome.
According to an embodiment of the present invention, the present invention provides a parallel computing processing method for high-reliability bistatic SAR real-time imaging, the method includes the following steps:
receiving a plurality of paths of parallel digital signals from a phase-controlled antenna;
preprocessing the parallel digital signals;
dividing the preprocessed data into N paths of same data to be sent, sending the data to corresponding DSP computing groups, and independently outputting a sub-image by the N paths of DSP computing groups receiving complete data respectively;
and the terminal receives all the output real-time images, performs image matching identification processing, and sends out corresponding control instructions according to identification results.
According to the method of the invention, preferably, the preprocessed data is divided into N paths of same data to be sent, each path of data to be sent is provided with a corresponding identifier, and when the data to be sent with the corresponding identifier is distributed to N paths of DSP calculation groups, the corresponding relation between the identifier and the DSP calculation group corresponding to the data to be sent is recorded;
after the N paths of DSP calculation groups respectively receive the preprocessed data with the identifier information, whether the data is complete or not is detected, if the data is incomplete, the identifier information is returned to request data retransmission, after the identifier information is received, the data corresponding to the identifier is selected, and the N paths of DSP calculation groups respectively and independently output one image after the complete data is received;
according to the method of the present invention, preferably, after dividing the preprocessed data into N paths of same preprocessed data and distributing the preprocessed data to N paths of DSP calculation groups, the method further includes automatically detecting whether the data is successfully sent to the N paths of DSP calculation groups, if there is N-2 paths of data that are not successfully sent to the DSP calculation groups, sending a second-level warning message to prompt that the current data sending channel has a medium level of risk of breaking, which needs to be noticed, and if there is N-1 paths of data that are not successfully sent to the DSP calculation groups, sending a first-level warning message to prompt that the current data sending channel has a high level of risk of breaking, which needs to be processed in time.
According to the method of the invention, preferably, no data communication and control exists between the N paths of DSP calculation groups, the N paths of DSP calculation groups run completely and independently, each path of DSP calculation group starts a calculation program respectively, and N complete data processing processes are started in total;
parallel computing is carried out among all DSP computing units in each DSP computing group, and the parallel computing of all DSP computing units in each DSP computing group comprises the following steps: coarse-grained parallel computation, medium-grained parallel computation and fine-grained parallel computation;
the coarse-grained parallel computation adopts a pipeline parallel computation technology, and a plurality of algorithm tasks are distributed to each DSP computing unit according to a pipeline;
the medium-granularity parallel computing adopts a parallel distributed computing technology, and shares computing tasks with huge computing quantities to a plurality of DSP computing units in a DSP computing group for parallel computing;
and fine-grained parallel computing adopts an instruction set parallel computing technology, and after a computing task is divided into instruction sets, the instruction sets are distributed to different DSP computing units in parallel.
According to the method of the present invention, it is preferable to adopt coarse-grained parallel deployment for the following computation tasks: fixed point to floating point conversion, Doppler center estimation, linear distance walking correction and matrix transposition;
adopting medium-granularity parallel deployment for the following computing tasks: doppler frequency modulation rate estimation, phase gradient self-focusing and geometric correction.
TMS320C6678 is selected for fine-grained parallel deployment, a Very Long Instruction Word (VLIW) architecture and rich SIMD assembly instructions are adopted.
According to another embodiment of the invention, a parallel computing processing system for high-reliability bistatic SAR real-time imaging comprises an FPGA, an N-way DSP computing group and a terminal, wherein the FPGA comprises an FPGA receiving unit, a preprocessing module and N SIRO modules, the terminal comprises a terminal control module, wherein,
the FPGA receiving unit is used for receiving the multipath parallel digital signals from the phase control antenna;
the preprocessing module is used for preprocessing the parallel digital signals, selecting data corresponding to the identifier when a data retransmission request is received, and sending the data to the DSP computing group corresponding to the identifier;
the preprocessing module is also used for automatically detecting whether the data are successfully sent to the N paths of DSP computing groups;
the SIRO module is used for dividing the preprocessed data into N paths of same data to be sent and distributing the data to N paths of DSP calculation groups;
the N paths of DSP calculation groups are used for respectively and independently calculating and outputting an image after respectively receiving the preprocessed data;
and the terminal control module is used for receiving all output real-time images, performing image matching identification processing and sending out corresponding control instructions according to identification results.
According to the system of the present invention, preferably, the preprocessing module is further configured to automatically detect whether data is successfully transmitted to the N-channel DSP computing group, and if N-2 channels of data are not successfully transmitted to the DSP computing group, send a second-level warning message to prompt that the current data transmission channel has a medium-level risk level of disconnection, which needs to be noticed, and if N-1 channels of data are not successfully transmitted to the DSP computing group, send a first-level warning message to prompt that the current data transmission channel has a high-level risk level of disconnection, which needs to be processed in time;
the SIRO module is used for dividing the preprocessed data into N paths of same data to be sent, setting a corresponding identifier for each path of data to be sent, and recording the corresponding relation between the identifier and the current DSP calculation group of the data to be sent when the data to be sent with the corresponding identifier is distributed to the N paths of DSP calculation groups;
and the N paths of DSP calculation groups are used for detecting whether the data are complete or not after respectively receiving the preprocessed data with the identifier information, returning the identifier information if the data are incomplete, requesting data retransmission, and respectively and independently outputting one image by the N paths of DSP calculation groups receiving the complete data.
According to the system of the present invention, preferably, the FPGA further includes a data unit, configured to assemble the plurality of preprocessed data frames into a data packet according to a predetermined sequence.
According to the system of the invention, preferably, no data communication and control exists between the N paths of DSP calculation groups, the N paths of DSP calculation groups run completely and independently, each path of DSP calculation group starts a calculation program respectively, and N complete data processing processes are started in total;
parallel computing is carried out among all DSP computing units in each DSP computing group, and the parallel computing of all DSP computing units in each DSP computing group comprises the following steps: coarse-grained parallel computation, medium-grained parallel computation and fine-grained parallel computation;
the coarse-grained parallel computation adopts a pipeline parallel computation technology, and a plurality of algorithm tasks are distributed to each DSP computing unit according to a pipeline;
the medium-granularity parallel computing adopts a parallel distributed computing technology, and shares computing tasks with huge computing quantities to a plurality of DSP computing units in a DSP computing group for parallel computing;
and fine-grained parallel computing adopts an instruction set parallel computing technology, and after a computing task is divided into instruction sets, the instruction sets are distributed to different DSP computing units in parallel.
According to a further embodiment of the invention, the invention also provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the method as described above.
The method of the invention solves the defects of reliability, communication efficiency, signal processing capability and the like on the premise of equal real-time calculability.
Drawings
FIG. 1 is a flow chart of a parallel computing method for high-reliability bistatic SAR real-time imaging provided by the invention;
FIG. 2 is a block diagram of a parallel computing system for high-reliability bistatic SAR real-time imaging proposed by the present invention;
FIG. 3 is a schematic diagram of a FPGA according to the present invention arranging a plurality of data units in a computation group;
FIG. 4 is a schematic diagram of the overall process of parallel computing according to the present invention;
FIG. 5 is a schematic diagram of a distributed parallel computing model of the present invention;
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings.
As shown in fig. 1 and 2, this embodiment provides a parallel computing processing method for high-reliability bistatic SAR real-time imaging, where the method includes the following steps:
the system of the scheme comprises an FPGA, a plurality of DSP computing groups and a high-speed interconnection bus. Wherein, the FPGA selects Virtex-7 series of Xilinx company; the DSP selects TMS320C6678 of TI company; the high-speed interconnection bus can be selected from an SRIO link, a HyperLink link, a PCIE link and the like.
FPGA unit
The signal output of the phased array antenna is connected with the FPGA;
the FPGA instantiates N SRIO modules which are respectively connected with N paths of DSP computing groups;
DSP computing group
The DSP computing group consists of N TMS320C6678 of TI company;
the DSP computing group is connected by a hyperlink;
the output of each DSP computing group is connected with a terminal;
terminal control
Specifically, the FPGA receives a plurality of paths of parallel digital signals from a phase control antenna;
preprocessing the received multipath parallel digital signals to obtain preprocessed data;
dividing the preprocessed data into N paths of same data to be sent, setting a corresponding identifier for each path of data to be sent, and recording the corresponding relation between the identifier and the current DSP calculation group of the data to be sent when the data to be sent with the corresponding identifier is distributed to the N paths of DSP calculation groups;
in the invention, after the preprocessed data are obtained, the data need to be sent to the DSP computing group, according to the purpose of the invention, the adopted scheme is that the data are divided into N same contents and respectively sent to N paths of DSP computing groups, in order to enable the sent data to find the sending direction, the invention adopts the scheme that the data are provided with identifiers, the same N data are respectively provided with different identifiers, for example, the first data is provided with AN identifier A1, the second data is provided with AN identifier A2, and so on, the N data identifier is provided with AN AN, thus each data has a corresponding label, meanwhile, because the data are divided into N paths of DSP computing groups, namely, the data are divided into a first path of DSP computing group, a second path of DSP computing group, and so on to the Nth path of DSP computing group, when the data occur, the identifiers correspond to the paths, for example, A1 corresponds to the second way, A2 corresponds to the first way, and so on.
The N paths of DSP computing groups respectively receive the preprocessed data with the identifier information, detect whether the data is complete, if the data is incomplete, return the identifier information to request data retransmission, select the data corresponding to the identifier after receiving the identifier information, send the data to the DSP computing group corresponding to the identifier, and respectively and independently output one image after receiving the complete data.
Dividing the preprocessed data into N paths of same preprocessed data, distributing the preprocessed data to N paths of DSP computing groups, automatically detecting whether the data is sent to the N paths of DSP computing groups, if N-2 paths of data are not successfully sent to the DSP computing groups, sending out second-level warning information to prompt that the current data sending channel is in a middle-level breaking risk level and needs to draw attention, and if N-1 paths of data are not successfully sent to the DSP computing groups, sending out first-level warning information to prompt that the current data sending channel is in a high-level breaking risk level and needs to be processed in time.
When the data is judged to be successfully sent, the DSP computing group may be used to feed back the successfully received data, or send a data message to the DSP computing group after sending the data to prompt that the data transmission channel can normally receive the data, or other manners may be used, which is not limited in the present invention.
And the terminal receives all the output real-time images, performs image matching identification processing, and sends out corresponding control instructions according to identification results.
The FPGA preprocesses the multiple parallel digital signals from the phased array antenna. The preprocessing stage comprises vertical course phase compensation, range-direction FFT, range pulse pressure, coarse compensation and the like.
The FPGA starts N SRIO modules, the preprocessed data are simultaneously and parallelly distributed to N paths of DSP computing groups, the SRIO modules are also used for dividing the preprocessed data into N paths of same data to be sent, each path of data to be sent is provided with a corresponding identifier, and when the data to be sent with the corresponding identifier is distributed to the N paths of DSP computing groups, the corresponding relation between the identifier and the current DSP computing group of the data to be sent is recorded;
through the SRIO link, data is stored in the DDR3 protocol area of the DSP compute group (the first DSP in the select compute group). Each DSP calculation group receives the same original preprocessed data frame;
the N paths of DSP computing groups are used for detecting whether the data are complete or not after respectively receiving the preprocessed data with the identifier information, returning the identifier information to request data retransmission if the data are incomplete, and respectively and independently outputting one image after receiving the complete data.
And the data unit is the minimum data set for signal processing of the DSP calculation group. The FPGA assembles a plurality of original data frames according to a certain sequence. As shown in fig. 3.
In the figure, the data unit [ m x n ], m represents the number of rows of the original data frame in one data unit, and n represents the number of data points of one original data frame.
The method comprises the steps of dividing preprocessed data into N paths of same preprocessed data and distributing the preprocessed data to N paths of DSP calculation groups, assembling a plurality of preprocessed data frames according to a preset sequence and then distributing the data to the N paths of DSP calculation groups, automatically detecting whether the data are successfully sent to the N paths of DSP calculation groups after the data are sent, if N-2 paths of data are not successfully sent to the DSP calculation groups, sending secondary warning information, prompting that the current data sending channel is in a middle-level open circuit risk level and needing to draw attention, and if N-1 paths of data are not successfully sent to the DSP calculation groups, sending primary warning information, prompting that the current data sending channel is in a high-level open circuit risk level and needing to be processed in time.
The scheme adopted by the invention is that the data are respectively sent to N paths of DSP calculation groups, so that the information of the paths needs to be obtained in time, when the data are not sent successfully, the data sent by other paths cannot be influenced, but in order to ensure that the data are transmitted to the terminal in time, the corresponding risk level is set in the invention for timely management and control. As described above, if N-2 data are not successfully transmitted to the DSP computing group, a second-level warning message is sent to prompt that the current data transmission channel is in a middle-level risk level of circuit breaking, and attention needs to be paid, and if N-1 data are not successfully transmitted to the DSP computing group, a first-level warning message is sent to prompt that the current data transmission channel is in a high-level risk level of circuit breaking and needs to be processed in time
After the N paths of DSP calculation groups receive the preprocessed data, the N paths of DSP calculation groups respectively start calculation programs, and N complete signal processing processes are started in total.
After each DSP calculation group receives the notice of the FPGA, the DSP calculation groups respectively start calculation programs, and N complete signal processing processes are started. As shown in fig. 4.
The scheme is provided with N paths of DSP calculation groups, and each path of DSP calculation group does not have any data communication and control and runs completely independently. Therefore, even if a certain DSP computing group is attacked by malicious attacks or hardware self-damage, because the computing group adopts a distributed characteristic, each DSP computing group has a high degree of independence, and at this time, the remaining M (M < N) DSP computing groups will still continuously provide real-time image data, which strongly guarantees the availability of products and reliability under complex and severe environments.
From the overall view of the system, as long as the calculation performance of one DSP calculation group is optimized, the system can be easily expanded to N paths of DSP calculation groups, so that the complexity of system integration joint test is reduced, scientific research tasks such as equipment development, technical support and the like can be effectively guaranteed, and the system has important significance on the expandability of the system. For example, when the airborne bistatic SAR real-time imaging is performed, each DSP calculation group independently calculates an image, and if the system needs to perform real-time imaging for 500 milliseconds, only one DSP calculation group needs to be continuously optimized, and the calculation time is kept below 1 second.
And secondly, the N paths of DSP calculation groups do not have any data communication and control, and compared with the traditional mode that a plurality of DSPs are connected according to a pipeline (a large amount of data communication and control exist), the overall operation efficiency of the system is actually improved.
The method comprises the steps that calculation programs are respectively started, N complete data processing processes are started, the idea of parallel calculation is also adopted in each DSP calculation group, and efficient parallel signal calculation processes are realized by reasonably organizing a plurality of DSPs in the DSP calculation group.
No data communication and control exist among the N paths of DSP calculation groups, and the N paths of DSP calculation groups are completely and independently operated.
In particular, according to embodiments of the present invention,
the N-way DSP computational groups execute signal processing algorithms in parallel. The parallel computing idea is also adopted in each DSP computing group, and the efficient parallel signal computing process is realized by reasonably organizing a plurality of DSPs in the DSP computing group.
The bistatic SAR is generally divided into azimuth processing and range processing, and a common signal processing algorithm process includes: fixed point floating point conversion, Doppler center estimation, linear distance walking correction, matrix transposition, FFT, IFFT, quadratic distance pulse pressure correction, vertical course quadratic phase compensation, high order polynomial fitting, Doppler frequency modulation rate estimation, azimuth phase compensation, azimuth high order phase filtering, phase gradient self-focusing, geometric correction and the like.
In the signal processing process, the parallel computation in the DSP computation group can be defined in three levels: coarse-grained parallelism, medium-grained parallelism and fine-grained parallelism.
(1) Coarse grain parallelism
Coarse grain parallelism, designing the parallelism of calculation at the top layer, and selecting the coarse grain parallelism technology-pipeline parallelism technology. The pipeline parallel computing technology is that a plurality of algorithm tasks are equally distributed to each DSP computing unit, and the DSP computing unit which consumes the most time is used as an actual performance estimated value.
The time-consuming distribution is uniform in algorithm modules, the signal data properties are consistent, such as fixed point to floating point conversion, Doppler center estimation, linear distance walk correction, matrix transposition and the like, and the method can be deployed on the DSP0 and the DSP1 in the DSP calculation group in the figure.
(2) Medium granularity parallelism
The medium-granularity parallelism is realized, and the parallelism of calculation is designed in the middle layer, so that the method is an effective supplement to the coarse-granularity parallelism. The available medium granularity parallel technology, distributed parallel computing technology. The distributed (distribution) parallel computing technology is to share the computing task with huge computing amount to a plurality of DSP computing units for parallel computing.
For the algorithm module with rapid increase of consumption time and no relevance of signal data, such as Doppler frequency modulation rate estimation, phase gradient self-focusing, geometric correction and the like, the algorithm module can be deployed on the DSPs 1-N in the DSP calculation group in the figure.
For example, the doppler frequency modulation estimation module needs to estimate the frequency modulation of each range cell from the signal data (radar echo), and a typical algorithm is an image bias method. For data accumulation of 4096 distance units after 2048 times, the signal calculation amount needs 900ms on a single DSP, and if the signal calculation amount is distributed to 3 DSPs, the time is approximately 1/3 of the original time.
The parallel computing design idea of 'assembly line + distribution type' is fused, and the optimal performance of the signal processor can be more easily discovered. Of course, the software complexity of such parallel computing is high, and a good software architecture is required to support the application program.
(3) Fine grain parallelism
Fine-grained parallelism, generally referred to as instruction set parallelism. TMS320C6678 of TI company selected adopts Very Long Instruction Word (VLIW) architecture and rich SIMD assembly instructions, thus having Very powerful instruction set parallel function.
And after the signal processing process of the N paths of DSP calculation groups is finished, N SAR images are output in total. And sending the N images to the terminal module through the SRIO link.
And the terminal receives all real-time images, performs image matching identification processing, and then sends out a corresponding control instruction according to an identification result.
According to an embodiment of the invention, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of any of the methods described above.
The invention aims to provide a high-reliability parallel computing processing method, a high-reliability parallel computing processing system and a high-reliability parallel computing processing computer medium for bistatic SAR real-time imaging, and the defects in the aspects of reliability, communication efficiency, signal processing capacity and the like are overcome on the premise of equal real-time computing performance.
It will be evident to those skilled in the art that the embodiments of the present invention are not limited to the details of the foregoing illustrative embodiments, and that the embodiments of the present invention are capable of being embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the embodiments being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is obvious that the word "comprising" does not exclude other elements or steps, and the singular does not exclude the plural. Several units, modules or means recited in the system, apparatus or terminal claims may also be implemented by one and the same unit, module or means in software or hardware. The terms first, second, etc. are used to denote names, but not any particular order.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention and not for limiting, and although the embodiments of the present invention are described in detail with reference to the above preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the embodiments of the present invention without departing from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (5)
1. A parallel computing processing method for bistatic SAR real-time imaging is characterized by comprising the following steps:
receiving a plurality of paths of parallel digital signals from a phase-controlled antenna;
preprocessing the parallel digital signals;
dividing the preprocessed data into N paths of same data to be sent, sending the data to corresponding DSP computing groups, and independently outputting a sub-image by the N paths of DSP computing groups receiving complete data respectively;
the terminal receives all the output real-time images, performs image matching identification processing, and sends out corresponding control instructions according to identification results;
dividing the preprocessed data into N paths of same data to be sent, setting a corresponding identifier for each path of data to be sent, and recording the corresponding relation between the identifier and a DSP calculation group corresponding to the data to be sent when the data to be sent with the corresponding identifier is distributed to the N paths of DSP calculation groups;
after the N paths of DSP calculation groups respectively receive the preprocessed data with the identifier information, whether the data is complete or not is detected, if the data is incomplete, the identifier information is returned to request data retransmission, after the identifier information is received, the data corresponding to the identifier is selected, and the N paths of DSP calculation groups respectively and independently output one image after the complete data is received;
after dividing the preprocessed data into N paths of same preprocessed data and distributing the preprocessed data to N paths of DSP calculation groups, automatically detecting whether the data is successfully sent to the N paths of DSP calculation groups, if N-2 paths of data are not successfully sent to the DSP calculation groups, sending out second-level warning information to prompt that the current data sending channel is in a middle-level open circuit risk level and needs to draw attention, and if N-1 paths of data are not successfully sent to the DSP calculation groups, sending out first-level warning information to prompt that the current data sending channel is in a high-level open circuit risk level and needs to be processed in time;
the N paths of DSP computing groups do not have any data communication and control and run completely and independently, and each path of DSP computing group respectively starts a computing program to start N complete data processing processes;
parallel computing is carried out among all DSP computing units in each DSP computing group, and the parallel computing of all DSP computing units in each DSP computing group comprises the following steps: coarse-grained parallel computation, medium-grained parallel computation and fine-grained parallel computation;
the coarse-grained parallel computation adopts a pipeline parallel computation technology, and a plurality of algorithm tasks are distributed to each DSP computing unit according to a pipeline;
the medium-granularity parallel computing adopts a parallel distributed computing technology, and shares computing tasks with huge computing quantities to a plurality of DSP computing units in a DSP computing group for parallel computing;
and fine-grained parallel computing adopts an instruction set parallel computing technology, and after a computing task is divided into instruction sets, the instruction sets are distributed to different DSP computing units in parallel.
2. A parallel computing processing method according to claim 1,
adopting coarse-grained parallel deployment for the following computing tasks: fixed point to floating point conversion, Doppler center estimation, linear distance walking correction and matrix transposition;
adopting medium-granularity parallel deployment for the following computing tasks: doppler frequency modulation rate estimation, phase gradient self-focusing and geometric correction;
TMS320C6678 is selected for fine-grained parallel deployment, and
a Very Long Instruction Word (VLIW) architecture, and rich SIMD assembly instructions.
3. A parallel computing processing system for bistatic SAR real-time imaging is characterized by comprising an FPGA, N paths of DSP computing groups and a terminal, wherein the FPGA comprises an FPGA receiving unit, a preprocessing module and N SIRO modules, the terminal comprises a terminal control module, and the parallel computing processing system comprises a DSP processing module,
the FPGA receiving unit is used for receiving the multipath parallel digital signals from the phase control antenna;
the preprocessing module is used for preprocessing the parallel digital signals, selecting data corresponding to the identifier when a data retransmission request is received, and sending the data to the DSP computing group corresponding to the identifier;
the preprocessing module is also used for automatically detecting whether the data are successfully sent to the N paths of DSP computing groups; the SIRO module is used for dividing the preprocessed data into N paths of same data to be sent and distributing the data to N paths of DSP calculation groups;
the N paths of DSP calculation groups are used for respectively and independently calculating and outputting an image after respectively receiving the preprocessed data;
the terminal control module is used for receiving all output real-time images, performing image matching identification processing and sending out corresponding control instructions according to identification results;
the SIRO module is used for dividing the preprocessed data into N paths of same data to be sent, setting a corresponding identifier for each path of data to be sent, and recording the corresponding relation between the identifier and the current DSP calculation group of the data to be sent when the data to be sent with the corresponding identifier is distributed to the N paths of DSP calculation groups;
the N paths of DSP computing groups are used for detecting whether the data are complete or not after respectively receiving the preprocessed data with the identifier information, if the data are incomplete, the identifier information is returned to request data retransmission, and the N paths of DSP computing groups receiving the complete data respectively and independently output one image;
the preprocessing module is also used for automatically detecting whether the data are successfully transmitted to the N paths of DSP computing groups, if the N-2 paths of data are not successfully transmitted to the DSP computing groups, second-level warning information is sent out to prompt that the current data transmission channel is in a middle-level open circuit risk level and needs to be noticed, and if the N-1 paths of data are not successfully transmitted to the DSP computing groups, first-level warning information is sent out to prompt that the current data transmission channel is in a high-level open circuit risk level and needs to be processed in time;
the N paths of DSP computing groups do not have any data communication and control and run completely and independently, and each path of DSP computing group respectively starts a computing program to start N complete data processing processes;
parallel computing is carried out among all DSP computing units in each DSP computing group, and the parallel computing of all DSP computing units in each DSP computing group comprises the following steps: coarse-grained parallel computation, medium-grained parallel computation and fine-grained parallel computation;
the coarse-grained parallel computation adopts a pipeline parallel computation technology, and a plurality of algorithm tasks are distributed to each DSP computing unit according to a pipeline;
the medium-granularity parallel computing adopts a parallel distributed computing technology, and shares computing tasks with huge computing quantities to a plurality of DSP computing units in a DSP computing group for parallel computing;
and fine-grained parallel computing adopts an instruction set parallel computing technology, and after a computing task is divided into instruction sets, the instruction sets are distributed to different DSP computing units in parallel.
4. The parallel computing processing system of claim 3, wherein the FPGA further comprises a data unit configured to assemble the pre-processed plurality of data frames into data packets according to a predetermined order.
5. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 2.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101441271A (en) * | 2008-12-05 | 2009-05-27 | 航天恒星科技有限公司 | SAR real time imaging processing device based on GPU |
| CN106134476B (en) * | 2008-11-24 | 2012-09-05 | 西安电子科技大学 | Spaceborne real-time parallel data treatment system |
| CN103116872A (en) * | 2013-01-25 | 2013-05-22 | 西安电子科技大学 | Synthetic aperture radar (SAR) image high-speed processing system and method based on parallel digital signal processors (DSPs) |
| CN104284079A (en) * | 2013-10-10 | 2015-01-14 | 中国科学院光电研究院 | Satellite-borne remote sensing image intelligent identification device |
| CN106886177A (en) * | 2016-12-16 | 2017-06-23 | 北京华航无线电测量研究所 | A kind of Radar Signal Processing System |
| CN107301398A (en) * | 2017-06-23 | 2017-10-27 | 电子科技大学 | A kind of identification method of image target of synthetic aperture radar realized based on GPU |
| CN108132467A (en) * | 2017-12-23 | 2018-06-08 | 成都汇蓉国科微***技术有限公司 | The biradical Forward-looking SAR imaging methods of DSP+FPGA and imaging device based on enhanced ADC |
| CN108152816A (en) * | 2016-12-05 | 2018-06-12 | 南京理工大学 | Real-time SAR imaging systems and imaging method based on multi-core DSP |
| CN108983238A (en) * | 2018-07-27 | 2018-12-11 | 山东航天电子技术研究所 | A kind of spaceborne Ka wave band SAR Real Time Image System |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103616681B (en) * | 2013-12-04 | 2015-07-15 | 西安电子科技大学 | Radar imaging method based on Zynq-series FPGA |
| CN106872977A (en) * | 2016-12-28 | 2017-06-20 | 北京建筑大学 | A kind of chromatography SAR three-D imaging methods based on the weak orthogonal matching pursuit of segmentation |
| US20180275676A1 (en) * | 2017-03-21 | 2018-09-27 | Irvine Sensors Corporation | Apparatus for Enabling Autonomous Operation of Land Vehicle Convoys using a Robotic, Bio-Inspired Enterprise (ROBBIE) |
| CN107316038B (en) * | 2017-05-26 | 2020-04-28 | 中国科学院计算技术研究所 | SAR image ship target statistical feature extraction method and device |
| CN107829452B (en) * | 2017-11-12 | 2020-10-02 | 湖南科技大学 | Deep foundation pit construction monitoring and early warning technology integrating multiple sensors and foundation SAR |
-
2018
- 2018-12-30 CN CN201811646350.XA patent/CN109444886B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106134476B (en) * | 2008-11-24 | 2012-09-05 | 西安电子科技大学 | Spaceborne real-time parallel data treatment system |
| CN101441271A (en) * | 2008-12-05 | 2009-05-27 | 航天恒星科技有限公司 | SAR real time imaging processing device based on GPU |
| CN103116872A (en) * | 2013-01-25 | 2013-05-22 | 西安电子科技大学 | Synthetic aperture radar (SAR) image high-speed processing system and method based on parallel digital signal processors (DSPs) |
| CN104284079A (en) * | 2013-10-10 | 2015-01-14 | 中国科学院光电研究院 | Satellite-borne remote sensing image intelligent identification device |
| CN108152816A (en) * | 2016-12-05 | 2018-06-12 | 南京理工大学 | Real-time SAR imaging systems and imaging method based on multi-core DSP |
| CN106886177A (en) * | 2016-12-16 | 2017-06-23 | 北京华航无线电测量研究所 | A kind of Radar Signal Processing System |
| CN107301398A (en) * | 2017-06-23 | 2017-10-27 | 电子科技大学 | A kind of identification method of image target of synthetic aperture radar realized based on GPU |
| CN108132467A (en) * | 2017-12-23 | 2018-06-08 | 成都汇蓉国科微***技术有限公司 | The biradical Forward-looking SAR imaging methods of DSP+FPGA and imaging device based on enhanced ADC |
| CN108983238A (en) * | 2018-07-27 | 2018-12-11 | 山东航天电子技术研究所 | A kind of spaceborne Ka wave band SAR Real Time Image System |
Non-Patent Citations (2)
| Title |
|---|
| SAR数据处理算法及基于机群的处理***研究;黄倩;《中国博士学位论文全文数据库信息科技辑》;20070215;I136-61 * |
| 基于DSP的SAR图像并行处理***的设计与算法实现;张文科;《中国优秀硕士学位论文全文数据库信息科技辑》;20141115;I136-789 * |
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