CN118301272A - Low-delay video transmission and multipath switching device - Google Patents

Abstract

The invention provides a low-delay video transmission and multipath switching device, which belongs to the technical field of video processing and comprises the following components: the multi-channel input/output interface is used for receiving and outputting video signals in different formats; the buffer unit is connected with the multipath input interfaces; the storage unit is used for writing the cached video signal into the storage unit under the action of the write request signal; and the video signal is used for reading and outputting the stored video signal under the action of the reading request signal; the switching unit is used for switching the interface number and the video format under the action of an external control signal and outputting switching selection information; the processing unit is used for generating a write request signal according to the video signal received by the input interface; and the video signal processing unit is used for generating a read request signal according to the switching selection information and performing frame synchronization on reading and writing when the stored video signal reaches a preset threshold value. The beneficial effects are that: the total delay between the output video and the input video after switching is greatly reduced, the real-time performance of video transmission is remarkably improved, and the user experience and the system performance are improved.

Description

Low-delay video transmission and multipath switching device

Technical Field

The invention relates to the technical field of video processing, in particular to a low-delay video transmission and multiplexing device.

Background

The video transmission and switching device is a device for transmitting and switching video signals, and is commonly used in meeting rooms, studios, monitoring centers and the like. The apparatus typically has multiple inputs and one or more output interfaces, and may be capable of simultaneously connecting multiple video sources and display devices, with signals from the multiple video sources being transmitted to the display devices via various interfaces (e.g., HDMI, VGA, DVI, etc.).

The existing video transmission and switching device mainly performs multiple switching on the same video signal, such as an HDMI interface or a BNC video interface. However, in practical applications, the input-output interface conversion manner at the physical level often causes video signal attenuation, including defects such as brightness loss, brightness/chrominance crosstalk, phase and amplitude distortion, and the like.

In addition, with the continuous expansion of the application fields of video transmission and switching devices, the demands for switching devices with different video interfaces are gradually increasing. In the prior art, a video buffering technology adopting multi-frame buffering can cause a larger delay of video transmitted after video switching compared with video before switching, even a delay of 50-100 milliseconds is achieved, and the real-time performance of video transmission can be obviously reduced.

Disclosure of Invention

In order to solve the technical problems, the invention provides a low-delay video transmission and multiplexing device.

The technical problems solved by the invention can be realized by adopting the following technical scheme:

a low-latency video transmission and multiplexing device, comprising:

The multi-channel input/output interface comprises an input interface and an output interface, wherein each channel of input/output interface comprises an input interface and an output interface, the multiple channels of input interfaces are used for receiving video signals in different formats, and the multiple channels of output interfaces are used for outputting video signals in different formats;

The buffer unit is connected with multiple paths of input interfaces and used for buffering the video signals received by each path of input interfaces;

The storage unit is respectively connected with the cache unit and the plurality of output interfaces and is used for writing the video signals cached in the cache unit into the storage unit for storage under the action of a write request signal; the video signal is read from the storage unit under the action of a read request signal, and is transmitted to one or more of the input interfaces for output;

The switching unit is connected with a plurality of input/output interfaces and is used for switching the number of the input/output interfaces and corresponding video formats under the action of an external control signal and outputting switching selection information;

The processing unit is respectively connected with the buffer unit and the storage unit and is used for generating the write request signal according to the video signal received by the input interface; and the video signal processing unit is used for generating the read request signal according to the switching selection information and performing frame synchronization on reading and writing when the video signal stored in the storage unit reaches a preset threshold value.

Preferably, the preset threshold is not more than one frame.

Preferably, the preset threshold is one quarter frame.

Preferably, the storage unit includes at least two memories, and the at least two memories are respectively connected with the buffer unit and the multiplexing output interface.

Preferably, the processing unit includes:

The write request generation module is used for generating a write request signal group according to the multiple paths of video signals and generating the write request signals according to the write request signal group and the corresponding video formats;

a read request generation module for generating the read request signal according to the switching selection information;

and the frame synchronization module is used for performing read-write frame synchronization when the number of paths corresponding to the switching selection information in the storage unit and the video signals stored in the video format reach a preset threshold.

Preferably, the write request generation module includes:

The arbitration sub-module is used for arbitrating the write request signal group according to the transmission bandwidth priority of the video format when the video formats of the multiple paths of the input interfaces are different, and determining the priority of the write request signal in the write request signal group;

and the polling sub-module is used for polling the write request signals in the write request signal group when the video formats of the multiple paths of the input interfaces are the same.

Preferably, the processing unit further comprises:

and the format conversion module is connected with a plurality of input interfaces and is used for converting video signals with different formats received by the input interfaces into preset formats.

Preferably, the switching unit includes:

the first knob is used for responding to the road number switching operation of the user and generating a first knob signal;

a second knob for generating a second knob signal in response to a video format switching operation of the user;

the external control signal includes the first knob signal and/or the second knob signal.

Preferably, the method further comprises:

the power supply unit is respectively connected with the multipath input and output interface, the buffer unit, the storage unit, the switching unit and the processing unit and is used for providing a direct current power supply with preset voltage amplitude;

and the display unit is respectively connected with the processing unit and the power supply unit.

Preferably, the processing unit comprises a field programmable gate array chip;

the buffer unit comprises a first-in first-out buffer memory;

The memory unit comprises two double-edge synchronous dynamic random access memories.

The technical scheme of the invention has the advantages that:

The invention supports the input and output of different video formats, and does not need to carry out the conversion of an input and output interface at a physical layer, thereby avoiding the problem of video signal attenuation caused by the conversion of the interface at the physical layer; and meanwhile, when the stored video signal reaches a preset threshold value, read-write frame synchronization is carried out, so that the total delay between the output video and the input video after switching is greatly reduced, the real-time performance of video transmission is remarkably improved, and the user experience and the system performance are improved.

Drawings

FIG. 1 is a block diagram of a low-latency video transmission and multiplexing device according to a preferred embodiment of the present invention;

FIG. 2 is a block diagram of a processing unit in accordance with the preferred embodiment of the present invention;

FIG. 3 is a block diagram illustrating a write request generation module in accordance with a preferred embodiment of the present invention;

FIG. 4 is a block diagram illustrating a processing unit in accordance with a preferred embodiment of the present invention;

FIG. 5 is a schematic diagram of a low-delay video transmission and multiplexing device according to the preferred embodiment of the present invention;

FIG. 6 is a schematic view of another angle of the device according to the preferred embodiment of the present invention;

FIG. 7 is a schematic diagram showing a layout of a device according to a preferred embodiment of the present invention;

FIG. 8 is a schematic diagram of the hidden menu bar for the I/O path number and video format in the preferred embodiment of the present invention;

FIG. 9 is a schematic diagram of a read/write DDR flow according to a preferred embodiment of the invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.

The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.

Referring to fig. 1, in accordance with the above-mentioned problems occurring in the prior art, a low-delay video transmission and multiplexing device is now provided, which comprises:

The multi-channel input/output interface 1, each channel of input/output interface includes an input interface and an output interface respectively, the multi-channel input interface (11, 12, & gt, 1N) is used for receiving video signals with different formats, and the multi-channel output interface (21, 22, & gt, 2N) is used for outputting video signals with different formats;

The buffer unit 2 is connected with multiple paths of input interfaces (11, 12, & gt, 1N) and is used for buffering video signals received by the input interfaces;

The storage unit 3 is respectively connected with the buffer unit 2 and the multiplexing output interfaces (21, 22, & gt, 2N) and is used for writing the video signals buffered in the buffer unit 2 into the storage unit 3 for storage under the action of a write request signal; and for reading the stored video signal from the memory unit 3 under the effect of a read request signal and transmitting it to one or more of the input interfaces (21, 22, 2N) for output;

The switching unit 4 is connected with the multiple paths of input/output interfaces 1 and is used for switching the paths of the input/output interfaces and corresponding video formats under the action of an external control signal and outputting switching selection information;

The processing unit 5 is respectively connected with the buffer unit 2 and the storage unit 3 and is used for generating a write request signal according to the video signal received by the input interface; and is used for producing the read request signal according to switching the selective information, and carry on the frame synchronization to the read-write when the video signal stored in storage unit 3 reaches a preset threshold value.

Specifically, in this embodiment, by setting multiple input/output interfaces 1, input/output of different video formats are supported, and no input/output interface conversion is required at the physical layer, so as to avoid video signal attenuation caused by physical layer interface conversion.

Further, aiming at the problem that in the prior art, a video buffering technology using multi-frame buffering is adopted, compared with a video before switching, a video transmitted after switching is delayed greatly, even 50-100 milliseconds are reached, so that the real-time performance of video transmission is obviously reduced.

As a preferred embodiment, the processing unit includes a Field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA) chip.

Specifically, in this embodiment, the processing unit may be implemented by using an FPGA chip, which is used for receiving and sending video signals, buffering video signals, and DDR read/write, so that the features of high speed, low power consumption, and strong flexibility can be implemented. The FPGA chip can realize complex algorithm and logic functions and has higher parallel processing capability. The FPGA chip can be reprogrammed as required, and is suitable for various application scenes.

Further, the number of the input interfaces and the output interfaces can be set according to actual needs, for example, three paths, four paths or more. Each path of input/output interface can be configured with different interface protocols according to requirements, such as High-definition multimedia interface (High-Definition Multimedia Interface, HDMI) protocol, all-copper thickened welding type video transmission universal interface (BayonetNut Connector, BNC) protocol, and serial digital interface (SERIAL DIGITAL INTERFACE, SDI) protocol. For HDMI signals, the FPGA may use an HDMI interface module to receive and decode video data. For BNC and SDI signals, the FPGA can use existing specialized interface circuitry to receive and process video data.

Furthermore, besides common HDMI, SDI, BNC interfaces, the device can increase or decrease corresponding input/output interfaces according to actual requirements, so that multiplexing is realized, and the application range is wide. Meanwhile, the device has the characteristic of low-delay switching while matching with a plurality of video formats with different input/output, and the video transmission difference before and after switching is less than one frame, so that real-time transmission is basically realized.

As a preferred embodiment, the buffer unit 2 comprises a first-in first-out (First Input First Output, FIFO) buffer memory.

Specifically, in the present embodiment, the buffer unit 2 uses a first-in first-out (FIFO) principle, that is, the data that first enters the buffer will be replaced first.

Further, when the cache unit is full, new data will replace the data that entered the cache earliest.

In some embodiments, the buffering unit 2 is configured to buffer one or more received video signals in multiple input interfaces (11, 12, 1N). Upon receiving the multiple video signals, the buffering unit 2 may simultaneously buffer the multiple video signals.

In some embodiments, the buffer unit 2 may allocate an independent buffer space for each input interface according to the number of input interfaces set, so as to ensure that each input interface has enough buffer space to store data, and meanwhile, avoid data collision and competition between different input interfaces, and improve the concurrent processing capability of the system. By way of example and not limitation, it is assumed that 4 input interfaces are provided, and by dividing the buffer unit 2 into 4 portions, each portion corresponds to one input interface, each portion has its own buffer space for storing data received by the input interface, and each input interface can independently perform data processing without mutual interference, thereby greatly improving the concurrent processing capability of the system.

Specifically, the capacity of the buffer space of each path is more than 2 lines of corresponding video signal data. For example, for 1080P resolution video, one line of data contains 1080 YUV422 data, where YUV422 represents 2Y values, 1U value, and 1V value for every 4 pixels. Thus, one line of data shares 1080/4=270 sets of YUV422 data. For the YUV422 format, the Y value of each pixel occupies 8 bits (1 byte), while the U and V values each occupy 8 bits (1 byte). Thus, each set of YUV422 data occupies a total of 2 bytes. Thus, a row of data occupies 270×2=540 bytes in total. Since one frame image contains a plurality of lines of data, the data size of the entire 1080P image is 540×1080= 583,200 bytes, that is, about 583KB. More than two rows include at least 2160 bytes of data.

As a preferred embodiment, the storage unit 3 comprises at least two memories, which are connected to the buffer unit 2 and the multiplexing interfaces (21, 22, 2N), respectively. Further, two memories use Double Data Rate (DDR SDRAM).

Specifically, in the present embodiment, the memory unit 3 is implemented by using the DDR memory technology, and the data transmission speed is improved by transmitting data on the rising edge and the falling edge, that is, transmitting data twice in each clock cycle.

Further, the memory unit 3 may select a corresponding DDR version according to needs, for example, the DDR version supported by the memory unit is determined according to the chip of the processing unit, which may be a third generation double edge synchronous dynamic random access memory (DDR 3) or may be a fourth generation double edge synchronous dynamic random access memory (DDR 4). In the embodiment of the invention, the storage unit 3 takes two DDR3 as an example, and 2 DDR3 forms a 32-bit image cache interface.

In a preferred embodiment, the preset threshold is not more than one frame.

Specifically, in this embodiment, when the data amount of the video signal with the DDR3 stored therein reaches the preset threshold, the frame synchronization is performed while the DDR3 read request is issued, so that the read DDR3 is ensured to be delayed by no more than one frame than the write DDR 3. When the input and output video transmission formats are 1080P.50HZ, the delay consumed in DDR3 is N.20ms, wherein N represents a preset threshold value, and N is less than or equal to 1 frame; the comprehensive delay of data processing after DDR3 in and DDR3 out is not more than 20ms, and the video transmission difference before and after switching is less than one frame, so that real-time transmission is basically realized.

1080P means that the resolution of the video is 1920×1080 pixels, that is, the number of horizontal pixels of the video is 1920 and the number of vertical pixels is 1080.

As a preferred embodiment, the preset threshold is one quarter frame.

Specifically, in this embodiment, when the data amount of the video signal with the DDR3 reaches a quarter frame, the frame synchronization is performed while the DDR3 read request is issued, so that the readout DDR3 is only delayed by a quarter frame compared with the write DDR3 (for example, 1080P video, the write DDR3 reaches 1080/4=270 lines). When the input and output video transmission formats are 1080px50hz, the delay consumed in DDR3 is 0.25x20ms=5ms, i.e. the integrated delay of data processing after DDR3 and DDR3 is not more than 5ms, so as to ensure that the total delay of output video after switching is 10ms compared with the total delay of input video.

As a preferred embodiment, wherein, as shown in fig. 2, the processing unit 5 comprises:

A write request generation module 51, configured to generate a write request signal group according to the multiple video signals, and generate a write request signal according to the write request signal group and the corresponding video format;

a read request generation module 52 for generating a read request signal according to the switching selection information;

The frame synchronization module 53 is configured to perform read-write frame synchronization when the number of channels corresponding to the switching selection information in the storage unit and the video signal stored in the video format reach a preset threshold.

Specifically, when multiple paths of video signals are cached in the FIFO, a write request signal group is generated; because of the multipath video input, the DDR write request signal group needs to be arbitrated, corresponding write request signals are generated, and only one path of input write DDR is needed at a time.

Further, a read request signal of DDR is issued to the corresponding input video signal according to the switching selection information corresponding to the external control signal (controlled by the two knobs). And simultaneously, when the video signal correspondingly stored into DDR3 reaches a quarter frame, the frame synchronization is carried out while the DDR3 read request signal is sent out to the video signal, so that the DDR is ensured to be read out and only delayed by a quarter frame compared with the DDR is ensured to be written in.

As a preferred embodiment, wherein, as shown in fig. 3, the write request generation module 51 includes:

an arbitration sub-module 511, configured to arbitrate the write request signal group according to the transmission bandwidth priority of the video format when the video formats of the multiple input interfaces are different, and determine the priority of the write request signal in the write request signal group;

The polling submodule 512 is configured to poll the write request signals in the write request signal group when the video formats of the multiple input interfaces are the same.

Specifically, in the case of multiple video inputs, it is necessary to arbitrate DDR write requests in order to write data buffered in the FIFO to the DDR for video data storage.

In this embodiment, when the formats of the three paths of video input are different, the arbitration will sort according to the size of the input video format, give the video data with the highest transmission bandwidth high priority, and give the video data with the lower transmission bandwidth low priority, so as to ensure that all the three paths of video data can be buffered in DDR 3.

When the formats of the three paths of input videos are the same, DDR writing adopts a polling mode, and the first path, the second path and the third path of input video data are sequentially cached.

In some embodiments, in order to ensure that no screen-splash occurs during the switching process, DDR3 needs to wait for the completion of the output of the previous frame of video data and send a read request signal to acquire the input video data after switching, so that the total delay time during the switching process is 10ms of the output time of one frame of video data plus the image processing time, which amounts to 30ms (in case of 1080px 50 hz).

As a preferred embodiment, wherein, as shown in fig. 4, the processing unit 5 further comprises:

The format conversion module 54 is connected to the multiple input interfaces (11, 12,..1N) and is configured to convert video signals of different formats received by the input interfaces into predetermined formats.

Specifically, in this embodiment, after receiving video signals in different formats (such as HDMI, BNC, or SDI protocols), the FPGA decodes the signals, and then converts the video signals into a unified video storage format. The predetermined format may be YUV422 format, performing 2:1 horizontal sampling and vertical full sampling on luminance and chrominance of the video signal; the predetermined format may also be other common video storage formats including, but not limited to, RGB, YUV420, YUV444, for example.

As a preferred embodiment, wherein, as shown in fig. 5, 6 and 7, the switching unit 4 includes:

a first knob 41 for generating a first knob signal in response to a user's road number switching operation;

A second knob 42 for generating a second knob signal in response to a video format switching operation by a user;

the external control signal includes a first knob signal and/or a second knob signal.

Specifically, in this embodiment, two knobs are disposed on the device housing, and when two knobs are pressed for more than 3 seconds, a hidden menu bar is superimposed on the display screen of the device, and the combination adjustment is performed by adopting a hidden menu bar manner, so as to realize the switching of multiple input/output interfaces. The hidden menu bar details of the two knobs are shown in fig. 8. The first knob 41 may be referred to as a "way number knob" for making a selection of the number of input/output video ways; the second knob 42 may be referred to as a "video format knob" for making a selection of an input/output video format.

Further, by adjusting the hidden menu bar, the number of input/output video passes and video formats can be switched. If no operation is performed within 10 seconds in the hidden menu bar, the hidden menu bar will be exited.

In some embodiments, each path of video signal input/output format is selected through two knobs, the number of paths of video input is selected in a left-handed mode, and the video output format is selected in a right-handed mode, so that 3 paths of different video inputs are converted into 3 paths of video output formats, and the video output formats can be freely selected according to requirements. The switching speed is determined by the knob response speed.

As a preferred embodiment, as shown in fig. 1, the method further includes:

The power supply unit 6 is respectively connected with the multi-channel input/output interface 1, the buffer unit 2, the storage unit 3, the switching unit 4 and the processing unit 5, and is used for providing a direct current power supply with a preset voltage amplitude. The preset voltage amplitude may be 12V.

Further, as shown in fig. 5, 6 and 7, a power input terminal 61 is further provided on the device housing, and the power input terminal 61 is connected to the power unit 6 to convert the input power into a voltage amplitude required by the later-stage circuit.

As a preferred embodiment, as shown in fig. 1 and 7, the method further includes: and a display unit 7 connected to the processing unit 5 and the power supply unit 6, respectively.

Specifically, in the present embodiment, the display unit 7 is implemented by a liquid crystal display, and the output interface is output through a low voltage differential signaling technology interface 70 (LVDS) and displayed on the liquid crystal display.

In the preferred embodiment, the processing unit 5 may further perform video processing such as clipping, zooming, splicing, fusing, character stacking on multiple paths of video signals, so as to further expand the application range of the video switching device, and may be very conveniently applied to fields such as a/V system conference room, home theater, control center, exhibition hall, audio-visual education, monitoring room, and video post-production.

As an example, as shown in fig. 9, a flow chart of low-delay four-channel video transmission and switching device for reading and writing DDR3 includes the following steps:

four-way video input signal processing: the FPGA chip receives video signals in different formats (such as HDMI, BNC, SDI), and converts the video signals into a unified video storage format (such as YUV422 format);

FIFO buffers video data: buffering each path of video signals through the FIFO, wherein the buffering capacity of each path of FIFO is more than 2 lines of corresponding video signals; for example 1080P, one line of data is 1080 YUV422 data, and 2 lines are 2160 bytes total;

generating DDR write requests and write DDR request arbitration: the data buffered in the FIFO is written into the DDR for video signal storage, and at this time, because of the multipath video input, the DDR write request needs to be arbitrated. Arbitration is performed specifically according to the following two cases:

when four paths of video input formats are different, the arbitration can be ordered according to the sizes of the input video formats, the highest transmission bandwidth is given high priority, the low transmission bandwidth is given low priority, and the four paths of video data are ensured to be cached in the DDR;

when four paths of input video formats are the same, DDR is written by using a polling mode, and the first path of input video data, the second path of input video data, the third path of input video data and the fourth path of input video data are buffered in sequence.

Read DDR request arbitration and read video signal processing: and selecting to send out DDR read requests to corresponding input video signals according to the switching selection signals output by the knob control. When the video signal stored in DDR3 reaches one quarter of a frame, the frame synchronization is performed while the DDR3 read request is sent to the video signal.

In the switching process, after all the video signals of the previous frame are output, the DDR reading request is sent out from the input video signals after the switching in the switching selection signals, so that the phenomenon of screen display caused by flickering of the screen can be avoided

In the switching process, therefore, a total of time t1+time T2 of the integrated delay of the input DDR3 and output DDR3 processing for waiting for one frame of video signal output is required. By way of example, T1 is 20ms and T2 is 10ms for 1080P resolution and 50HZ refresh rate, for a total of about 30ms.

It should be noted that the video input/output is not limited to 4 paths, and the number of interfaces can be increased or decreased according to actual requirements. The corresponding hardware can also be replaced by DDR4 and higher-speed FPGA to expand the number of paths of video input/output to 8, 16, 32 paths or more, so that the expandability is high.

The technical scheme has the advantages that: the invention supports the input and output of different video formats, and does not need to carry out the conversion of an input and output interface at a physical layer, thereby avoiding the problem of video signal attenuation caused by the conversion of the interface at the physical layer; and meanwhile, when the stored video signal reaches a preset threshold value, read-write frame synchronization is carried out, so that the total delay between the output video and the input video after switching is greatly reduced, the real-time performance of video transmission is remarkably improved, and the user experience and the system performance are improved.

The foregoing is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the embodiments and scope of the present invention, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations herein, which should be included in the scope of the present invention.

Claims (10)

1. A low-latency video transmission and multiplexing device, comprising:

The multi-channel input/output interface comprises an input interface and an output interface, wherein each channel of input/output interface comprises an input interface and an output interface, the multiple channels of input interfaces are used for receiving video signals in different formats, and the multiple channels of output interfaces are used for outputting video signals in different formats;

The buffer unit is connected with multiple paths of input interfaces and used for buffering the video signals received by each path of input interfaces;

The storage unit is respectively connected with the cache unit and the plurality of output interfaces and is used for writing the video signals cached in the cache unit into the storage unit for storage under the action of a write request signal; the video signal is read from the storage unit under the action of a read request signal, and is transmitted to one or more of the input interfaces for output;

The switching unit is connected with a plurality of input/output interfaces and is used for switching the number of the input/output interfaces and corresponding video formats under the action of an external control signal and outputting switching selection information;

The processing unit is respectively connected with the buffer unit and the storage unit and is used for generating the write request signal according to the video signal received by the input interface; and the video signal processing unit is used for generating the read request signal according to the switching selection information and performing frame synchronization on reading and writing when the video signal stored in the storage unit reaches a preset threshold value.

2. The low-latency video transmission and multiplexing device according to claim 1, wherein the preset threshold is not more than one frame.

3. The low-latency video transmission and multiplexing device according to claim 2, wherein the preset threshold is one-quarter frame.

4. The low-latency video transmission and multiplexing device according to claim 1, wherein the storage unit comprises at least two memories, the at least two memories being respectively connected to the buffer unit and the multiplexing interface.

5. The low-latency video transmission and multiplexing device according to claim 1, wherein the processing unit comprises:

The write request generation module is used for generating a write request signal group according to the multiple paths of video signals and generating the write request signals according to the write request signal group and the corresponding video formats;

a read request generation module for generating the read request signal according to the switching selection information;

and the frame synchronization module is used for performing read-write frame synchronization when the number of paths corresponding to the switching selection information in the storage unit and the video signals stored in the video format reach a preset threshold.

6. The low-latency video transmission and multiplexing device according to claim 5, wherein the write request generation module comprises:

The arbitration sub-module is used for arbitrating the write request signal group according to the transmission bandwidth priority of the video format when the video formats of the multiple paths of the input interfaces are different, and determining the priority of the write request signal in the write request signal group;

and the polling sub-module is used for polling the write request signals in the write request signal group when the video formats of the multiple paths of the input interfaces are the same.

7. The low-latency video transmission and multiplexing device according to claim 1, wherein the processing unit further comprises:

and the format conversion module is connected with a plurality of input interfaces and is used for converting video signals with different formats received by the input interfaces into preset formats.

8. The low-delay video transmission and multiplexing switching apparatus according to claim 1, wherein the switching unit comprises:

the first knob is used for responding to the road number switching operation of the user and generating a first knob signal;

a second knob for generating a second knob signal in response to a video format switching operation of the user;

the external control signal includes the first knob signal and/or the second knob signal.

9. The low-latency video transmission and multiplexing device according to claim 1, further comprising:

the power supply unit is respectively connected with the multipath input and output interface, the buffer unit, the storage unit, the switching unit and the processing unit and is used for providing a direct current power supply with preset voltage amplitude;

and the display unit is respectively connected with the processing unit and the power supply unit.

10. The low-latency video transmission and multiplexing device according to claim 1, wherein the processing unit comprises a field programmable gate array chip;

the buffer unit comprises a first-in first-out buffer memory;

The memory unit comprises two double-edge synchronous dynamic random access memories.