CN109411418B - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN109411418B
CN109411418B CN201710784754.4A CN201710784754A CN109411418B CN 109411418 B CN109411418 B CN 109411418B CN 201710784754 A CN201710784754 A CN 201710784754A CN 109411418 B CN109411418 B CN 109411418B
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layer
encapsulation layer
interposer
thickness
packaging
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CN109411418A (zh
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蔡文山
郑子企
林长甫
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Geometry (AREA)

Abstract

一种电子封装件及其制法，通过于中介板的上侧设有电子元件及形成有包覆该电子元件的第一封装层，且于该中介板的下侧设有多个导电元件及包覆所述导电元件的第二封装层，以于该电子封装件进行热循环时，该第一封装层的收缩力与该第二封装层的收缩力会相互抵销，而减缓该中介板翘曲情况。

Description

电子封装件及其制法
技术领域
本发明有关一种半导体封装结构，尤指一种能减缓结构翘曲的电子封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。据此，目前应用于芯片封装领域的技术，例如芯片尺寸构装(Chip Scale Package，简称CSP)、芯片直接贴附封装(Direct Chip Attached，简称DCA)或多芯片模组封装(Multi－ChipModule，简称MCM)等覆晶型态的封装模组、或将芯片立体堆叠化整合为三维积体电路(3DIC)芯片堆叠技术等，藉以达到缩小芯片封装面积及缩短讯号传递路径的目的。
图1A至1B为现有三维集成电路芯片堆叠的封装结构1的制法的剖面示意图。如图1A所示，提供一硅中介板(Through Silicon interposer，简称TSI)10，该硅中介板10具有相对的置晶侧10a与转接侧10b、及连通该置晶侧10a与转接侧10b的多个导电硅穿孔(Through-silicon via，简称TSV)100，且该转接侧10b上形成有一重布线路结构101，再将半导体芯片19的电极垫190通过多个焊锡凸块102电性结合至该置晶侧10a上，并以底胶192包覆所述焊锡凸块102，且形成封装胶体18于该硅中介板10上，以包覆该半导体芯片19。接着，如图1B所示，于该重布线路结构101上通过多个如焊锡凸块的导电元件103电性结合封装基板17的焊垫170，并以另一底胶172包覆所述导电元件103。
惟，现有封装结构1的制法中，于图1A的制程中，该硅中介板10的置晶侧10a形成有封装胶体18，而该转接侧10b上仅形成有导电元件103，导致该封装胶体18于热循环过程中会产生一收缩力，致使图1A所示的结构发生严重的翘曲，导致后续于第1B所示的制程中，所述导电元件103无法准确对位结合该封装基板17的焊垫170，因而造成电性连接不良。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种电子封装件，包括：中介板，其具有相对的第一侧与第二侧；电子元件，其设于该中介板的第一侧上；第一封装层，其形成于该中介板的第一侧上以包覆该电子元件；多个导电元件，其设于该中介板的第二侧上；以及第二封装层，其形成于该中介板的第二侧上以包覆所述导电元件，且令所述导电元件的部分表面外露出该第二封装层。
本发明复提供一种电子封装件的制法，包括：提供一具有相对的第一侧与第二侧的中介板，且于该中介板的第一侧上设置电子元件；于该中介板的第一侧上形成包覆该电子元件的第一封装层；于该中介板的第二侧上形成多个导电元件；以及于该中介板的第二侧上形成包覆所述导电元件的第二封装层，且令所述导电元件的部分表面外露出该第二封装层。
前述的电子封装件及其制法中，该第一封装层与第二封装层为环氧树酯所形成者，且该环氧树酯包含有树脂材及填充材，其中，该第一封装层的树酯材含量与该第二封装层的树酯材含量不同。例如，该第二封装层的树酯材含量大于第一封装层的树酯材含量。进一步地，该第一封装层与该第二封装层的填充材含量不相同，例如，该第一封装层的填充材含量大于该第二封装层的填充材含量。
前述的电子封装件及其制法中，该第一封装层的体积大于该第二封装层的体积。例如，该第一封装层的宽度等于该第二封装层的宽度。或者，该第一封装层的厚度大于该第二封装层的厚度。亦或，该第一封装层的厚度与该第二封装层的厚度的比值大于或等于1.3。
前述的电子封装件及其制法中，该第一封装层的宽度等于该中介板的宽度。
前述的电子封装件及其制法中，该第二封装层的宽度等于该中介板的宽度。
前述的电子封装件及其制法中，所述导电元件凸伸出该第二封装层。
前述的电子封装件及其制法中，该第二封装层的厚度小于该导电元件的厚度的一半。
由上可知，本发明的电子封装件及其制法，主要通过在中介板的第一侧与第二侧上分别形成第一封装层与第二封装层，以于制程中进行热循环时，该第一封装层的收缩力与该第二封装层的收缩力会相互抵销，使该中介板的应力得以平衡，因而减缓该中介板翘曲情况，故相较于现有技术，本发明的电子封装件于后续制程中，所述导电元件能准确对位结合该封装基板的电性接点，避免电性连接不良的问题。
附图说明
图1A至1B为现有封装结构的制法的剖面示意图；
图2A至2E为本发明的电子封装件的制法的剖面示意图；以及
图3为图2E的后续制程的剖面示意图。
符号说明：
1,3 封装结构 10 硅中介板
10a 置晶侧 10b 转接侧
100 导电硅穿孔 101 重布线路结构
102,240 焊锡凸块 103,20 导电元件
17 封装基板 170 焊垫
172,192,31 底胶 18 封装胶体
19 半导体芯片 190 电极垫
2 电子封装件 200 凸块底下金属层
21 第一封装层 22 第二封装层
23 中介板 23a 第一侧
23b 第二侧 230 导电穿孔
231 重布线路层 24 电子元件
30 电子装置 300 电性接点
S 切割路径 W 宽度
T,H1,H2 厚度。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至2E为本发明的电子封装件2的制法的剖面示意图。
如图2A所示，提供一具有相对的第一侧23a与第二侧23b的中介板23，且该中介板23的第一侧23a上设有多个电子元件24。
于本实施例中，该中介板23为半导体板材，如硅基板、玻璃板或其它适当板材，其具有多个连通该第一侧23a与第二侧23b的导电穿孔230、及至少一设于该第一侧23a上并电性连接该导电穿孔230的重布线路层(redistribution layer，简称RDL)231。另外，该重布线路层231亦可选择设于该第二侧23b上或同时布设于该中介板23的第一侧23a与第二侧23b，并电性连接该导电穿孔230。
再者，该电子元件24为主动元件、被动元件或其组合者，其中，该主动元件为例如半导体芯片，而该被动元件为例如电阻、电容及电感。例如，该电子元件24为半导体芯片，其通过多个焊锡凸块240以覆晶方式电性结合该重布线路层231；或者，该电子元件24可通过多个焊线(图略)以打线方式电性连接该重布线路层231；亦或，该电子元件24可直接接触该重布线路层231。然而，有关该电子元件24电性连接该中介板23的方式不限于上述。
如图2B所示，形成第一封装层21于该中介板23的第一侧23a上以包覆该电子元件24。
于本实施例中，形成该第一封装层21的材质为聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(epoxy)或封装材。
如图2C所示，形成多个导电元件20于该中介板23的第二侧23b上，使所述导电元件20电性连接该导电穿孔230。
于本实施例中，可依需求形成凸块底下金属层(Under Bump Metallurgy，简称UBM)200于该导电穿孔230与该导电元件20之间，即所述导电元件20对应设于各该导电穿孔230的端面上，且该导电元件20为如焊球或其它金属块体(如铜柱)，并无特别限制。
如图2D所示，形成第二封装层22于该中介板23的第二侧23b上以包覆所述导电元件20，且令所述导电元件20的部分表面外露于该第二封装层22。
于本实施例中，形成该第二封装层22的材质为聚酰亚胺(PI)、干膜、环氧树脂或封装材，其可相同或不相同于该第一封装层21的材质。
再者，所述的第一及第二封装层的构成包含主要材质与填充材(filler)，若上述第一及第二封装层的主要材质为环氧树脂，且包含有树脂材及填充材，该第一封装层21的树酯材(epoxy resin)含量与该第二封装层22的树酯材含量不同，其中，该第二封装层22的树酯材含量大于第一封装层21的树酯材含量，使该第二封装层22于树酯材较多时收缩力较大，而可提供一大于该第一封装层21的收缩力的反向收缩力，藉以降低翘曲的发生机率。具体地，该第一封装层21的树酯材含量少于20％重量百分比，且该第二封装层22的树酯材含量大于或等于20％重量百分比。换言之，该第一封装层21与该第二封装层22的填充材含量不相同，且该第一封装层21的填充材含量大于该第二封装层22的填充材含量。具体地，该第一封装层21的填充材含量大于或等于80％重量百分比，且该第二封装层22的填充材含量小于80％重量百分比。
又，该第一封装层21的体积大于该第二封装层22的体积。例如，当该第一封装层21的宽度等于该第二封装层22的宽度(或两者均等于该中介板23的宽度)时，该第一封装层21的厚度H1大于该第二封装层22的厚度H2。较佳地，该第一封装层21的厚度H1与该第二封装层22的厚度H2的比值(H1/H2)大于或等于1.3，以达成较佳的翘曲控制。
另外，所述导电元件20的部分表面(如端部)凸伸出该第二封装层22以外露于该第二封装层22，例如，该第二封装层22的厚度H2小于该导电元件20相对该第二侧23b的厚度T的一半(即H2＜T/2)。然而，于其它实施例中，亦可以其它方式外露于该第二封装层22，例如，所述导电元件20的端面齐平该第二封装层22的下表面、或该第二封装层22形成多个外露所述导电元件20的开孔等，故有关所述导电元件20外露于该第二封装层22的方式并无特别限制。
如图2E所示，沿如图2D所示的切割路径S进行切单制程，以获得多个电子封装件2。
于本实施例中，于后续制程中，如图3所示，该电子封装件2可通过所述导电元件20结合至一如封装基板的电子装置30上，再以底胶31包覆所述导电元件20，以制成一封装结构3，其中，该电子装置30具有多个电性接点300以结合所述导电元件20。
本发明的制法，通过于该中介板23的第一侧23a与第二侧23b上分别形成该第一封装层21与第二封装层22，以当该电子封装件2进行热循环时，该第一封装层21的收缩力与该第二封装层22的收缩力会相互抵销，使该中介板23的相对两侧(第一侧23a与第二侧23b)的应力得以平衡，因而能减缓该中介板23翘曲状况，故相较于现有技术，本发明的电子封装件2于后续制程中，所述导电元件20能准确对位结合该封装基板30的电性接点300，因而能避免电性连接不良的问题。
本发明提供一种电子封装件2，包括：一中介板23、一电子元件24、第一封装层21、多个导电元件20以及第二封装层22。
所述的中介板23具有相对的第一侧23a与第二侧23b。
所述的电子元件24设于该中介板23的第一侧23a上。
所述的第一封装层21形成于该中介板23的第一侧23a上以包覆该电子元件24。
所述的导电元件20设于该中介板23的第二侧23b上。
所述的第二封装层22形成于该中介板23的第二侧23b上以包覆所述导电元件20，且令所述导电元件20的部分表面外露出该第二封装层22。
于一实施例中，该第一与第二封装层21,22为环氧树酯，且该第一封装层21的树酯材含量与该第二封装层22的树酯材含量不同。例如，该第二封装层22的树酯材含量大于第一封装层21的树酯材含量。进一步，该第一封装层21与该第二封装层22的填充材含量不相同，例如，该第一封装层21的填充材含量大于该第二封装层22的填充材含量。
于一实施例中，该第一封装层21的体积大于该第二封装层22的体积。例如，该第一封装层21的宽度W等于该第二封装层22的宽度W，该第一封装层21的厚度H1大于该第二封装层22的厚度H2。再者，该第一封装层21的厚度H1与该第二封装层22的厚度H2的比值大于或等于1.3。
于一实施例中，该第一封装层21的宽度W等于该中介板23的宽度W。
于一实施例中，该第二封装层22的宽度W等于该中介板23的宽度W。
于一实施例中，所述导电元件20凸伸出该第二封装层22。
于一实施例中，该第二封装层22的厚度H2小于该导电元件20相对该第二侧23b的厚度T的一半。
综上所述，本发明的电子封装件及其制法，通过该中介板的第一侧与第二侧上分别形成该第一与第二封装层的设计，以于进行热循环时，能减缓该中介板翘曲情况，故本发明的电子封装件于后续制程中，所述导电元件能准确对位结合该封装基板的电性接点，因而能避免电性连接不良的问题。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何所属领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (18)

1.一种电子封装件，其特征为，该电子封装件包括：
中介板，其具有相对的第一侧与第二侧；
电子元件，其设于该中介板的第一侧上；
第一封装层，其形成于该中介板的第一侧上以包覆该电子元件；
多个导电元件，其设于该中介板的第二侧上；以及
第二封装层，其形成于该中介板的第二侧上以包覆所述导电元件，且令所述导电元件的部分表面外露出该第二封装层，
其中，该第一封装层与该第二封装层为环氧树脂所形成者，该环氧树脂包含有树脂材及填充材，该第二封装层的树脂材含量大于第一封装层的树脂材含量，该第一封装层与该第二封装层的填充材含量不相同，且该第一封装层的体积大于该第二封装层的体积，使得所述第一封装层的收缩力与所述第二封装层的收缩力在制程中进行热循环时会相互抵消，所述中介板的应力得以平衡。
2.根据权利要求1所述的电子封装件，其中，该第一封装层的填充材含量大于该第二封装层的填充材含量。
3.根据权利要求1所述的电子封装件，其中，该第一封装层的宽度等于该第二封装层的宽度。
4.根据权利要求1所述的电子封装件，其中，该第一封装层的厚度大于该第二封装层的厚度。
5.根据权利要求1所述的电子封装件，其中，该第一封装层的厚度与该第二封装层的厚度的比值大于或等于1.3。
6.根据权利要求1所述的电子封装件，其中，该第一封装层的宽度等于该中介板的宽度。
7.根据权利要求1所述的电子封装件，其中，该第二封装层的宽度等于该中介板的宽度。
8.根据权利要求1所述的电子封装件，其中，所述导电元件凸伸出该第二封装层。
9.根据权利要求1所述的电子封装件，其中，该第二封装层的厚度小于该导电元件的厚度的一半。
10.一种电子封装件的制法，其特征为，该制法包括：
提供一具有相对的第一侧与第二侧的中介板，且于该中介板的第一侧上设置电子元件；
于该中介板的第一侧上形成包覆该电子元件的第一封装层；
于该中介板的第二侧上设置多个导电元件；以及
于该中介板的第二侧上形成包覆所述导电元件的第二封装层，且令所述导电元件的部分表面外露出该第二封装层，
其中，该第一封装层与该第二封装层为环氧树脂所形成者，该环氧树脂包含有树脂材及填充材，该第二封装层的树脂材含量大于第一封装层的树脂材含量，该第一封装层与该第二封装层的填充材含量不相同，且该第一封装层的体积大于该第二封装层的体积，使得所述第一封装层的收缩力与所述第二封装层的收缩力在制程中进行热循环时会相互抵消，所述中介板的应力得以平衡。
11.根据权利要求10所述的电子封装件的制法，其中，该第一封装层的填充材含量大于该第二封装层的填充材含量。
12.根据权利要求10所述的电子封装件的制法，其中，该第一封装层的宽度等于该第二封装层的宽度。
13.根据权利要求10所述的电子封装件的制法，其中，该第一封装层的厚度大于该第二封装层的厚度。
14.根据权利要求10所述的电子封装件的制法，其中，该第一封装层的厚度与该第二封装层的厚度的比值大于或等于1.3。
15.根据权利要求10所述的电子封装件的制法，其中，该第一封装层的宽度等于该中介板的宽度。
16.根据权利要求10所述的电子封装件的制法，其中，该第二封装层的宽度等于该中介板的宽度。
17.根据权利要求10所述的电子封装件的制法，其中，所述导电元件凸伸出该第二封装层。
18.根据权利要求10所述的电子封装件的制法，其中，该第二封装层的厚度小于该导电元件的厚度的一半。
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