CN109378969A - The DC-DC converter of the device of variation with reply input voltage - Google Patents
The DC-DC converter of the device of variation with reply input voltage Download PDFInfo
- Publication number
- CN109378969A CN109378969A CN201810281754.7A CN201810281754A CN109378969A CN 109378969 A CN109378969 A CN 109378969A CN 201810281754 A CN201810281754 A CN 201810281754A CN 109378969 A CN109378969 A CN 109378969A
- Authority
- CN
- China
- Prior art keywords
- mentioned
- voltage
- terminal
- pulse
- width modulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 45
- 230000005611 electricity Effects 0.000 claims description 19
- 238000012360 testing method Methods 0.000 claims description 2
- 230000002708 enhancing effect Effects 0.000 description 18
- 230000008859 change Effects 0.000 description 13
- 238000002955 isolation Methods 0.000 description 13
- 230000001360 synchronised effect Effects 0.000 description 13
- 229920001621 AMOLED Polymers 0.000 description 9
- 230000033228 biological regulation Effects 0.000 description 9
- 238000001514 detection method Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 5
- 239000011513 prestressed concrete Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 210000001367 artery Anatomy 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 210000003462 vein Anatomy 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000518 rheometry Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Dc-Dc Converters (AREA)
Abstract
The present invention discloses a kind of DC-DC boost converter, it is characterized in that, including booster converter, above-mentioned booster converter includes NMOS and PMOS, is controlled in a manner of making the grid voltage of above-mentioned PMOS have grid off voltage always during above-mentioned NMOS periodically converts on-off state.Above-mentioned DC-DC converter includes: the DC voltage conversion portion of switching type；Pulse-width modulation waveform signal control part, as generating in order to be contained in above-mentioned DC voltage conversion portion switch movement and the pulse-width modulation waveform signal control part of pulse-width modulation waveform signal that provides, the duty ratio of above-mentioned pulse-width modulation waveform signal are determined according to the feedback voltage inputted to pulse-width modulation waveform signal control part；And generate the feed circuit portion of above-mentioned feedback voltage, above-mentioned feedback voltage is generated and subtracting the value directlyed proportional to the DC input voitage inputted to above-mentioned DC voltage conversion portion from the value directly proportional to above-mentioned error voltage, above-mentioned error voltage to and above-mentioned DC voltage conversion portion output DC output voltage it is relevant value between scheduled reference voltage difference directly proportional.
Description
Technical field
The present invention relates to DC-DC converters, more particularly to also can provide the DC- of required output voltage to high input voltage
The structure of DC booster converter relates to the use of the technology of the changing value correction output voltage of the input voltage of DC-DC converter.
Background technique
In order to provide the DC voltage inputted to active matrix organic light-emitting diode (AMOLED) plate, need to pass through change
The grade of the DC input voitage provided by battery or scheduled DC power supply is suitble to the organic hair of above-mentioned active matrix to change into
The DC output voltage of near-infrafed photodiodes plate, this function can be executed by DC-DC converter.
Alternatively, being needed to provide the DC output voltage inputted to battery charged when carrying out wireless charging
Change the direct current output electricity for being suitble to above-mentioned battery by changing the grade of DC input voitage provided by wireless charging device
Pressure, this function can also be executed by DC-DC converter.
In addition, there are many application programs applied to DC-DC converter.DC-DC converter is mainly used for by electricity
Pond provides the mobile phone of electric power and the portable electronic device of laptop etc..This electronic device generally includes a few height electricity
Road, but there is each sub-circuit the voltage level of its own to require item, and this voltage level is different from provided by battery
Voltage level.
For example, mobile phone display device come using battery as power supply using.Cell voltage with to device carry out using and by
Gradually decline.This leads to the variation of the input voltage of DC-DC converter, i.e. pipeline (Line) changes.For example, especially in active matrix
In organic light emitting diode DC-DC converter, the subtle shake of DC output voltage will lead to the scintillation of picture
(flicker), it is therefore preferred that the DC-DC converter of active matrix organic light-emitting diode plate should have outstanding route
Regulation characteristic.
DC-DC converter can provide DC output voltage by receiving DC input voitage.At this point, inputting electricity in direct current
In the case that pressure generates variation, the value of DC output voltage, which is inaccurate, is fixed on set target value, thus can produce table
The phenomenon that revealing predictive error value, the variation of this DC output voltage, which has to change, receives above-mentioned DC output voltage
The problem of working characteristics of device.
Fig. 1 is the attached drawing for illustrating the working principle of common booster converter.
Common booster converter shown in part (a) of Fig. 1 can include: inductor 211 has and applies cell voltage VBAT
A terminal；Common node LX is defined in the other end of above-mentioned inductor 211；NMOS110, drain electrode and above-mentioned common section
Point is connected；PMOS120, source electrode (or drain electrode) are connected with above-mentioned common node；Output voltage VO UT, from above-mentioned PMOS120
Drain electrode (or source electrode) output；And capacitor 12, a terminal are connected with the drain electrode of above-mentioned PMOS120.Above-mentioned NMOS110's
The another terminal of source electrode and above-mentioned capacitor can be connected with reference potential (ground).Moreover, can be to the grid of above-mentioned NMOS110
Apply switching signal SW_NG, switching signal SW_PG can be applied to the grid of above-mentioned PMOS120.Above-mentioned PMOS120
Source electrode and drain electrode position it is interchangeable.Hereinafter, cell voltage VBAT above-mentioned in the present specification is referred to alternatively as input voltage
VIN.Also, above-mentioned output voltage VO UT is referred to alternatively as output voltage ELVDD.
Above-mentioned switching signal SW_NG and above-mentioned switching signal SW_PG can be periodically to take turns rheology respectively
The mode for changing low value and high level into generates change.In one embodiment, above-mentioned switching signal SW_NG and above-mentioned switch can be made
Switching signal SW_PG does not maintain on-state simultaneously.Alternatively, in one embodiment, above-mentioned switching signal SW_NG and upper
Complementary value can be had by stating switching signal SW_PG.According to based on above-mentioned switching signal SW_NG and above-mentioned switching
Signal SW_PG maintains the ratio of the time span of on-state and off-state come the duty ratio defined, and the value of output voltage can
Become different.
(b) of Fig. 1 is shown partially to maintain on-state and above-mentioned PMOS120 to maintain off-state in above-mentioned NMOS110
In the case of circuit work.At this point, above-mentioned switching signal SW_NG can have high level, above-mentioned switching signal SW_PG
There can be high level.At this point, electric current provided by battery can be flowed by NMOS110.The state shown in part (b) of Fig. 1
In the case where stabilization, the potential difference at above-mentioned 211 both ends of inductor is 0, and therefore, the voltage of above-mentioned common node is input voltage
VIN。
(c) of Fig. 1 above-mentioned NMOS110 shown partially maintains off-state and above-mentioned PMOS120 maintains the feelings of on-state
The work of circuit under condition.At this point, above-mentioned switching signal SW_NG can have low value, above-mentioned switching signal SW_PG can
With low value.In this case, electric current provided by battery can be flowed by PMOS120.In the part (b) institute from Fig. 1
When the state shown is converted to the conversion section of state shown in part (c) of Fig. 1, the electric current that is flowed in above-mentioned inductor 211
The continuity of value is protected, and therefore, will increase the voltage of common node LX.At this point, output voltage VO UT can have
The value of the voltage between the source electrode of PMOS120 and drain electrode is subtracted from the voltage of common node.
If state shown in part (c) from Fig. 1 is converted to state shown in part (b) of Fig. 1, output voltage again
The value of VOUT can be maintained based on capacitor.
In common booster converter shown in Fig. 1, output voltage VO UT and input voltage VIN have following formula 1
Relationship.
Formula 1
VOUT={ 1/ (1-D) } × VIN
Wherein, D < 1, in general, D < 0.8
That is, circuit shown in Fig. 1 is so that the mode of value of the value greater than VIN of VOUT works.That is, booster converter is only
Produce the output voltage greater than input voltage.In general, minimum VOUT=VIN+0.2V.
Booster converter shown in fig. 1 can be used as what generation was supplied to active matrix organic light-emitting diode (AMOLED) plate
The DC-DC converter of voltage.In order to provide the DC voltage inputted to active matrix organic light-emitting diode plate, change need to be passed through
The grade of DC input voitage provided by battery or predetermined direct current power supply is suitable for the organic hair of above-mentioned active matrix to change into
The DC output voltage of near-infrafed photodiodes plate provides, and this function can be executed by DC-DC converter.
Alternatively, in order to provide the DC output voltage inputted to the battery unit to charge when wireless charging, it need to be by changing
Become the grade of DC input voitage provided by wireless charging device, to change the direct current output electricity for being suitable for above-mentioned battery into
Pressure, this function can also be executed by DC-DC converter.
In general, the active matrix organic light-emitting diode plate of boost type is designed to pass through reception with DC-DC converter
VBAT (2.9V~4.4V) exports preset selected objective target value, such as 4.6V.That is, boosting difference can have 0.2V~
The range of 1.7V.But make cell voltage VBAT with 4.5V's or more because of bad wired charger and quick charge recently
Voltage is electrically charged.In this case, the output voltage of booster converter can have the value of above-mentioned target value or more.If to active
The voltage of matrix/organic light emitting diode (AMOLED) plate input is greater than the value being pre-designed, then causes picture bad.
Summary of the invention
The technical issues of solution
The purpose of the present invention is to provide following booster converters, that is, the case where cell voltage VBAT is greater than 4.4V
Under, it is in an off state the PMOS120 of output end by detecting, so that output voltage VO UT be made to reach 4.6V.That is, this hair
Bright is designed to provide following booster converter, that is, when range of the cell voltage VBAT in 2.9~(4.4+VTHP),
When range i.e. when cell voltage in 2.9V~5.2V, guarantee that output voltage reaches 4.6.
In the present invention, to solve the above-mentioned problems, it provides as the variation of DC input voitage can make DC-DC converter
DC output terminal provided by DC output voltage variation minimize technology.That is, providing enhancing DC-DC converter
The technology of line regulation (line regulation) characteristic.
Technical solution
The DC-DC boost converter that a viewpoint according to the present invention provides includes: booster converter, including NMOS and
PMOS；And mode control unit, the input voltage VBAT of opposite above-mentioned booster converter input is detected, thus according to being examined
The above-mentioned input voltage surveyed makes the above-mentioned booster converter be transformed to first mode or second mode.At this point, above-mentioned first mode
For to make the grid voltage of above-mentioned PMOS that there are grid always during above-mentioned NMOS periodically converts on-off state
The mode that the mode of pole off voltage is controlled, above-mentioned second mode are periodically to convert on-off in above-mentioned NMOS
The grid voltage of above-mentioned PMOS is made also to convert the mode that the mode of on-off state is controlled during state.
At this point, when above-mentioned input voltage be greater than predetermined value when, above-mentioned booster converter in the first mode described above into
Row work can make when above-mentioned input voltage and above-mentioned predetermined value are identical or less than above-mentioned predetermined value
Booster converter is stated to work with above-mentioned second mode.
At this point, the conversion between above-mentioned first mode and above-mentioned second mode can have the sluggishness based on above-mentioned input conversion
Phenomenon characteristic.
At this point, be greater than the moment of predetermined first value in above-mentioned input voltage, above-mentioned booster converter is from above-mentioned the
Two modes are converted to above-mentioned first mode, later, are less than in above-mentioned input voltage smaller than above-mentioned predetermined first value pre-
First the moment of determining second value, above-mentioned booster converter can be made to be converted to above-mentioned second mode from above-mentioned first mode.
It is connected at this point, above-mentioned booster converter can enhance circuit with efficiency.Moreover, above-mentioned efficiency enhancing circuit includes the
One diode and the second diode, apply the output voltage of above-mentioned booster converter to the anode terminal of above-mentioned first diode,
Apply above-mentioned input voltage to the anode terminal of above-mentioned second diode, the cathode terminal of above-mentioned first diode can be with above-mentioned the
The cathode terminal of two diodes is connected.Moreover, the cathode terminal of above-mentioned first diode and above-mentioned second diode can with it is upper
State the first isolation ring (ISO_ring) terminal, the post tensioned unbonded prestressed concrete terminal of above-mentioned PMOS and the second isolation ring end of above-mentioned PMOS of PMOS
Son is connected.
DC-DC boost converter provided by another viewpoint includes booster converter according to the present invention, above-mentioned boosting inverter
Device includes NMOS and PMOS, to make the grid of above-mentioned PMOS during above-mentioned NMOS periodically converts on-off state
Always there is voltage the mode of grid off voltage to be controlled.
Above-mentioned DC-DC boost converter can further include inductor.At this point, applying to a terminal of above-mentioned inductor to above-mentioned
The input voltage of booster converter input, the another terminal of above-mentioned inductor are connected with the drain electrode of above-mentioned NMOS, above-mentioned NMOS
Source electrode be connected with reference potential, the drain electrode of above-mentioned NMOS is connected with the first terminal of above-mentioned PMOS, the of above-mentioned PMOS
Two-terminal can be the output terminal of above-mentioned booster converter.
It is connected at this point, above-mentioned booster converter can enhance circuit with efficiency.At this point, above-mentioned efficiency enhancing circuit may include
First diode and the second diode.Moreover, applying the defeated of above-mentioned booster converter to the anode terminal of above-mentioned first diode
Voltage out applies above-mentioned input voltage to the anode terminal of above-mentioned second diode, the cathode terminal of above-mentioned first diode with
The cathode terminal of above-mentioned second diode is connected, the cathode terminal of above-mentioned first diode and above-mentioned second diode can with it is upper
The the second isolation ring terminal for stating the first isolation ring terminal of PMOS, the post tensioned unbonded prestressed concrete terminal of above-mentioned PMOS and above-mentioned PMOS is connected.
DC-DC boost converter provided by another viewpoint includes booster converter and efficiency enhancing electricity according to the present invention
Road, above-mentioned booster converter include NMOS and PMOS, and above-mentioned efficiency enhancing circuit is connected with above-mentioned booster converter.At this point,
Above-mentioned efficiency enhancing circuit includes first diode and the second diode, is applied to the anode terminal of above-mentioned first diode above-mentioned
The output voltage of booster converter applies the input voltage of above-mentioned booster converter to the anode terminal of above-mentioned second diode,
The cathode terminal of above-mentioned first diode is connected with the cathode terminal of above-mentioned second diode, above-mentioned first diode and above-mentioned
The cathode terminal of second diode can be with the first isolation ring terminal of above-mentioned PMOS, the post tensioned unbonded prestressed concrete terminal of above-mentioned PMOS and above-mentioned
The second isolation ring terminal of PMOS is connected.
There is the DC-DC converter of pulse-width modulation waveform signal control part to input for a viewpoint according to the present invention, opposite direction
The variation of DC input voitage is detected, so that the variation of above-mentioned DC input voitage detected is used for pulsewidth modulation control
System.Even if DC input voitage is shaken as a result, prevented also from the shake of DC output voltage, to enhance DC-DC converter
Line regulation characteristics.
The DC-DC converter that a viewpoint according to the present invention provides includes: the DC voltage conversion portion of switching type；
Pulse-width modulation waveform signal control part controls the movement for the switch for being contained in above-mentioned DC voltage conversion portion as generating
Pulse-width modulation waveform signal pulse-width modulation waveform signal control part, the duty ratio of above-mentioned pulse-width modulation waveform signal according to
The feedback voltage V of pulse-width modulation waveform signal control part inputCTo determine；And generate the feed circuit portion of error voltage.This
When, above-mentioned feedback voltage VCBy from above-mentioned error voltage VERRDirectly proportional value a × VERRSubtract with to above-mentioned DC voltage
The DC input voitage V of transformation component inputBATDirectly proportional value b × VBATAnd it generates, above-mentioned error voltage VERRWith with above-mentioned direct current
The DC output voltage V of voltage transformating part outputOUTRelevant value VSENSEWith scheduled reference voltage VREFBetween difference it is directly proportional.
Here, D/C voltage converting unit can be above-mentioned boost converter, including opening in DC voltage converting unit
Pass can be above-mentioned NMOS and PMOS.
At this point, DC-DC converter of the invention may also include the feedback voltage generating unit for generating above-mentioned feedback voltage.And
And above-mentioned feedback voltage generating unit may include the first current mirror, the second current mirror and third current mirror.Moreover, the first current mirror
It generates by the error current I directly proportional to above-mentioned error voltageERRThe error current I for being reflected to be replicatedERR, third
Current mirror generate by with above-mentioned DC input voitage VBATDirectly proportional input current IBATReflected to be replicated is defeated
Enter electric current IBAT, above-mentioned second current mirror generation is by the above-mentioned input current I being replicatedBATReflected to be replicated
Two input current IBAT, export from the above-mentioned error current I being replicatedERRSubtract the above-mentioned second input current I being replicatedBAT's
Feedback current IX.Moreover, above-mentioned feedback voltage V can be generated from above-mentioned feedback current IXC。
At this point, above-mentioned feedback voltage VCIt can be with above-mentioned DC input voitage VBATIt is inversely proportional.
At this point, the size of above-mentioned feedback voltage can be directly proportional to the dutyfactor value of above-mentioned pulse-width modulation waveform signal.
At this point, above-mentioned first current mirror may include the 11st PMOS transistor and the 12nd PMOS transistor.Moreover, above-mentioned
The source terminal of 11st PMOS transistor and the source terminal of above-mentioned 12nd PMOS transistor can be connected with feeding terminal.
Moreover, the gate terminal of above-mentioned 11st PMOS transistor can respectively with the gate terminal of above-mentioned 12nd PMOS transistor and on
The drain terminal for stating the 11st PMOS transistor is connected.Moreover, above-mentioned second current mirror may include the 13rd PMOS transistor
And the 14th PMOS transistor.Moreover, source terminal and above-mentioned 14th PMOS transistor of above-mentioned 13rd PMOS transistor
Source terminal can be connected with above-mentioned feeding terminal.Moreover, the gate terminal of above-mentioned 13rd PMOS transistor can respectively with
The gate terminal of above-mentioned 14th PMOS transistor and the drain terminal of above-mentioned 14th PMOS transistor are connected.On moreover,
Stating third current mirror may include the 11st NMOS transistor and the tenth bi-NMOS transistor.Moreover, above-mentioned 11st NMOS crystal
The source terminal of the source terminal of pipe and above-mentioned tenth bi-NMOS transistor can be connected with the first reference potential.Moreover, above-mentioned
The gate terminal of 11st NMOS transistor can respectively with above-mentioned tenth bi-NMOS transistor gate terminal and the above-mentioned 12nd
The drain terminal of NMOS transistor is connected.Moreover, the drain terminal of above-mentioned 11st NMOS transistor can be with the above-mentioned 12nd
The drain terminal of PMOS transistor is connected.Moreover, the drain terminal of above-mentioned tenth bi-NMOS transistor can be with the above-mentioned 13rd
The drain terminal of PMOS transistor is connected.
At this point, above-mentioned DC voltage conversion portion may include inductor, the first NMOS transistor and the first PMOS transistor.And
And a terminal of above-mentioned inductor can be connected with the input terminal of above-mentioned DC-DC converter, the another terminal of above-mentioned inductor
It can be connected with the drain terminal of the drain terminal of above-mentioned first NMOS transistor and above-mentioned first PMOS transistor, above-mentioned first
The source terminal of PMOS transistor can be connected with the output terminal of above-mentioned DC-DC converter.
At this point, pulse-width modulation waveform signal control part may include gate driving portion, using the arteries and veins in above-mentioned gate driving portion
Wide modulation voltage value controls above-mentioned first NMOS transistor and the first PMOS transistor.
At this point, pulse-width modulation waveform signal control part can further include current detecting part and gradient compensation portion.Moreover, above-mentioned electricity
Stream test section can detect the electric current of the source terminal of above-mentioned first NMOS transistor, by above-mentioned electric current detected
Peak value detected and exported.Moreover, above-mentioned gradient compensation portion can pass through the output valve and tool of the above-mentioned current detecting part of reception
There is the sawtooth voltage in predetermined period to export offset voltage.
At this point, above-mentioned pulse-width modulation waveform signal control part can further include comparing section, latch portion and gate driving portion.And
And above-mentioned comparing section can export logical value by receiving above-mentioned offset voltage and above-mentioned feedback voltage, above-mentioned latch portion can
Above-mentioned pwm voltage value is exported by receiving above-mentioned logical value and the above-mentioned gate driving portion of clock direction of signal.
At this point, above-mentioned feed circuit portion may include first resistor, second resistance and error amplifier.Moreover, above-mentioned first
One terminal of resistance can be connected with the output terminal of above-mentioned DC-DC converter, the another terminal of above-mentioned first resistor and second
One terminal of resistance can be connected with the inversing input terminal of above-mentioned error amplifier jointly.Moreover, above-mentioned second resistance is another
One terminal can be connected with the first reference potential, and the non-inverting input terminal of above-mentioned error amplifier can be with the second reference potential phase
Connection.
Invention effect
It therefore,, can also even if cell voltage VBAT is caused to increase because of battery overcharge using the present invention
The output voltage that can ensure that normal display quality is provided.
According to the present invention, the DC input voitage (ex: cell voltage, or be located at wireless charging of opposite DC-DC converter input
The output voltage of the rectifier (Rectifier) of lower one end of electric coil) variation detected, value detected can be used for
Thus pulse width modulation controlled can enhance to enhance the line regulation characteristics of DC-DC converter and receive above-mentioned DC-DC conversion
The craftmanship of the device of the DC output voltage of device.Therefore, it can design according to the present invention in opposite direction for example using the dress of battery
The converter used in the sensitive device of variation of the voltage of inputs such as set, so that the production of line regulation characteristics enhancing can be obtained
Product.
Detailed description of the invention
Fig. 1 is the figure for illustrating the working principle of common booster converter.
Fig. 2 is the figure for showing the structure of DC-DC boost converter of the invention.
Fig. 3 be for illustrate one embodiment of the invention booster converter and can be connected above-mentioned efficiency enhancing electricity
The working principle when structure on road and the voltage possessed by applying to the booster converter are greater than the cell voltage VBAT of 4.4V
Figure.
Fig. 4 is for illustrating between two operating modes provided by the booster converter of one embodiment of the invention mutually
The figure of the technology of conversion.
Fig. 5, which is shown, carries out mould to the output voltage based on the mode conversion in one embodiment of the invention illustrated in fig. 4
Quasi- result.
Fig. 6 is to show to the booster converter of one embodiment of the invention from the case where the work of trigger switch (STS) mode
Under the chart of result simulated of efficiency.
Fig. 7 and Fig. 8 shows the internal structure of the DC-DC converter of a previous embodiment.
Fig. 9 graphically shows current value, the node N2 of inductor 50 according to a previous embodiment according to the time
The voltage value of~N4 and pulse-width signal.
Figure 10 shows the structure chart of the DC-DC converter 200 of one embodiment of the invention, and Figure 11 shows one embodiment of the invention
DC-DC converter circuit diagram.
Figure 12 shows the internal circuit of the feedback voltage generating unit 60 of one embodiment of the invention.
Figure 13 is the figure for illustrating the difference of the feedback voltage of the size based on input current of one embodiment of the invention.
Specific embodiment
Hereinafter, being illustrated with reference to the attached drawing for enclosing the embodiment of the present invention.But the present invention is not limited in this theory
Embodiment illustrated in bright book can be embodied with various other embodiments.Term used in the present specification is used for
Help understands embodiment, rather than intended limitation the scope of the present invention.Also, if opposite meaning is not explicitly indicated that in sentence,
Then singular form used below further includes plural form.
The particular voltage level stated in embodiment explained below be it is specific for ease of description, need to pay attention to
It is that, even if changing the voltage value, thought of the invention will also maintain.
In the present specification, for the sake of convenient, the grid voltage that can will be provided to be in an off state NMOS or PMOS
Referred to as " grid off voltage ".
Fig. 2 is the figure for showing the structure of DC-DC boost converter of the invention.
The DC-DC converter 1 of one embodiment of the invention may include booster converter 210, efficiency enhancing circuit 220 and mode
Control unit 230.
Booster converter 210 can have structure identical with booster converter shown in fig. 1.Efficiency enhances circuit 220
In the electricity from trigger switch mode for improving efficiency as the operating mode in the content being described in detail below based on Fig. 3
Road, specific structure will describe in the related description to Fig. 3.
Circuit 220 can be enhanced to efficiency and input cell voltage VBAT and output voltage VO UT.
Mode control unit 230 it is executable by detection cell voltage VBAT come according to value detected come to booster converter
The function that 210 operating mode is converted.
Fig. 3 be for illustrate one embodiment of the invention booster converter and can be connected above-mentioned efficiency enhancing electricity
The working principle when structure on road and the voltage possessed by applying to the booster converter are greater than the cell voltage VBAT of 4.4V
Figure.
In booster converter shown in Fig. 3, the PMOS120 selectivity of previous booster converter that can be shown in Fig. 1
Ground adds above-mentioned " efficiency enhances circuit 220 ".Referring to Fig. 3, above-mentioned efficiency enhancing circuit 220 may include first diode 221 and
Second diode 222.At this point, the output of above-mentioned booster converter 210 can be applied to the anode terminal of above-mentioned first diode 221
Voltage VOUT can apply above-mentioned input voltage VBAT, above-mentioned first diode to the anode terminal of above-mentioned second diode 222
221 cathode terminal can be connected with the cathode terminal of above-mentioned second diode 222.At this point, above-mentioned first diode 221 and on
The voltage for stating the cathode terminal of the second diode 222 is referred to alternatively as " isolation voltage ".
At this point, the cathode terminal of above-mentioned first diode 221 and above-mentioned second diode 222 can be with the first of above-mentioned PMOS
Second isolation ring terminal 125 of isolation ring terminal 121, the post tensioned unbonded prestressed concrete terminal 122 of above-mentioned PMOS and above-mentioned PMOS is connected.It can base
The work of PMOS body diode (PMOS parasitic diode) is isolated in above-mentioned isolation voltage.
123 terminal of source electrode (drain electrode) of above-mentioned PMOS120 is connected with common node LX1, the drain electrode of above-mentioned PMOS120
(source electrode) terminal 124 can provide output voltage ELVDD.
The the first isolation ring terminal 111 and the second isolation ring terminal 115 of NMOS110 in Fig. 3 can receive cell voltage
VBAT.Moreover, the post tensioned unbonded prestressed concrete terminal 112 and source terminal 113 of NMOS110 are connected with reference potential PGND.And NMOS110
Drain terminal 114 can be connected with common node LX1.
One terminal of inductor 211 can receive cell voltage VBAT, the another terminal of above-mentioned inductor 211 can with it is above-mentioned total
It is connected with node LX1.
Booster converter 210 according to an embodiment of the invention can be worked with multiple modes.At this point, Fig. 3 is shown in electricity
The working principle for the first mode that cell voltage VBAT works in the case where being 4.4V or more.Hereinafter, in the present specification, it will be above-mentioned
First mode is referred to as from trigger switch (STS, self triggering switch) mode.
During maintaining the above-mentioned mode from trigger switch, it is disconnected high grid can be applied to the grid of above-mentioned PMOS120 always
Open voltage (ex:4.6V), so that above-mentioned PMOS120 maintains off-state.
At this point, electric current can not pass through NMOS110 if carrying out the conversion from on-state to off-state to NMOS110
Flowing.Moreover, because to the grid of PMOS120 supply so that PMOS120 maintain off-state high grid off voltage (ex:
4.6V), therefore the voltage VLX1 of common node LX1 continues to rise.At this point, above-mentioned voltage VLX1 is possible to than as to above-mentioned
The 4.6V of the grid voltage of the grid supply of PMOS120 adds the VTH.PMOS120's of the critical voltage as above-mentioned PMOS120
It is worth also big.At this point, PMOS120 is from triggering (self triggered), so that electric current can pass through the source electrode of PMOS120 and drain electrode
Between and flow, at this point, output voltage ELVDD is about 4.6V.
Fig. 4 is for illustrating between two operating modes provided by the booster converter of one embodiment of the invention mutually
The figure of the technology of conversion.
Switch technology between mode illustrated in fig. 4 can be attached with above-mentioned efficiency increasing shown in Fig. 2 by utilizing
The booster converter 210 on forceful electric power road 220 does not add the booster converter 210 of above-mentioned efficiency enhancing circuit to embody.
The booster converter 210 of one embodiment of the invention optionally with illustrated in fig. 3 from trigger switch mould
Formula and synchronous switch as described below (SS, Synchronous Switch) mode work.It is above-mentioned from trigger switch mode
For concept corresponding with above-mentioned synchronous switch mode, it is also known as asynchronous switch mode (Asynchronous Switch
Mode)。
At this point, above-mentioned refer to following mode from trigger switch mode, that is, to the grid of PMOS120 supply so that
The high grid off voltage (ex:4.6V) that PMOS120 is in an off state always, and NMOS110 is repeated periodically and is turned
Change on/off.
Moreover, above-mentioned synchronous switch mode refer to PMOS120 and NMOS110 be repeated cyclically complementaryly mutually connection/
The mode of disconnection.
The booster converter 210 of one embodiment of the invention is by detecting cell voltage (VBAT), in battery electricity
Press VBAT be greater than 4.4V in the case where with it is above-mentioned from trigger switch mode work, cell voltage VBAT and 4.4V identical or less than
With the work of above-mentioned synchronous switch mode in the case where 4.4V, so that operating mode changes according to cell voltage VBAT.Therefore,
The booster converter 210 of one embodiment of the invention can be connected with " mode control unit 230 ", and above-mentioned mode control unit 230 passes through
Cell voltage VBAT is detected, thus according to its result come so that above-mentioned booster converter 210 above-mentioned from trigger switch
It is converted between mode and above-mentioned synchronous switch mode.Above-mentioned mode control unit 230 is combined with above-mentioned booster converter 210
Device can be referred to " DC-DC boost converter 1 " of one embodiment of the invention.DC-DC boost converter 1 may include above-mentioned effect
Rate enhancing circuit 220 also may not include above-mentioned efficiency enhancing circuit 220.
When with the work of above-mentioned synchronous switch mode, with above-mentioned booster converter 210 feelings low in cell voltage VBAT
The high efficiency advantage of required output voltage VO UT is also supplied under condition.When with the above-mentioned work from trigger switch mode, even if having
In the case where cell voltage VBAT is excessively high but also the output voltage VO UT that the supply of above-mentioned booster converter 210 is pre-designed comes
So that the effect that the device for receiving above-mentioned output voltage VO UT reliably works.
Another embodiment according to the present invention, in order to above-mentioned booster converter 210 mode convert, can in order to it is above-mentioned from
It is converted between trigger switch mode and above-mentioned synchronous switch mode and assigns hysteresis phenomenon characteristic.That is, for example in battery electricity
VBAT is pressed to be greater than the moment of 4.45V, above-mentioned mode control unit 230 is so that PMOS120 maintains the mode of off-state to above-mentioned
The gate terminal of PMOS120 applies grid voltage (ex:4.6V), to be worked with above-mentioned from trigger switch mode.Later,
Such as it is lower than the moment of 4.35V in above-mentioned cell voltage VBAT, above-mentioned mode control unit 230 makes the grid for being applied to PMOS120
The voltage of pole forms the possessed value spike train form complementary with the spike train for the grid for being applied to NMOS110, thus, it can turn
It is changed to above-mentioned synchronous switch mode.As described above, can by from trigger switch mode entrance and disengaging assign hysteresis phenomenon,
To improve job stability when pattern conversion.
In Fig. 2 and booster converter shown in Fig. 3 210, above-mentioned efficiency enhancing circuit can be omitted.But in above-mentioned liter
In the case that buckling parallel operation 210 includes above-mentioned efficiency enhancing circuit 220, electric current will not flow to PMOS120 from the ontology of PMOS120
Parasitic diode, thus have the effect of from trigger switch mode efficiency enhancing.
Even if with the booster converter 210 to work from trigger switch mode such as one embodiment of the invention in cell voltage
The value of VBAT also executes normal work in the case where being greater than 4.4V.Therefore, it is supplied to active matrix organic light-emitting diode plate
In the case where the output voltage of the above-mentioned booster converter 210 to work from trigger switch mode, it can be ensured that above-mentioned active matrix
The display quality of organic light emitting diode plate.
Above-mentioned can be considered from trigger switch mode according to an embodiment of the invention rectifies as diode to be used as
(rectifier) asynchronous mode (asynchronous type) of element, but the thoroughly work of isolation body diode, utilize
Voltage in common node LX1 rises property to transmit electric current by the channel PMOS120.Therefore, with one embodiment of the invention
When being worked from trigger switch mode, with based on diode mode carry out work compared with, it is more efficient under STD mode.
Fig. 5, which is shown, carries out the output voltage based on the mode conversion in one embodiment of the invention illustrated in fig. 4
The result of simulation.Horizontal axis indicates the value of cell voltage VBAT, and vertical pivot indicates the value of output voltage VO UT.As shown in figure 5, simulation feelings
Condition is as follows, when cell voltage is relatively low with the work of synchronous switch mode, when cell voltage is relatively high with from trigger switch mould
Formula work.At this point, definitely being maintained relative to all cell voltage VBAT output voltage VO UT, to be appreciated that output electricity
The line regulation characteristic that pressure VOUT has had.Chart according to figure 5, according to synchronous switch mode and from trigger switch mode
The difference of the output voltage of conversion is within 2mV.It is smaller than under synchronous switch mode from the output voltage under trigger switch mode
Output voltage.
Fig. 6 is to show to the booster converter of one embodiment of the invention with from the effect in the case where the work of trigger switch mode
The chart for the result that rate is simulated.Horizontal axis indicates the electric current of the output terminal from the terminal as supply output voltage VO UT
(lout) size, vertical pivot indicate efficiency.Fig. 6 show it is when carrying out a variety of variations to input voltage VIN as a result, but can confirm,
Input voltage VIN is higher, the efficiency just slightly tendency of reduction.But, it is known that from the maximal efficiency under trigger switch mode extremely
Less 84% or more.
In the present specification, above-mentioned to be referred to alternatively as first mode from trigger switch mode, above-mentioned synchronous switch mode can quilt
It is referred to as second mode.
Fig. 7 and Fig. 8 shows the internal structure of the DC-DC converter of a previous embodiment.
Fig. 7 shows the brief configuration of DC-DC converter in block diagram form.
The DC-DC converter 100 being shown in FIG. 7 includes DC voltage conversion portion 30, pulse-width modulation waveform letter in inside
Number control unit 10 and feed circuit portion 20.
For example, DC voltage conversion portion 30 may include two transistors.The electric current inputted by DC voltage conversion portion 30
It is controllable to by the first transistor flowing in above-mentioned two transistor or by the second crystal in above-mentioned two transistor
Pipe flowing.Above-mentioned two transistor is controllable to the switching periodically switch repeatedly movement.Also, it can control above-mentioned
Two transistors are not in open state at the same time.Also, it is controllable to when above-mentioned the first transistor is in open state, above-mentioned
Two-transistor is in off status, on the contrary, above-mentioned second transistor is in and opens shape when above-mentioned the first transistor is in off status
State.Change the output voltage of DC-DC converter according to the duty ratio of the switching timer of each above-mentioned transistor.Its
In, " duty ratio " may be defined as the switching timer provided to the grid of above-mentioned the first transistor or above-mentioned second transistor
Open interval time span and close section time span between ratio.Alternatively, above-mentioned " duty ratio " may be defined as first
Transistor maintain open state when section and above-mentioned second transistor maintain open state when section time scale.
For example, above-mentioned the first transistor and above-mentioned second transistor may respectively be NMOS transistor and PMOS transistor.
The DC input voitage of DC-DC converter can be supplied to the input terminal (TI1=IN) in DC voltage conversion portion 30
VIN.DC voltage conversion portion may be defined as including the inductor 50 or the above-mentioned inductor 50 of exclusion for being provided in its input terminal.Direct current
The voltage value Vst or the current value directly proportional to above-mentioned voltage value Vst of first output end TO1 of voltage transformating part 30 can be inputted
In pulse-width modulation waveform signal control part 10, the voltage value of second output end (TO2=OUT) in DC voltage conversion portion 30
VOUTIt can be inputted to the input terminal TI2 in feed circuit portion.
Feed circuit portion 20 can be by the input voltage in reception DC voltage conversion portion 30, i.e., DC-DC converter 100 is defeated
Voltage out amplifies come the difference between the value and preset a reference value of the above-mentioned output voltage being entered to calibration,
Thus error voltage V is providedERR.In Fig. 7 and Fig. 8, above-mentioned error voltage VERRWith feedback voltage VCIt is identical.
Pulse-width modulation waveform signal control part 10 to using from the received value such as DC voltage conversion portion 30 by generating
Offset voltage and above-mentioned feedback voltage VCBe compared, can thus output pulse width modulation voltage, can be with above-mentioned pulsewidth modulation
Supplied based on voltage above-mentioned DC voltage conversion portion 30 above-mentioned two transistor (such as: NMOS transistor and PMOS are brilliant
Body pipe) grid voltage, to compensate the output voltage of DC-DC converter 100.
Fig. 8 shows the internal circuit for the DC-DC converter being shown in FIG. 7.
Fig. 9 graphically shows current value, the node of inductor 50 according to a previous embodiment according to the time
The voltage value of N2~N4 and pulse-width signal.
Hereinafter, being illustrated together with reference to Fig. 8 and Fig. 9.
The DC-DC converter 100 illustrated in fig. 8 includes DC voltage conversion portion 30, pulse-width modulation waveform inside it
Signal control part 10 and feed circuit portion 20.
DC voltage conversion portion 30 may include inductor 50, NMOS transistor 31 and PMOS transistor 32.Pulse width modulated wave
Shape signal control part 10 may include current detecting part 11, gradient compensation portion 12, comparing section 13, latch (latch) 14 and grid
Driving portion 15.Moreover, feed circuit portion 20 may include first resistor 23, second resistance 24, reference potential portion 22 and error amplification
Device 21.
DC voltage conversion portion
DC input voitage V can be supplied to the input terminal IN in DC voltage conversion portion 30IN.For example, above-mentioned direct current input
Voltage VINIt can be supplied from the rectifier (Rectifier) of lower one end of battery or the wireless charging power supply coil of wireless charging
It gives.One terminal of above-mentioned inductor 50 can be with the rectifier of lower one end of above-mentioned battery or above-mentioned wireless charging power supply coil
It is connected, the another terminal N1 of above-mentioned inductor 50 can be connected with LX terminal respectively.LX terminal can respectively with NMOS transistor
31 drain terminal and the drain terminal of PMOS transistor 32 are connected.The gate terminal and PMOS transistor of NMOS transistor 31
Gate terminal can be connected respectively with the first terminal in gate driving portion 15 and Second terminal.Moreover, NMOS transistor 31
Source terminal can be connected with a terminal of resistance 33, and the another terminal of resistance 33 can be connected with reference potential (GND).And
And the drain terminal of PMOS transistor 32 can be connected with output terminal OUT.
Being illustrated in Figure 8 two transistors included by DC voltage conversion portion 30 is respectively 31 He of NMOS transistor
The example of PMOS transistor 32, but not limited to this.
If supplying DC input voitage V to the input terminal IN in DC voltage conversion portionIN, then based on NMOS transistor and
The switching of PMOS transistor acts, the value of the electric current flowed by inductor 50 can as Fig. 9 the part (a) chart in
Shown in 311.NMOS transistor and PMOS transistor can alteration switch states alternate with each other.The source electrode and benchmark of NMOS transistor 31
It can be connected with resistance 33 between current potential.Above-mentioned switching movement can be provided based on individual gate driving portion 15.
PW waveform signal control unit
The current detecting part 11 of pulse-width modulation waveform signal control part 10 can be to the electric current flowed in above-mentioned resistance 33
Value, which is detected, carrys out output voltage.At this point, the voltage V in node N2N2It can be identical as 312 in the chart of the part (b) of Fig. 9.This
When, the reasons why voltage of interior joint N2 is reduced to 0 in the section TI~T3 the starting point for NMOS transistor in each section T1, T2, T3
It closes, PMOS transistor work, to flow to the current direction PMOS transistor of inductor 50.That is, in each section T1, T2, T3
In, electric current is not flowed to NMOS transistor, therefore voltage is reduced to 0.
The electric current I that the detection of current detecting part 11 is flowed by inductor 50APeak value.The detection time point of above-mentioned peak value can
It is provided to gradient compensation portion 12.For example, it can be t1, t2, t3, above-mentioned t1, t2 and t3 that inductor 50, which has the time point of peak value,
Value can be provided to gradient compensation portion 12.
It can be to the voltage V in 12 input node N2 of the gradient compensation portion of pulse-width modulation waveform signal control part 10N2And have
The sawtooth voltage V in predetermined periodN3.Above-mentioned sawtooth voltage can as Fig. 9 chart in 313.
The voltage V of the exportable above-mentioned node N2 in gradient compensation portion 12N2With above-mentioned sawtooth voltage VN3Conjunction offset voltage
VN4.But gradient compensation portion 12 can be in time point t1, t2, the t3 to above-mentioned sawtooth voltage V being detected from above-mentioned peak valueN3It drops to
Force control at above-mentioned offset voltage V in section between time point t11, t12, t13 of minimumN4With reference potential to identical
Constant value.That is, above-mentioned offset voltage VN4It can be identical as 314 in the chart of the part (d) of Fig. 9.Using gradient compensation portion
12 prevent the vibration of output voltage.
The comparing section 13 of pulse-width modulation waveform signal control part 10 can be in above-mentioned offset voltage VN4Greater than above-mentioned feed circuit
Feedback voltage V provided by portion 20CIn the case where export logical value " 1 ", otherwise export logical value " 0 ", or in above-mentioned compensation electricity
Press VN4Greater than feedback voltage V provided by above-mentioned feed circuit portion 20CIn the case where export logical value " 0 ", otherwise export logic
It is worth " 1 ".
The latch portion 14 of pulse-width modulation waveform signal control part 10 can receive in timer-signals and above-mentioned comparing section 13
The value of middle output, the pwm voltage V supplied so as to final output to gate driving portion 15PWM.Above-mentioned timer-signals
Period has preset value, and the period of the period of above-mentioned sawtooth voltage and above-mentioned inductor current can be with above-mentioned timer
The period of signal is identical.
The gate driving portion 15 of pulse-width modulation waveform signal control part 10 can receive above-mentioned pwm voltage VPWM, herein
On the basis of supply the grid voltage of above-mentioned NMOS transistor 31 and above-mentioned PMOS transistor 32.
Feed circuit portion
The first resistor 23 and second resistance 24 in feed circuit portion 20 can form divider (voltage divider).
The one end of first resistor (R1) 23 can be connected with the DC output terminal OUT in DC voltage conversion portion 30, the
The other end of one resistance (R1) 23 can be connected with second resistance (R2) 24.It the other end of second resistance (R2) 24 can be with base
Quasi- current potential is connected.
As the voltage in node (Nsense) defined between first resistor (R1) 23 and second resistance (R2) 24
Detection voltage VSENSEWith reference potential V provided by reference potential portion 22REFBetween difference can be put by error amplifier 21
Greatly.
At this point, for example, detection voltage VSENSEIt can be to be demarcated using above-mentioned divider from above-mentioned DC output voltage
Value.Moreover, for example, said reference current potential VREFIt may be set to that there is preset preferred value in above-mentioned DC output voltage
In the case where the identical value of generated above-mentioned detection voltage.For example, above-mentioned preferred preset value is 4.6V, at this point,
If said reference current potential may be set to 2.3V so that the mode that above-mentioned detection voltage reaches 2.3V constitutes circuit.
At this point, the voltage for being amplified and being exported by error amplifier 21 is error voltage VERR, in the example of Fig. 8, above-mentioned error
Voltage VERRIt being capable of feedback voltage V to be inputted to pulse-width modulation waveform signal control part 10CMode supply.
Figure 10 shows the structure chart of the DC-DC converter 200 of one embodiment of the invention, and Figure 11 shows one embodiment of the invention
DC-DC converter circuit diagram.
The basic structure of the DC-DC converter of Figure 10 includes DC voltage conversion portion 30, the control of pulse-width modulation waveform signal
Portion 10 and feed circuit portion 20, can be identical as the structure of Fig. 8.
At this point, the difference of Figure 10 and Fig. 7 is output terminal and the control of pulse-width modulation waveform signal in feed circuit portion 20
Feedback voltage generating unit 60 is added between the input terminal in portion 10 processed.Therefore, in fig. 8, if feedback voltage VCWith error voltage
VERRValue it is identical, then lead to the feedback voltage V in Fig. 3 because of above-mentioned feedback voltage generating unit 60CWith error voltage VERRHave
Mutually different value.
That is, the input voltage V of 30 input of the opposite DC voltage conversion of feedback voltage generating unit 60 portionINIt is detected, is utilized
Above-mentioned input voltage detected and above-mentioned error voltage VERRTo generate feedback voltage VC.Above-mentioned feedback voltage VCCan by from
Error voltage VERRDirectly proportional value a × VERRThe DC input voitage V for subtracting and being inputted to above-mentioned DC voltage conversion portion 30BAT
=ViINDirectly proportional value b × VIN=b × VBATAnd it generates, above-mentioned error voltage VERRBy to above-mentioned DC voltage conversion portion
The DC output voltage V of 30 outputsOUTThe value V demarcatedSENSEWith scheduled reference voltage VREFBetween difference amplify and
?.
According to an embodiment of the invention, the error voltage V that necessary feedback voltage in order to obtain can be reduced and usedERR's
Variation.That is, error voltage VERRVariation small mean output voltage VOUTIt is small with the difference of the preferred value originally set.Therefore ignore
Above-mentioned input voltage VINVariation, also can be obtained closer to preset output voltage defined output voltage VOUT。
Figure 12 shows the internal circuit of the feedback voltage generating unit 60 of one embodiment of the invention.
Feedback voltage generating unit 60 may include the first current mirror 61, the second current mirror 62 and third current mirror 63.
If error voltage VERRBe input into feedback voltage generating unit 60, then the first current mirror 61 can to above-mentioned error voltage
VERRDirectly proportional error current (IERR) 611 reflected to generate the error current (I of duplicationERR)612。
First current mirror 61 may include two PMOS transistors.The source terminal and the tenth of 11st PMOS transistor PM1
The source terminal of two PMOS transistor PM2 can be connected with service voltage VDD respectively.The grid of 11st PMOS transistor PM1
Terminal can be connected with the gate terminal of the 12nd PMOS transistor PM2, and the gate terminal of the 11st PMOS transistor PM1
It can also be connected with the drain terminal of the 11st PMOS transistor PM1.
The drain terminal of 11st PMOS transistor PM1 can be connected with the drain terminal of NMOS transistor NM0, above-mentioned mistake
Potential difference VERRThe gate terminal of NMOS transistor NM0 can be input into.The source terminal of NMOS transistor NM0 can be with the one of resistance
End is connected, and the other end of above-mentioned resistance can be connected with reference potential GND.
If to the gate terminal input voltage V of the 13rd NMOS transistor NM3BAT=VIN, then can pass through the 13rd NMOS crystalline substance
The drain terminal of body pipe NM3 makes input current IBATFlowing.At this point, the source terminal and resistance of the 13rd NMOS transistor NM3
One end is connected, and the other end of above-mentioned resistance is connected with reference potential GND.Above-mentioned input voltage VBATIt can exist in the same manner
Third current mirror 63 flows.
Third current mirror 63 can to DC input voitage VBATDirectly proportional input current (IBAT) 631 carry out reflection next life
At the input current (I of duplicationBAT)632。
Third current mirror 63 may include two PMOS transistors.The source terminal and the tenth of 13rd PMOS transistor PM3
The source terminal of four PMOS transistor PM4 can be connected with service voltage VDD respectively.The grid of 13rd PMOS transistor PM3
Terminal can be connected with the gate terminal of the 14th PMOS transistor PM4, and the gate terminal of the 13rd PMOS transistor PM3
It can also be connected with the drain terminal of the 14th PMOS transistor PM4.
Above-mentioned input current (the I of duplicationBAT) 632 it can flow to the second current mirror 62.Above-mentioned second current mirror 62 can be to duplication
Above-mentioned input current (IBAT) 632,621 reflected to generate the second input current (I of duplicationBAT)622。
Second current mirror 62 may include two NMOS transistors.The source terminal and the tenth of 11st NMOS transistor NM1
The source terminal of bi-NMOS transistor NM2 is connected with reference potential GND respectively.The gate terminal of 11st NMOS transistor NM1
Son can be connected with the gate terminal of the tenth bi-NMOS transistor NM2, also, can also be with the leakage of the tenth bi-NMOS transistor NM2
Extreme son is connected.
Finally, the exportable above-mentioned error current (I from duplication of feedback voltage generating unit 60ERR) 612 subtract above-mentioned duplication
Second input current (IBAT) 622 feedback current Ic, above-mentioned feedback voltage V can be generated from above-mentioned feedback current IcC。
That is, feedback voltage VCCan with from error voltage VERRDirectly proportional value a × VERRIt subtracts and input voltage VBATCheng Zheng
Value b × V of ratioBATDirectly proportional (the V of valueC∝(a×VERR- b × VBAT))。
Figure 13 is the figure for illustrating the difference of the feedback voltage of the size based on input current of one embodiment of the invention.
Partially the change pattern of the inductor current when applying different size of input voltage is carried out at (a) of Figure 13
Compare.Figure 13 (b) partially to the feedback voltage V when applying above-mentioned different size of input voltage based on the timeCWith mistake
Potential difference VERRThe size of signal be compared.It is then shown according to the time based on each above-mentioned feedback electricity in part (c) of Figure 13
Press VCPulsewidth modulation voltage VPWMSignal.
In (a) of Figure 13, for example, if the variation of the inductor current when input voltage of first level is entered is presented
Chart shown in appended drawing reference 211 out, then when the horizontal second horizontal input voltage higher than above-mentioned first level is entered
The variation of inductor current is equivalent to chart shown in appended drawing reference 212.
At this point, the error electricity exported in the case where the input voltage of above-mentioned first level is applied from feed circuit portion 20
Press (VERR) 215 size can be greater than in the feelings that is higher than the above-mentioned second high horizontal input voltage of above-mentioned first level and be applied
Error voltage (the V exported under condition from feed circuit portion 20ERR)216。
Such as conventional art, the present invention maintains feedback voltage V as former stateCValue (that is, adjusting arteries and veins in mode as in the past
The duty ratio of width modulation), but additional detection can be carried out by the variation to input voltage, carry out enhancement line regulation.With reference to this
Any continues to illustrate.
It is illustrated together referring to the comparison techniques and Figure 11 being illustrated in Figure 8, then when the first input voltage is entered
When error voltage (the V that generatesERR) 215 size can be with the error voltage (V that generates when the second input voltage is enteredERR)
216 is different.If inputting above-mentioned error voltage (V to feedback voltage generating unit 60ERR) 215, then exportable feedback voltage (VC)213。
If also, inputting above-mentioned error voltage (V to feedback voltage generating unit 60ERR) 216, then exportable feedback voltage (VC)214.If
With Fig. 9 shown in compared with the prior art, then according to the prior art, error voltage is voltage identical with feedback voltage, because
The change of the changing value of this error voltage based on different input voltages and the feedback voltage based on different above-mentioned input voltages
Change value is identical.In contrast to this, as shown in figure 13, an embodiment according to the present invention, it is known that the mistake based on different input voltages
The changing value (for example, difference of error voltage 215 and error voltage 216) of potential difference is less than based on different above-mentioned another inputs
The changing value (for example, difference of feedback voltage 213 and feedback voltage 214) of voltage is small.
According to the present invention, feedback voltage (V is being requiredC) and the feedback voltage (V obtained in above-mentioned comparison techniquesC) identical
In the case where, in the present invention, in order to generate feedback voltage (VC) and utilize error voltage (VERR) come to input voltage (VIN)
Variation compensates, and therefore, is forming feedback voltage (V same as the prior artC) while reduce error voltage (VERR)
Difference (error voltage (V when input voltage is differentERR) difference).That is, error voltage (VERR) difference reduce meaning
Line regulation enhancing.
That is, if making feedback voltage (V in the pastC) and error voltage (VERR) form identical value and then in the present invention make
Obtain feedback voltage (VC) and error voltage (VERR) mutually different value is formed (for example, VC=k1 × VERR+k2×VIN).Wherein,
K1 and k2 can be real number.
Above-mentioned error voltage VERRFor reflect output voltage DC Variable (Variation) value.Therefore, in order to subtract
The DC Variable of few output voltage needs to find and reduces error voltage VERRVariation method.In the prior art, benefit is needed
With error voltage VERRIt adjusts duty ratio, but in the present invention, is compensated using the variation by detection input voltage
Thus structure can reduce error voltage V under the same conditionsERRVariation.
Using embodiment present invention as described above, person skilled in the art of the present invention can not depart from the present invention
Intrinsic propesties in the range of easily implement numerous variations and modification.Invent the interior of each claim in claimed range
Hold can other claims in the range of can be understood by this specification with not adduction relationship combine.
Claims (11)
1. a kind of DC-DC converter, wherein include:
The DC voltage conversion portion (30) of switching type；
Pulse-width modulation waveform signal control part is carried out as the movement generated to the switch for being contained in above-mentioned DC voltage conversion portion
The pulse-width modulation waveform signal control part (10) of the pulse-width modulation waveform signal of control, the duty of above-mentioned pulse-width modulation waveform signal
Than according to the feedback voltage (V inputted to pulse-width modulation waveform signal control partC) determine；And
The feed circuit portion (20) of error voltage is generated,
Above-mentioned feedback voltage (VC) by from above-mentioned error voltage (VERR) directly proportional value (a × VERR) subtract with to above-mentioned straight
Flow the DC input voitage (V of voltage transformating part inputBAT) directly proportional value (b × VBAT) and generate, above-mentioned error voltage (VERR)
With the DC output voltage (V exported with above-mentioned DC voltage conversion portionOUT) relevant value (VSENSE) and scheduled reference voltage
(VREF) between difference it is directly proportional.
2. DC-DC converter according to claim 1, wherein further include the feedback voltage life for generating above-mentioned feedback voltage
At portion (60),
Above-mentioned feedback voltage generating unit (60) includes the first current mirror (61), the second current mirror (62) and third current mirror (63),
First current mirror (61) is generated by the error current (I directly proportional to above-mentioned error voltageERR) (611) reflected
Come the error current (I being replicatedERR) (612),
Third current mirror (63) generate by with above-mentioned DC input voitage (VBAT) directly proportional input current (IBAT)(631)
Input current (the I for being reflected to be replicatedBAT) (632),
Above-mentioned second current mirror (62) generates by the above-mentioned input current (I being replicatedBAT) (632,621) reflected come
The second input current (I being replicatedBAT) (622),
It exports from the above-mentioned error current (I being replicatedERR) (612) subtract the above-mentioned second input current (I being replicatedBAT)
(622) feedback current (IC),
From above-mentioned feedback current (IC) generate above-mentioned feedback voltage (VC)。
3. DC-DC converter according to claim 1, wherein above-mentioned feedback voltage (VC) and above-mentioned DC input voitage
(VBAT) be inversely proportional.
4. DC-DC converter according to claim 1, wherein the size of above-mentioned feedback voltage and above-mentioned pulse width modulated wave
The dutyfactor value of shape signal is directly proportional.
5. DC-DC converter according to claim 2, wherein above-mentioned first current mirror (61) includes the 11st PMOS brilliant
Body pipe and the 12nd PMOS transistor,
The source terminal of above-mentioned 11st PMOS transistor and the source terminal and feeding terminal of above-mentioned 12nd PMOS transistor
It is connected,
The gate terminal of above-mentioned 11st PMOS transistor respectively with the gate terminal of above-mentioned 12nd PMOS transistor and above-mentioned
The drain terminal of 11st PMOS transistor is connected,
Above-mentioned second current mirror (62) includes the 13rd PMOS transistor and the 14th PMOS transistor,
The source terminal of above-mentioned 13rd PMOS transistor and the source terminal of above-mentioned 14th PMOS transistor and above-mentioned supply
Terminal is connected,
The gate terminal of above-mentioned 13rd PMOS transistor respectively with the gate terminal of above-mentioned 14th PMOS transistor and above-mentioned
The drain terminal of 14th PMOS transistor is connected,
Above-mentioned third current mirror (63) includes the 11st NMOS transistor and the tenth bi-NMOS transistor,
The source terminal of above-mentioned 11st NMOS transistor and the source terminal and the first benchmark of above-mentioned tenth bi-NMOS transistor
Current potential is connected,
The gate terminal of above-mentioned 11st NMOS transistor respectively with the gate terminal of above-mentioned tenth bi-NMOS transistor and above-mentioned
The drain terminal of tenth bi-NMOS transistor is connected,
The drain terminal of above-mentioned 11st NMOS transistor is connected with the drain terminal of above-mentioned 12nd PMOS transistor, above-mentioned
The drain terminal of tenth bi-NMOS transistor is connected with the drain terminal of above-mentioned 13rd PMOS transistor.
6. DC-DC converter according to claim 1, wherein above-mentioned DC voltage conversion portion (30) includes inductor
(50), the first NMOS transistor (31) and the first PMOS transistor (32),
One terminal of above-mentioned inductor (50) is connected with the input terminal of above-mentioned DC-DC converter, above-mentioned inductor it is another
Terminal is connected with the drain terminal of the drain terminal of above-mentioned first NMOS transistor (31) and above-mentioned first PMOS transistor (32)
It connects, the source terminal of above-mentioned first PMOS transistor (32) is connected with the output terminal of above-mentioned DC-DC converter.
7. DC-DC converter according to claim 6, wherein above-mentioned pulse-width modulation waveform signal control part (10) includes
Gate driving portion (15),
Above-mentioned first NMOS transistor (31) and the first PMOS are controlled using the pwm voltage value in above-mentioned gate driving portion
Transistor (32).
8. DC-DC converter according to claim 7, wherein above-mentioned pulse-width modulation waveform signal control part further includes electricity
It flows test section (11) and gradient compensation portion (12),
Above-mentioned current detecting part detects the electric current of the source terminal of above-mentioned first NMOS transistor (31), by being examined
The peak value for the above-mentioned electric current surveyed is detected and is exported,
Sawtooth wave of the above-mentioned gradient compensation portion by receiving the output valve of above-mentioned current detecting part and with the predetermined period
Voltage exports offset voltage.
9. DC-DC converter according to claim 8, wherein above-mentioned pulse-width modulation waveform signal control part further includes ratio
Compared with portion (13), latch portion (14) and gate driving portion (15),
Above-mentioned comparing section exports logical value by receiving above-mentioned offset voltage and above-mentioned feedback voltage,
Above-mentioned latch portion exports above-mentioned pulsewidth tune by receiving above-mentioned logical value and the above-mentioned gate driving portion of clock direction of signal
Voltage value processed.
10. DC-DC converter according to claim 1, wherein above-mentioned feed circuit portion includes first resistor, the second electricity
Resistance and error amplifier,
One terminal of above-mentioned first resistor is connected with the output terminal of above-mentioned DC-DC converter, above-mentioned first resistor it is another
Terminal and a terminal of second resistance are connected with the inversing input terminal of above-mentioned error amplifier jointly,
The another terminal of above-mentioned second resistance is connected with the first reference potential,
The non-inverting input terminal of above-mentioned error amplifier is connected with the second reference potential.
11. a kind of DC-DC converter, wherein include:
The DC voltage conversion portion (30) of switching type；
Pulse-width modulation waveform signal control part is carried out as the movement generated to the switch for being contained in above-mentioned DC voltage conversion portion
The pulse-width modulation waveform signal control part (10) of the pulse-width modulation waveform signal of control, the duty of above-mentioned pulse-width modulation waveform signal
Than according to the feedback voltage (V inputted to pulse-width modulation waveform signal control partC) determine；And
The feed circuit portion (20) of error voltage is generated,
Above-mentioned error voltage and the DC output voltage (V exported with above-mentioned DC voltage conversion portionOUT) directly proportional value (VSENSE)
With scheduled reference voltage (VREF) between difference it is directly proportional,
Above-mentioned feedback voltage (VC) by from above-mentioned error voltage (VERR) directly proportional value (a × VERR) subtract with to above-mentioned straight
Flow the DC input voitage (V of voltage transformating part inputBAT) directly proportional value (b × VBAT) and generate.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020160158626A KR101855339B1 (en) | 2016-11-25 | 2016-11-25 | DC-DC converter having a device to cope with change of input voltage |
| KR10-2016-0158626 | 2016-11-25 | ||
| KR1020160158627A KR101879653B1 (en) | 2016-11-25 | 2016-11-25 | DC-DC converter having stable output characteristic over wide range of input voltage |
| KR10-2016-0158627 | 2016-11-25 | ||
| CN201680042032.5A CN108475984B (en) | 2016-11-25 | 2016-12-13 | DC-DC converter |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680042032.5A Division CN108475984B (en) | 2016-11-25 | 2016-12-13 | DC-DC converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109378969A true CN109378969A (en) | 2019-02-22 |
Family
ID=62023744
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680042032.5A Active CN108475984B (en) | 2016-11-25 | 2016-12-13 | DC-DC converter |
| CN201810281754.7A Pending CN109378969A (en) | 2016-11-25 | 2016-12-13 | The DC-DC converter of the device of variation with reply input voltage |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680042032.5A Active CN108475984B (en) | 2016-11-25 | 2016-12-13 | DC-DC converter |
Country Status (2)
| Country | Link |
|---|---|
| CN (2) | CN108475984B (en) |
| WO (1) | WO2018079929A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110417262A (en) * | 2019-06-28 | 2019-11-05 | 上海芯导电子科技有限公司 | A kind of loop compensation circuit |
| WO2021115146A1 (en) * | 2019-12-13 | 2021-06-17 | 北京集创北方科技股份有限公司 | Voltage regulation apparatus, chip and electronic device |
| CN114424071A (en) * | 2019-07-26 | 2022-04-29 | 艾尔多股份有限公司 | Electronic monitoring circuit for detecting changes in power or current absorbed by at least one electronic circuit to be tested and electronic system for testing the operation of at least one electronic circuit |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113126691B (en) * | 2019-12-31 | 2022-12-02 | 苏州福瑞思信息科技有限公司 | Current source circuit and control system |
| CN111711361B (en) * | 2020-06-09 | 2023-03-31 | 成都芯源***有限公司 | Ultra-low input voltage boost converter and control circuit and method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006149128A (en) * | 2004-11-22 | 2006-06-08 | Funai Electric Co Ltd | Switching regulator |
| JP2009303313A (en) * | 2008-06-11 | 2009-12-24 | Seiko Npc Corp | Inversion-type dc/dc converter |
| CN102761258A (en) * | 2012-07-25 | 2012-10-31 | 圣邦微电子（北京）股份有限公司 | Boosted circuit and control method thereof |
| JP2014212626A (en) * | 2013-04-18 | 2014-11-13 | 旭化成エレクトロニクス株式会社 | Switching power-supply circuit |
| CN105245100A (en) * | 2015-10-28 | 2016-01-13 | 成都芯源***有限公司 | Boost circuit and control method thereof |
| CN105337500A (en) * | 2014-06-27 | 2016-02-17 | 意法半导体研发(深圳)有限公司 | Power converter and method for adjusting linear transient response of power converter |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006050833A (en) * | 2004-08-06 | 2006-02-16 | Matsushita Electric Ind Co Ltd | Charge pump circuit |
| JP2009253990A (en) * | 2008-04-01 | 2009-10-29 | Seiko Epson Corp | Switching supply circuit |
| JP2010081748A (en) * | 2008-09-26 | 2010-04-08 | Fujitsu Microelectronics Ltd | Circuit and method for controlling step-up dc-dc converter and step-up dc-dc converter |
| US8441231B2 (en) * | 2011-05-27 | 2013-05-14 | Eta Semiconductor Inc. | Bidirectional hysteretic power converter |
| JP2013141409A (en) * | 2013-04-23 | 2013-07-18 | Fuji Electric Co Ltd | Switching element drive circuit for electric power conversion system |
| JP6531767B2 (en) * | 2015-02-13 | 2019-06-19 | 三菱電機株式会社 | Power converter |
-
2016
- 2016-12-13 CN CN201680042032.5A patent/CN108475984B/en active Active
- 2016-12-13 CN CN201810281754.7A patent/CN109378969A/en active Pending
- 2016-12-13 WO PCT/KR2016/014570 patent/WO2018079929A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006149128A (en) * | 2004-11-22 | 2006-06-08 | Funai Electric Co Ltd | Switching regulator |
| JP2009303313A (en) * | 2008-06-11 | 2009-12-24 | Seiko Npc Corp | Inversion-type dc/dc converter |
| CN102761258A (en) * | 2012-07-25 | 2012-10-31 | 圣邦微电子（北京）股份有限公司 | Boosted circuit and control method thereof |
| JP2014212626A (en) * | 2013-04-18 | 2014-11-13 | 旭化成エレクトロニクス株式会社 | Switching power-supply circuit |
| CN105337500A (en) * | 2014-06-27 | 2016-02-17 | 意法半导体研发(深圳)有限公司 | Power converter and method for adjusting linear transient response of power converter |
| CN105245100A (en) * | 2015-10-28 | 2016-01-13 | 成都芯源***有限公司 | Boost circuit and control method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110417262A (en) * | 2019-06-28 | 2019-11-05 | 上海芯导电子科技有限公司 | A kind of loop compensation circuit |
| CN114424071A (en) * | 2019-07-26 | 2022-04-29 | 艾尔多股份有限公司 | Electronic monitoring circuit for detecting changes in power or current absorbed by at least one electronic circuit to be tested and electronic system for testing the operation of at least one electronic circuit |
| WO2021115146A1 (en) * | 2019-12-13 | 2021-06-17 | 北京集创北方科技股份有限公司 | Voltage regulation apparatus, chip and electronic device |
| US12009748B2 (en) | 2019-12-13 | 2024-06-11 | Chipone Technology (Beijing) Co., Ltd. | Voltage regulation apparatus, chip and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108475984B (en) | 2021-05-07 |
| CN108475984A (en) | 2018-08-31 |
| WO2018079929A1 (en) | 2018-05-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109378969A (en) | The DC-DC converter of the device of variation with reply input voltage | |
| CN100414825C (en) | Switching power supply circuit and electronic apparatus provided therewith | |
| CN101645652B (en) | Dc-dc converter and organic light emitting display device using the same | |
| US8508963B2 (en) | Step-down switching regulator capable of providing high-speed response with compact structure | |
| CN102651608A (en) | Control circuit, electronic device, and method for controlling power supply | |
| US9514671B2 (en) | Power supply unit and organic light emitting display including the same | |
| US9136836B2 (en) | Converter including a bootstrap circuit and method | |
| CN203416160U (en) | Synchronous rectification controller and power converter using the synchronous rectification controller | |
| US9997123B2 (en) | Switching power supply circuit, liquid crystal driving device, and liquid crystal display device | |
| CN101752893A (en) | Cable voltage drop compensation for battery chargers | |
| CN102545603A (en) | Switching power-supply unit | |
| CN109906547A (en) | Power converter with the control of predictive pulse width modulation device | |
| US20130063110A1 (en) | Fast startup algorithm for low noise power management | |
| US20090179584A1 (en) | Dc/dc converter | |
| US8384356B2 (en) | Self contained power source | |
| TWI408542B (en) | Apparatus for supplying power source | |
| US9876439B2 (en) | Ultra high voltage regulator | |
| US11594959B1 (en) | Switched capacitor circuit with passive charge recycling | |
| US9265121B2 (en) | OLED power driver circuit | |
| US9966843B2 (en) | Supply voltage generating method | |
| US20130162234A1 (en) | Buck regulation of a boost regulator | |
| JP2006129630A (en) | Power supply device and portable device | |
| US10890626B2 (en) | Power management integrated circuit | |
| CN108258745B (en) | Chip with high-current switch type charging and power management functions and application | |
| TWI532027B (en) | A power driver for oled panels and its method of driving a load |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190222 |
|
| RJ01 | Rejection of invention patent application after publication |