CN109285505A - A kind of shift register cell, gate driving circuit and display device - Google Patents

A kind of shift register cell, gate driving circuit and display device Download PDF

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Publication number
CN109285505A
CN109285505A CN201811301619.0A CN201811301619A CN109285505A CN 109285505 A CN109285505 A CN 109285505A CN 201811301619 A CN201811301619 A CN 201811301619A CN 109285505 A CN109285505 A CN 109285505A
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China
Prior art keywords
transistor
connect
signal
input terminal
shift register
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CN201811301619.0A
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Chinese (zh)
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CN109285505B (en
Inventor
张盛东
雷腾腾
廖聪维
黄杰
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

This application discloses a kind of shift register cell circuit, gate driving circuit and display devices, it proposes and is designed with the dynamic inverter of cross-linked positive feedback reinforced pipe and bootstrap capacitor, it being capable of leakage current preferably on suppressor grid driving circuit key node.Compared to traditional gate driving circuit, DC channel is not present in the gate driving circuit of the application, and circuit power consumption is lower；The thin film transistor (TFT) threshold voltage ranges allowed are bigger, are more suitable for the needs integrated on large scale flat-panel monitor.

Description

A kind of shift register cell, gate driving circuit and display device
Technical field
The present invention relates to field of display technology, and in particular to a kind of shift register cell, gate driving circuit and display Device.
Background technique
In recent years, it is rapidly developed using liquid crystal display and organic light emitting display as the flat panel display of representative.FPD Technology just develops towards in large size, high-resolution direction.In the development process of large scale flat-panel monitor, it is faced with perhaps More challenges.First, due to the dispersibility of thin film transistor (TFT) (Thin Film Transistor, TFT) electric property, scan line and The multi-party factors such as resistance-capacitance (RC) the delay limitation of (Delay), the distribution of voltage and current network be unbalanced on data line, The show uniformity of large size panel is difficult to ensure.Second, the gate driving circuit response speed of large size panel is difficult to meet It is required that.This is because the increase of panel size and resolution ratio become larger, the sweep time of corresponding controlling grid scan line and data line is wanted Microsecond grade to be reduced to is sought, and load capacitance and the amount of resistance sharp increase on panel, this just gives to panel peripheral driver Circuit proposes more harsh driving requirement.Third, the gate driving circuit robustness on large scale display panel is bad, work It is relatively short to make the service life.Due to the difference between different technology conditions and different production batch, the threshold value electricity of thin film transistor (TFT) Pressing element has biggish dispersibility, can be distributed to from depletion type it is enhanced, this requires on large size panel gate driving electricity Road can tolerate biggish process deviation, there is higher robustness；In addition when the threshold voltage of thin film transistor (TFT) also can be with work Between drift about, weaken the performance of gate driving circuit, influence working life.Therefore, it is necessary to design one kind to can satisfy plate Display device can also improve the driving circuit of display resolution while increasing panel size.
For small-medium size display panel, the load capacity of integrated gate drive circuitry is smaller, to the device performance of TFT It is required that lower.Although lower (the generally less than 1cm of the mobility of non-crystalline silicon tft2(V.s)-1), reliability it is poor, but amorphous silicon TFT has met the requirement of the integrated gate drive circuitry of general small-medium size enough.But non-crystalline silicon tft and traditional TFT integrated circuit structure is difficult to meet requirement of the large scale display device to driving circuit.Based on metal-oxide film crystal The line-scan circuit of pipe is considered as the technology being most hopeful applied to large scale display panel, because metal-oxide film is brilliant Body pipe transfer rate is high, up to 10~50cm2(V.s)-1, leakage current is small, preparation process temperature is low, device stability is good and big It is good etc. that area prepares uniformity.Currently, mainly being deposited using the integrated gate drive circuitry that metal oxide thin-film transistor designs In two problems.First is metal oxide thin-film transistor usually from depletion device, i.e. threshold voltage is negative, which results in Low level in circuit maintains the key node of part to be easy to happen electric leakage, leads to circuit malfunction.Second is that metal oxide is thin The threshold voltage of film transistor can drift about with the working time, for being maintained pipe by the low level of positively biased compression for a long time It says, the possible positive excursion of threshold voltage, and the lower trombone slide by the driving tube of negative bias compression and phase inverter for a long time, threshold value Voltage may bear drift.The low level of threshold voltage polarization maintains pipe that will be hardly turned on, under serious situation, gate driving circuit meeting It loses low level and maintains function, output waveform is caused to maintain part to seal in clock pulse signal in low level.The drop-down of phase inverter Pipe threshold voltage is partially negative, and the output of phase inverter can be made to leak electricity, cause phase inverter that can not export high level.In order to make circuit in device It remains to work normally when the threshold voltage of part drifts about, under normal circumstances, be designed by multiple low levels or STT (Series-Connected Two-Transistor) structure come inhibit input pipe, lower trombone slide, low level maintain pipe bootstrapping rank The electric leakage of section.Since low level maintains the grid of pipe to be coupled to the output end of phase inverter, so the output of phase inverter is to circuit It works normally also most crucial.If low potential is arrived in the not high enough even electric leakage of the output current potential of phase inverter, circuit will be lost It goes low level to maintain function, leads to the failure of circuit.Therefore, in the low level maintenance stage, the threshold voltage of device drifts about, The output of phase inverter remains to be stably maintained at the service life that relatively high level is conducive to extend integrated gate drive circuitry.
Summary of the invention
The application a kind of shift register cell is provided and the gate driving circuit that is made of the shift register cell and Display device can enhance the robustness and working life of circuit while meeting the driving of large scale high-resolution display panel.
According in a first aspect, provide a kind of shift register cell in a kind of embodiment, including input module (21), reverse phase Device module (22), pull-down module (23), output module (24) and low level maintenance module (25)；
Further include:
First signal input part, for receiving the first clock signal (CLK)；
Second signal input terminal, for receiving the second pulse signal (RST)；
Third signal input part, for receiving line scan signals (OUTn-1)；
Fourth signal input terminal, for receiving cascade Mach-Zehnder interferometer signal (COUTn-1)；
First signal output end, for exporting line scan signals (OUTn)；
Second signal output end controls signal (COUT for output cascaden)；
First current potential input terminal is used for the input of the first low potential (VSSL)；
Second current potential input terminal is used for the input of the second low potential (VSS)；
Third current potential input terminal is used for the input of the first high potential (VGH)；
First internal node (Q) is the input module (21) and the pull-down module (23), the output module (24) Between connecting node；
Second internal node (QB) is the connection section between the inverter modules (22) and the pull-down module (23) Point；
The input module (21) is connected to third signal input part, fourth signal input terminal and the first internal node (Q) Between, for being pre-charged to first internal node (Q)；
The inverter modules (22) be connected to second signal input terminal, fourth signal input terminal, the first current potential input terminal, Between third current potential input terminal and second signal output end, for being generated in described first in second internal node (QB) The electric signal of portion's node (Q) reverse phase；
The pull-down module (23) is connected to the first internal node (Q), the second internal node (QB), the first current potential input terminal Between second signal output end, for the current potential of first internal node (Q) to be down to the first current potential (VSSL)；
The output module (24) be connected to the first signal input part, the first internal node (Q), the first signal output end and Between second signal output end, signal (COUT is controlled for output cascaden) and output line scan signals (OUTn)；
The low level maintenance module (25) is connected to the second internal node (QB), the second current potential input terminal, the first signal Between output end and second signal output end, for the current potential of the first signal output end and second signal output end to be down to respectively Second current potential (VSS) and the first current potential (VSSL).
According to second aspect, a kind of gate driving circuit, including the first clock line (CK1), are provided in a kind of embodiment Two clock lines (CK2), third clock line (CK3), the 4th clock line (CK4), the first enabling signal line (STV1), the first starting letter Number line (STV2) and the first low potential line (VSSL), the second low potential line (VSS), third equipotential line (VGH), line scan signals line (OUTn), cascade Mach-Zehnder interferometer signal wire (COUTn)；
The gate driving circuit further includes N+1 grades of cascade shift register cells as claimed in claim 8, wherein N is positive integer；
The first current potential input terminal, the second current potential input terminal and the third current potential input terminal of every level-one shift register cell point It is not connect with the first low potential line (VSSL), the second low potential line (VSS) and third equipotential line (VGH), is used for the first low potential (VSSL), the input of the second low potential (VSS) and the first high potential (VGH)；
First clock line (CK1) connect with the first signal input part of N grades of shift register cells, is used for as institute State N grades of shift register cell transmission clock signals；The of second clock line (CK2) and N+1 grades of shift register cells One signal input part connection, for transmitting clock signal for the N+1 grades of shift register cells；Third clock line (CK3) It is connect with the first signal input part of N+2 grades of shift register cells, for being transmitted for the N+2 shift register cell Clock signal；4th clock line (CK4) is connect with the first signal input part of N+3 grades of shift register cells, is the N + 3 shift register cells transmit clock signal；
The third signal input part of the shift register cell of the first order connects the second enabling signal line (STV2)；The first order Shift register cell the fourth signal input terminal connect the first enabling signal line (STV1)；The shift LD of the first order First signal output end of device unit is connect with the third signal input part of next stage shift register cell；The first order The second signal output end of shift register cell is connect with the fourth signal input terminal of next stage shift register cell；
The third signal input part of the N+1 grades of shift register cells and previous stage shift register cell The connection of first signal output end；The fourth signal input terminal and previous stage of the N+1 grades of shift register cells shift The second signal output end of register cell connects；
The second signal input terminal of the N+1 grades of shift register cells and next stage shift register cell The connection of second signal output end.
According to the third aspect, a kind of display device is provided in a kind of embodiment, comprising:
Panel, the panel include the two-dimensional array being made of multiple pixels, and with pixel phase each in array The multiple data lines of first direction even and a plurality of controlling grid scan line of second direction；
Further include the gate driving circuit as described in second aspect, provides gate drive signal for the controlling grid scan line.
A kind of shift register cell, gate driving circuit and display device of foundation above-described embodiment, by using DC channel, drive circuit power consumption meeting is not present compared to the static inverters structure of diode connection in dynamic inverter structure It is lower, meet the low-power consumption requirement of display screen.Display device using the gate driving circuit is possessing large scale high-resolution While display panel, also have the characteristics that high reliablity, long working life.
Detailed description of the invention
Fig. 1 is a kind of shift register cell structural schematic diagram；
Fig. 2 is a kind of electrical block diagram of the shift register cell of embodiment；
Fig. 3 is a kind of inverter modules electrical block diagram of the shift register cell of embodiment；
Fig. 4 is a kind of inverter modules electrical block diagram of the shift register cell of embodiment；
Fig. 5 is a kind of inverter modules electrical block diagram of the shift register cell of embodiment；
Fig. 6 is a kind of inverter modules electrical block diagram of the shift register cell of embodiment；
Fig. 7 is a kind of inverter modules electrical block diagram of the shift register cell of embodiment；
Fig. 8 is a kind of working timing figure of the gate driving circuit of embodiment；
Fig. 9 is a kind of gate driving circuit cascade connection schematic diagram of embodiment；
Figure 10 is a kind of gate driving circuit cascade operation time diagram of embodiment；
Figure 11 is that a kind of gate driving circuit internal node QB current potential of embodiment compares schematic diagram；
Figure 12 is a kind of output waveform diagram of the gate driving circuit of embodiment；
Figure 13 is that a kind of output waveform of the gate driving circuit of embodiment compares schematic diagram.
Specific embodiment
Below by specific embodiment combination attached drawing, invention is further described in detail.Wherein different embodiments Middle similar component uses associated similar element numbers.In the following embodiments, many datail descriptions be in order to The application is better understood.However, those skilled in the art can recognize without lifting an eyebrow, part of feature It is dispensed, or can be substituted by other elements, material, method in varied situations.In some cases, this Shen Please it is relevant it is some operation there is no in the description show or describe, this is the core in order to avoid the application by mistake More descriptions are flooded, and to those skilled in the art, these relevant operations, which are described in detail, not to be necessary, they Relevant operation can be completely understood according to the general technology knowledge of description and this field in specification.
It is formed respectively in addition, feature described in this description, operation or feature can combine in any suitable way Kind embodiment.Meanwhile each step in method description or movement can also can be aobvious and easy according to those skilled in the art institute The mode carry out sequence exchange or adjustment seen.Therefore, the various sequences in the description and the appended drawings are intended merely to clearly describe a certain A embodiment is not meant to be necessary sequence, and wherein some sequentially must comply with unless otherwise indicated.
It is herein component institute serialization number itself, such as " first ", " second " etc., is only used for distinguishing described object, Without any sequence or art-recognized meanings.And " connection ", " connection " described in the application, unless otherwise instructed, include directly and It is indirectly connected with (connection).
As described in the background section, it should reasonable design inverter circuit, so that when the threshold voltage shift of TFT, Integrated gate drive circuitry remains to normally work.As shown in Figure 1, being a kind of shift register cell structural schematic diagram, the shifting Bit register cellular construction includes transistor T110, transistor T121, transistor T122, transistor T123, transistor T124, crystalline substance Body pipe T131, transistor T132, transistor T141, transistor T142, transistor T151, transistor T152, first capacitor Cb and Second capacitor Cs, VOUTn-1 is the line scan signals of previous stage shift register cell, Carryn-1 previous stage shift register The cascade Mach-Zehnder interferometer signal of unit, the cascade Mach-Zehnder interferometer signal of Carryn+1 rear stage shift register cell, Carryn are the same level shifting The cascade Mach-Zehnder interferometer signal of bit register unit, VOUTn-1 are the line scan signals of previous stage shift register cell, and VOUT is this The line scan signals of grade shift register cell, VDD are high potential, and VSSL is the first low potential, and VSS is the second low potential, and Q is First internal node, QB are the second internal nodes, and CLK is pulse signal.The control electrode of transistor T110 is posted with previous stage displacement The cascade Mach-Zehnder interferometer signal output end of storage unit connects, the cascade Mach-Zehnder interferometer signal for previous stage shift register cell it is defeated Enter.The first pole of transistor T110 is connect with the line scan signals output end of previous stage shift register cell.Transistor T110 The second pole connect with internal node Q.The control electrode of transistor T121 and the cascade Mach-Zehnder interferometer of rear stage shift register cell are believed The connection of number output end, the input for rear stage cascade Mach-Zehnder interferometer signal.The control electrode of transistor T122 is connect with internal node QB. The first pole of transistor T121 and transistor T122 is connect with internal node Q.The second pole of transistor T121 and transistor T122 The second pole connection.The control electrode of transistor T123 is connect with the line scan signals output end of rear stage shift register cell. The first pole of transistor T123 is connected with the second pole of transistor T121.The second pole of transistor T123 and previous stage shift LD The line scan signals output end of device unit connects.The control electrode of transistor T124 is connect with internal node QB.Transistor T124's First pole is connected with the second pole of transistor T121.The second pole of transistor T124 and the grade joint control of the same level shift register cell Signal output end connection processed.Second capacitor Cs is connected between the first pole of transistor T124 and the second pole.Transistor T131's Control electrode and first it is extremely short connect, and connect with high potential VDD.The second pole of transistor T131 is connect with internal node QB.Crystal The control electrode of pipe T132 is connect with internal node QB.The first pole of transistor T132 is connect with internal node Q.Transistor T132's Second pole is connect with the second low potential VSS.The control electrode of transistor T141 and transistor T142 are connect with internal node Q.Crystal The first pole of pipe T141 and transistor T142 is connect with pulse signal CK input terminal.The second pole of transistor T141 and the same level shift The cascade Mach-Zehnder interferometer signal output end of register cell is connected.The second pole of transistor T142 and the row of the same level shift register cell Scanning signal output end is connected.Capacitor C b is connected between the control electrode of transistor T124 and the second pole.Transistor T151 and crystalline substance The control electrode of body pipe T152 is connect with internal node QB.The first pole of transistor T151 and the cascade of the same level shift register cell Control signal output is connected.The second pole of body pipe T151 is connect with the first low potential VSSL.The first pole of transistor T152 with The line scan signals output end of the same level shift register cell is connected.The second pole of body pipe T152 is connect with the second low potential VSS. Phase inverter in shift register cell circuit connects into diode, and input signal is the driving tube grid of transistor T132 Electrode potential Q, output signal are the inversion signal QB of the driving tube grid potential of transistor T132, the circuit knot to work in this mode Structure is static inverters.When the shortcomings that static inverters is trombone slide work instantly, the upper trombone slide of conducting will affect the electricity of output end Position, and there are the DC channels of VDD to GND, therefore the size of the upper trombone slide of static inverters and lower trombone slide is difficult to choose.
An explanation first is made to some terms involved by the application below.
Transistor in the application can be the transistor of any structure, such as bipolar junction transistor (BJT) or field effect Answer transistor (FET).When transistor is bipolar junction transistor, control electrode refers to the grid of bipolar junction transistor, the first pole It can be the collector or emitter of bipolar junction transistor, corresponding second extremely can be the emitter or collection of bipolar junction transistor Electrode, in actual application, " emitter " and " collector " can be exchanged with basis signal flow direction；When transistor is field effect When answering transistor, control electrode refers to the grid of field effect transistor, and first extremely can be drain electrode or the source of field effect transistor Pole, corresponding second extremely can be source electrode or the drain electrode of field effect transistor, in actual application, " source electrode " and " drain electrode " It can be exchanged with basis signal flow direction.Transistor in display device is usually thin film transistor (TFT) (TFT), at this point, transistor Control electrode refers to the source electrode of thin film transistor (TFT).Light-emitting component can be Organic Light Emitting Diode (Organic Light- Emitting Diode, OLED), electrodeless light emitting diode and light emitting diode with quantum dots etc. in other embodiments can also be with It is other light-emitting components.The first end of light-emitting component can be cathode or anode, and correspondingly, then the second end of light-emitting component is sun Pole or cathode.It should be understood by those skilled in the art that: electric current should flow to cathode from the anode of light-emitting component, therefore, be based on electric current Flow direction, can determine the anode and cathode of light-emitting component.Significant level can be high level, be also possible to low level, can root It is adaptively replaced according to the function realization of specific component.First potential end, the second potential end and third potential end are to drive Power supply provided by dynamic circuit work.In one embodiment, the first potential end can be cold end VSSOr ground wire, the second electricity Position end can be cold end VSSLOr ground wire, third potential end can be hot end VH, in other embodiments, can also be with Adaptively replace.It should be understood that for pixel circuit, the first potential end (such as low level end VSSOr ground wire) With third potential end (such as high level end VH) it is not a part of the application pixel circuit, in order to make those skilled in the art more The technical solution of the application is understood well, and is specifically incorporated the first potential end and the second potential end is described by.
It should be noted that for convenience, also for making those skilled in the art be more clearly understood that the application's Technical solution introduces first internal node Q the second internal node QB in present specification and marks to circuit structure relevant portion Know the terminal, and it cannot be said that additionally introduce in circuit.
For convenience of description, high level uses VGHCharacterization, low level use VSSAnd VSSLIt indicates.In embodiments herein In, diode connection refers to that the first pole of thin film transistor (TFT) is connected with control electrode.
In an embodiment of the present invention, using the dynamic reverse phase with cross-linked positive feedback reinforced pipe and bootstrap capacitor Device design can preferably be pressed down in conjunction with two sets of low level designs and STT structure, the electric leakage on the key node of driving circuit System.
Embodiment one:
Referring to FIG. 2, a kind of electrical block diagram of the shift register cell for embodiment, including input module 21, inverter modules 22, pull-down module 23, output module 24 and low level maintenance module 25, input module 21 are used for before The line scan signals of level-one shift register cell output generate control signal.Output module 24 is for generating line scan signals. Pull-down module 23 is used to turn off output module 24 at the end of scanning signal.Low level maintenance module 25 is for maintaining line scan signals Low level.Inverter modules 22 include phase inverter, are maintained for generating control signal function in pull-down module 23 and low level Module 25.22 one end of inverter modules is connected to the second pulse signal RST input terminal as reset signal, and one end is connected to instead The output end of phase device, reset signal trigger phase inverter by inverter modules 22 and export high level, enhance on inverter modules 22 The driving capability of drawing.Shift register cell further include:
First signal input part, for receiving the first clock signal clk；
Second signal input terminal, for receiving the second pulse signal RST；
Third signal input part, for receiving line scan signals OUTn-1；
Fourth signal input terminal, for receiving cascade Mach-Zehnder interferometer signal COUTn-1；
First signal output end, for exporting line scan signals OUTn；
Second signal output end controls signal COUT for output cascaden；
First current potential input terminal, the input for the first low potential VSSL；
Second current potential input terminal, the input for the second low potential VSS；
Third current potential input terminal, the input for the first high potential VGH；
First internal node Q is the connecting node between input module 21 and pull-down module 23, output module 24；In second Portion node QB is the connecting node between the inverter modules 22 and pull-down module 23.
Input module 21 is connected between third signal input part, fourth signal input terminal and the first internal node Q, is used for First internal node Q is pre-charged.
Inverter modules 22 are connected to second signal input terminal, fourth signal input terminal, the first current potential input terminal, third electricity Between position input terminal and second signal output end, for generating the electricity with the first internal node Q reverse phase in the second internal node QB Signal.
Pull-down module 23 is connected to the first internal node Q, the second internal node QB, the first current potential input terminal and second signal Between output end, for the current potential of the first internal node Q to be down to the first current potential VSSL.
Output module 24 is connected to the first signal input part, the first internal node Q, the first signal output end and second signal Between output end, signal COUT is controlled for output cascadenWith output line scan signals OUTn。
Low level maintenance module 25 be connected to the second internal node QB, the second current potential input terminal, the first signal output end and Between second signal output end, for the current potential of the first signal output end and second signal output end to be down to the second current potential respectively (VSS) and the first current potential (VSSL).
Input module 21 includes the first transistor T11, for being pre-charged to the first internal node Q.The first transistor The control electrode of T11 is connect with fourth signal input terminal.The first pole of the first transistor T11 is connect with third signal input part.The The second pole of one transistor T11 is connect with the first internal node Q.
Pull-down module 23 includes second transistor T31, third transistor T32 and the 4th transistor T33, for will be in first The potential drop of portion node Q is down to the first low potential VSSL.The control electrode of second transistor T31 and third transistor T32 and second Internal node QB connection.The first pole of second transistor T31 is connect with the first internal node Q.The second pole of second transistor T31 It is connect with the first pole of third transistor T32.The second pole of third transistor T32 is connect with the first current potential input terminal.4th is brilliant The control electrode of body pipe T33 is connect with second signal output end.The first pole of 4th transistor T33 and control electrode are shorted.4th is brilliant The second pole of body pipe T33 is connect with the second pole of second transistor T31.
Output module 24 includes the 5th transistor (T41), the 6th transistor T42 and first capacitor Cb, is used for output cascade Control signal COUTnWith output line scan signals OUTn.The control electrode and first of 5th transistor (T41) and the 6th transistor T42 Internal node Q connection.The first pole of 5th transistor (T41) and the 6th transistor T42 are connect with the first signal input part.5th Second pole of transistor (T41) is connect with second signal output end.The second pole of 6th transistor T42 and the first signal output end Connection.First capacitor Cb is connected between the control electrode and the second pole of the 6th transistor T42.
Low level maintenance module 25 includes the 7th transistor T51 and the 8th transistor T52, is used for the first signal output end It is down to the second current potential VSS and the first current potential VSSL respectively with the current potential of second signal output end.7th transistor T51 and the 8th is brilliant The control electrode of body pipe T52 is connect with the second internal node QB.7th the first pole transistor T51 is connect with second signal output end. 7th the second pole transistor T51 is connect with the first current potential input terminal.8th the first pole transistor T52 and the first signal output end connect It connects.8th the second pole transistor T52 is connect with the second current potential input terminal.
Inverter modules 22 include the tenth transistor T21, the 11st transistor T22, the tenth two-transistor T23, the 13rd Transistor T24, the 14th transistor T25, the 15th transistor (T26) and the second capacitor Cs.Tenth transistor T21 and the 12nd The control electrode of transistor T23 is connect with fourth signal input terminal.The first electrode of tenth transistor T21 and the second internal node QB Connection.The second electrode of tenth transistor T21 is connect with the first current potential input terminal.The second electrode of tenth two-transistor T23 with Second internal node QB connection.The first electrode of tenth two-transistor T23 is connected with the second pole of the 11st transistor T22.The The control electrode of 11 transistor T22 is connect with second signal input terminal.The first electrode and third current potential of 11st transistor T22 Input terminal connection.The control electrode of 13rd transistor T24 is connect with the second pole of the 11st transistor T22.13rd transistor The first pole of T24 is connect with third current potential input terminal.The second pole of 13rd transistor T24 is connect with the second internal node QB. Second capacitor Cs is connected between the first control electrode and the second pole of the 13rd transistor T24.The first of 14th transistor T25 Pole is connected with the second pole of the 11st transistor T22.The second pole of 14th transistor T25 is connect with third current potential input terminal. The control electrode of 14th transistor T25 is connect with the second internal node QB.The control electrode and second signal of 15th transistor T26 Output end connection.The first pole of 15th transistor T26 is connect with the second internal node QB.The second of 15th transistor T26 Pole is connect with the first current potential input terminal.Wherein, the received second pulse signal RST of second signal input terminal is the shift register The cascade Mach-Zehnder interferometer signal COUT of the rear stage shift register cell output of unitn+1。
Further, as shown in figure 3, a kind of inverter modules circuit structure signal of the shift register cell for embodiment Figure, the control electrode of the 14th transistor T25 or can connect with the second pole of the 11st transistor T22.
Or, as shown in figure 4, for a kind of embodiment shift register cell inverter modules electrical block diagram, Inverter modules 22 can also include the tenth transistor T21, the 13rd transistor (T24), the 14th transistor (T25) and the tenth Five transistors (T26).The control electrode of 13rd transistor T24 is connect with second signal input terminal.13rd transistor T24 and The first pole of 14 transistor T25 is connect with third current potential input terminal.13rd transistor T24's and the 14th transistor T25 Second pole is connect with the second internal node QB.The control electrode of 14th transistor T25 and second extremely short connects.Tenth transistor T21 Control electrode connect with fourth signal input terminal.The first pole of tenth transistor T21 is connect with the second internal node QB.Tenth is brilliant The second pole of body pipe T21 is connect with the first current potential input terminal.The control electrode and second signal output end of 15th transistor T26 connects It connects.The first pole of 15th transistor T26 is connect with the second internal node QB.The second pole and first of 15th transistor T26 The connection of current potential input terminal.Wherein, the received second pulse signal RST of second signal input terminal is clock pulse signal CKA, clock Signal CKA can be the clock signal of the first signal input part of the next stage shift register cell of the shift register cell CLK。
Or, as shown in figure 5, for a kind of embodiment shift register cell inverter modules electrical block diagram, Inverter modules 22 can also include the tenth transistor T21, the 13rd transistor T24 and the 15th transistor (T26).13rd Transistor T24 is double gate transistor, including the first control electrode and the second control electrode.The control electrode of tenth transistor T21 with The connection of fourth signal input terminal.The first pole of tenth transistor T21 is connect with the second internal node QB.Tenth transistor T21's Second pole is connect with the first current potential input terminal.The first control electrode of 13rd transistor T24 is connect with second signal input terminal.The The first pole of 13 transistor T24 is connect with third current potential input terminal.The second control electrode of 13rd transistor T24 and the second pole It is shorted, and is connect with the second internal node QB.The control electrode of 15th transistor T26 is connect with second signal output end.Tenth The first pole of five transistor T26 is connect with the second internal node QB.The second pole of 15th transistor T26 and the first current potential input End connection.Wherein, the received second pulse signal RST of second signal input terminal is clock pulse signal CKA, clock signal CKA It can be the clock signal clk of the first signal input part of the next stage shift register cell of the shift register cell.
Or, as shown in fig. 6, for a kind of embodiment shift register cell inverter modules electrical block diagram, Inverter modules 22 can also include the tenth transistor T21, the 11st transistor T22, the tenth two-transistor T23, the 13rd crystalline substance Body pipe T24, the 15th transistor (T26) and the second capacitor Cs；
The control electrode of tenth transistor T21 and the tenth two-transistor T23 is connect with fourth signal input terminal.Tenth transistor The first electrode of T21 is connect with the second internal node QB.The second electrode of tenth transistor T21 and the first current potential input terminal connect It connects.The second electrode of tenth two-transistor 23 is connect with the second internal node QB.The first electrode of tenth two-transistor T23 and The second pole of 11 transistor T22 connects.The control electrode of 11st transistor T22 is connect with second signal input terminal.11st The first electrode of transistor T22 is connect with third current potential input terminal.13rd transistor T24 is double gate transistor, including First control electrode and the second control electrode.The first control electrode of 13rd transistor T24 and the second pole of the 11st transistor T22 connect It connects.The second control electrode of 13rd transistor T24 is connected with second electrode, and is connect with the second internal node QB.13rd is brilliant The first electrode of body pipe T24 is connect with third current potential input terminal.The control electrode and second signal output end of 15th transistor T26 Connection.The first pole of 15th transistor T26 is connect with the second internal node QB.The second pole of 15th transistor T26 and the The connection of one current potential input terminal.Second capacitor Cs is connected between the first control electrode and the second pole of the 13rd transistor T24.Its In, the received second pulse signal RST of second signal input terminal is the rear stage shift register list of the shift register cell The cascade Mach-Zehnder interferometer signal COUT of member outputn+1。
Or, as shown in fig. 7, for a kind of embodiment shift register cell inverter modules electrical block diagram, Inverter modules 22 can also include the tenth transistor T21, the 11st transistor T22, the tenth two-transistor T23, the 13rd crystalline substance Body pipe T24, the 15th transistor (T26) and the second capacitor Cs.Tenth transistor T21 is double gate transistor, including first Control electrode and the second control electrode.The control electrode and fourth signal of tenth transistor T21 the first control electrode and the tenth two-transistor T23 Input terminal connection.The second control electrode of tenth transistor T21 is connect with the first internal node Q.The first electricity of tenth transistor T21 Pole is connect with the second internal node QB.The second electrode of tenth transistor T21 is connect with the first current potential input terminal.12nd crystal The second electrode of pipe T23 is connect with the second internal node QB.The first electrode and the 11st transistor of tenth two-transistor T23 The second pole of T22 connects.The control electrode of 11st transistor T22 is connect with second signal input terminal.11st transistor T22's First electrode is connect with third current potential input terminal.13rd transistor T24 is double gate transistor, including the first control electrode and Second control electrode.The first control electrode of 13rd transistor T24 is connected with the second pole of the 11st transistor T22.13rd is brilliant The second control electrode of body pipe T24 is connected with second electrode, and is connect with the second internal node QB.The of 13rd transistor T24 One electrode is connect with third current potential input terminal.15th transistor T26 is double gate transistor, including the first control electrode and Two control electrodes.The first control electrode of 15th transistor T26 is connect with second signal output end.The of 15th transistor T26 Two control electrodes are connect with the first internal node Q.The first electrode of 15th transistor T26 is connect with the second internal node QB.The The second electrode of ten transistor T21 is connect with the first current potential input terminal.Second capacitor Cs is connected to the of the 13rd transistor T24 Between one control electrode and the second pole.Wherein, the received second pulse signal RST of second signal input terminal is the shift register list The cascade Mach-Zehnder interferometer signal COUT of the rear stage shift register cell output of membern+1。
Shift register cell in summary, wherein second signal input terminal is for receiving second clock signal or being somebody's turn to do The cascade Mach-Zehnder interferometer signal COUTn of the next stage shift register cell output of shift register cell.Third signal input part with The line scan signals output end of the shift register cell previous stage shift register cell connects, for receiving the shift LD The line scan signals OUTn of device unit previous stage shift register cell output.Fourth signal input terminal and the shift register list The cascade Mach-Zehnder interferometer signal output end of first previous stage shift register cell connects, for receiving the shift register cell previous stage The cascade Mach-Zehnder interferometer signal COUTn of shift register cell output.First signal output end is next with the shift register cell The line scan signals input terminal connection of grade shift register cell, for exporting line scan signals to the shift register cell Next stage shift register cell.The next stage shift register cell of second signal output end and the shift register cell The connection of cascade Mach-Zehnder interferometer signal input part is moved for output cascade control signal COUTn to the next stage of the shift register cell Bit register unit.
Referring to FIG. 8, a kind of working timing figure of the gate driving circuit for embodiment, is that displacement as shown in Figure 2 is posted The working sequence of storage unit.Wherein, CLK indicates clock signal, and OUTn-1 indicates the output of upper level shift register cell Line scan signals, COUTn-1 indicate that the cascade Mach-Zehnder interferometer signal of upper level shift register cell output, COUTn+1 indicate next The cascade Mach-Zehnder interferometer signal of grade shift register cell output, Q indicate that first node voltage, QB indicate second node voltage, OUTn Indicate the line scan signals of the same level shift register cell output.It is expert in a frame time of scanning including pre-charging stage, certainly Act stage, drop-down stage and low level maintenance stage.
Pre-charging stage includes T1 to the T2 moment, the line scan signals OUTn-1 of previous stage shift register cell circuit and Cascade Mach-Zehnder interferometer signal COUTn-1 becomes high level, and the first internal node Q is electrically charged, and current potential is elevated.At the same time, previous stage The current potential of first internal node QB is pulled low to low level by the cascade Mach-Zehnder interferometer signal COUTn-1 of shift register cell circuit, control The lower trombone slide T31 being connected with the first internal node Q and T32 shutdown is made, the charging rate of the first internal node Q is accelerated.Upper level The low potential of the cascade Mach-Zehnder interferometer signal COUTn-1 of shift register cell output is lower than the output of upper level shift register cell The low potential of line scan signals OUTn-1.In next bootstrapping stage, when the first internal node Q is hanging, input transistors T11 It is reverse-biased, the first internal node Q can be inhibited to leak electricity.In this stage, the pull-down module and low level dimension of the second internal node QB control Module is held to be in close state.
Bootstrapping stage includes T2 to the T3 moment, and the first clock signal clk becomes high level, since the first internal node Q is The current potential of high level, the horizontal scanning line signal OUTn and cascade Mach-Zehnder interferometer signal COUTn of the output of the same level shift register cell will Rise, the current potential of the first internal node Q also can be with rising due to the coupling of first capacitor Cb.Therefore in bootstrapping stage sheet The horizontal scanning line signal OUTn and cascade Mach-Zehnder interferometer signal COUTn of grade shift register cell output will rapidly be drawn to the full amplitude of oscillation High level.
The drop-down stage includes T3 to the T4 moment, and the first clock signal clk becomes low level, next stage shift register cell The cascade Mach-Zehnder interferometer signal COUTn+1 of circuit becomes high level, therefore transistor T22 is opened, by internal node QC shown in Fig. 2 It is charged to high level.Therefore, the T24 that pulls up transistor is opened, and the second internal node QB is electrically charged, its current potential is elevated.Connection The transistor T51 and crystal of part are maintained in the pull-down transistor T31 and transistor T32 and low level of the second internal node QB Pipe T52 conducting, the line scan signals OUTn and cascade Mach-Zehnder interferometer that the first internal node Q and the same level shift register cell are exported Signal COUTn is drawn to low potential.Here, there are two effects by the second capacitor Cs:
1) for when the threshold voltage polarization of TFT, the raising meeting of the current potential of the second internal node QB is so that the first internal node Q boots to higher current potential, so that the output current potential of the second internal node QB point will be elevated；
2) the second capacitor of Cs is also able to maintain the charge of the second internal node QB, inhibits the electric leakage of the second internal node QB point.
When the threshold voltage of TFT is partially negative, the grid of positive feedback enhancing transistor T25 is connected with the second internal node QB, The grid for the T24 that pulls up transistor is connected by the transistor T25 pipe of conducting with high potential VGH, and the T24 that pulls up transistor can be in second Portion's node QB point persistently charges, and maintains the high potential of the second internal node QB point.In addition, source-drain electrode is connected to the crystalline substance of QB and QC point Body pipe T23 pipe, first is that can be pulled down to QC point when phase inverter output is low, turn off the T24 that pulls up transistor, VGH is blocked to arrive The DC channel of VSSL, second is that the high potential of second internal node QB can inhibit QC point to pass through crystalline substance when phase inverter output is high The electric leakage of body pipe T23, the current potential of more stable maintenance internal node QC.
After the low level maintenance stage includes the T4 moment, in the low level maintenance stage, the second internal node QB is maintained surely Fixed high potential, by the transistor T31 of the second internal node QB control, transistor T32, transistor T51, transistor T52 by the The line scan signals OUTn and cascade Mach-Zehnder interferometer signal COUTn of one internal node Q and the same level shift register cell circuit are maintained Low level, while the STT structure that transistor T31, transistor T31 and transistor T33 are constituted inhibits the first internal node Q outstanding When empty, the electric leakage of transistor T31.
In the present embodiment, in shift register cell circuit as shown in Figure 2, the control electrode of the 14th transistor T25 It is connected to the second internal node QB of inverter modules 22, when the reset signal of second signal input terminal input is next stage displacement When the cascade Mach-Zehnder interferometer signal COUTn+1 of register cell output is got higher, the 13rd transistor T24 of upper trombone slide of inverter modules 22 It opens, the second internal node QB point current potential gradually rises, and feedback the 14th transistor T25 of pipe is gradually opened, to upper trombone slide the tenth The control electrode of three transistor T24 charges, so that the second internal node QB current potential further increases, forms a positive feedback in this way and increases Strong structure stabilizes the high potential of the second internal node QB.In inverter modules 22 shown in Fig. 3, the 14th transistor T25 Control electrode with first it is extremely short connect, constitute a diode connection form, when second signal input terminal input reset signal When being that the cascade Mach-Zehnder interferometer signal COUTn+1 of next stage shift register cell output is got higher, the 13rd transistor T24 and the 14th Transistor T25 is opened simultaneously, and the control electrode of the 14th transistor T25 maintains high potential, so that the 13rd transistor T24 opens one It directly charges to the second internal node QB point, inverter modules 22 is kept to export higher level in a frame time.Therefore shown in Fig. 3 Inverter modules 22 equally also can achieve and widen threshold voltage ranges, extend the purpose of circuit working life.It is shown in Fig. 4 Inverter modules 22 in, wherein inverter modules 22 are coupled in second clock signal CKA, high level end VGH, low level end Between the cascade Mach-Zehnder interferometer signal output end COUTn-1 of VSSL, internal node QB and previous stage gate drive unit circuit, it is used for When second clock signal CKA is low level, the cascade Mach-Zehnder interferometer signal COUTn-1 of previous stage gate drive unit circuit is high level When, the current potential of the second internal node QB is drawn to low potential；When second clock signal CKA is high level, upper level shift LD When the cascade Mach-Zehnder interferometer signal COUTn-1 of device element circuit is low level, the current potential of the second internal node QB is charged to high level. When the second internal node QB is high potential, the 13rd transistor T24 with negative threshold voltage is opened, to the second internal node QB charging, when the arrival of the high level period of second clock signal CKA, the 13rd transistor T24 is opened to inside second Node QB charging.In inverter modules 22 shown in Fig. 5, when the arrival of the high level period of second clock signal CKA, 13rd transistor T24, which is opened, charges to the second internal node QB, wherein the second control electrode of the 13rd transistor T24 connects In the second internal node QB, for when the second internal node QB becomes high level, the 13rd transistor T24 of trombone slide in regulation Threshold voltage is partially negative, and the 13rd transistor T24 of trombone slide is made more sufficiently to be opened for the second internal node QB charging.It is shown in Fig. 6 Inverter modules 22 in, when previous stage shift register cell circuit cascade Mach-Zehnder interferometer signal COUTn-1 be high level and under When the cascade Mach-Zehnder interferometer signal COUTn+1 of level-one shift register cell circuit is low level, the current potential of internal node QB is dragged down To low level；When the cascade Mach-Zehnder interferometer signal COUTn-1 of previous stage shift register cell circuit is low level and next stage displacement When the cascade Mach-Zehnder interferometer signal COUTn+1 of register cell circuit is high level, the current potential of internal node QB is charged into high level. Wherein feedback fraction is completed by the second control electrode of the double-gated transistor T24 of inverter modules 22, and the second of double-gated transistor T24 Control electrode is connected to internal node QB, for when internal node QB becomes high level, the threshold voltage of trombone slide T24 to be inclined in regulation It is negative, so that trombone slide T24 is more sufficiently opened for internal node QB charging.
In shift register cell circuit as shown in Figure 7, when the cascade Mach-Zehnder interferometer of previous stage shift register cell circuit Signal COUTn-1 and internal node Q is the cascade Mach-Zehnder interferometer signal COUTn of high level and next stage shift register cell circuit + 1 be low level when, the current potential of internal node QB is pulled low to low level；When the cascade of previous stage shift register cell circuit Control signal COUTn-1 and internal node Q is the cascade Mach-Zehnder interferometer signal of low level and next stage shift register cell circuit When COUTn+1 is high level, the current potential of internal node QB is charged into high level.In this embodiment, inverter modules 22 are anti- Feedback part is completed by the second control electrode of double-gated transistor T24, and the second control electrode of double-gated transistor T24 is connected to internal node QB, for when internal node QB becomes high level, the threshold voltage of trombone slide T24 is partially negative in regulation, keeps trombone slide T24 more abundant It is opened for internal node QB charging.The second control electrode of double-gated transistor T21 is connected to internal node Q, for working as internal node Q When for high level, the threshold voltage for regulating and controlling transistor T21 is partially negative, and the current potential of internal node QB is easier to draw and arrives low level；When When internal node Q is low level, regulate and control the threshold voltage polarization of transistor T21, inhibits leakage of the transistor T21 to internal node QB Electricity.Wherein, pull-down module 23, will be interior when the cascade Mach-Zehnder interferometer signal COUTn of the same level shift register cell circuit is high level Portion node QB maintains low level VSSL, and when internal node QB is high level, the current potential of internal node Q is pulled low to low Current potential.22 transistor T26 of inverter modules is double-gated transistor.The second control electrode of double-gated transistor T26 is connected to internal section Point Q, the threshold voltage for being used to regulate and control when internal node Q is high level transistor T26 is partially negative, is conducive to internal node QB electric leakage To low potential；When internal node Q is low level, regulate and control the threshold voltage polarization of transistor T26, inhibits transistor T26 to interior The electric leakage of portion node QB.
Present applicant proposes dynamic inverter designs, it has cross-linked positive feedback reinforced pipe and bootstrap capacitor, knot Closing two sets of low level designs and STT structure, the electric leakage on the key node of gate driving circuit can preferably be inhibited.This The advantage of kind dynamic inverter design is:
1) circuit is low in energy consumption.The dynamic inverter structure of use, compared to diode connection static inverters structure, There is no DC channel, gate driving circuit power consumption can be lower, meets the low-power consumption requirement of display screen.
2) strong robustness of circuit allows biggish threshold voltage ranges.Specifically when internal node Q is hanging, with Q point Connected transistor is in reverse-biased, inhibits the electric leakage of Q point, when the threshold voltage of transistor drifts about, row scanning letter Number output end is still able to maintain complete waveform.The shift register cell composition gate driving circuit utilize have feedback arrangement and The phase inverter of bootstrap effect enhances the performance for being coupled in the low level maintenance part of inverter output, when the threshold of transistor Threshold voltage polarization or it is partially negative when, low level maintain structure remain to play a role, ensure that the integrated gate drive circuitry just Chang Gongneng.The gate driving circuit can be worked normally when the threshold voltage of transistor is -8V to+9V, increase grid drive The robustness and the scope of application of dynamic circuit.
Embodiment two:
As shown in figure 9, for a kind of gate driving circuit cascade connection schematic diagram of embodiment, including the first clock line CK1, Second clock line CK2, third clock line CK3, the 4th clock line CK4, the first enabling signal line STV1, the first enabling signal line STV2 and the first low potential line VSSL, the second low potential line VSS, third equipotential line VGH, line scan signals line OUTn, grade joint control Signal wire COUTn processed.The gate driving circuit further includes the N+1 grades of cascade shift register lists as described in embodiment one Member, wherein N is positive integer.The first current potential input terminal, the second current potential input terminal and the third electricity of every level-one shift register cell Position input terminal is connect with the first low potential line VSSL, the second low potential line VSS and third equipotential line VGH respectively, low for first The input of current potential VSSL, the second low potential VSS and the first high potential VGH.First clock line CK1 and N grades of shift register lists The first signal input part connection of member, for transmitting clock signal for N grades of shift register cells.Second clock line CK2 with The first signal input part connection of N+1 grades of shift register cells, for transmitting clock for N+1 grades of shift register cells Signal.Third clock line CK3 is connect with the first signal input part of N+2 grades of shift register cells, for shifting for N+2 Register cell transmits clock signal.First signal input part of the 4th clock line CK4 and N+3 grades of shift register cells connects It connects, for transmitting clock signal for N+3 shift register cell.
Wherein, gate driving circuit cascade connection schematic diagram shown in Fig. 9, expression is by N+3 grades of shift register The gate driving circuit that unit cascaded mode forms, wherein first N grades is used to generate the line scan signals of gate driving circuit, most 3 grades (N+1 grades, N+2 grades and N+3 grades of shifting deposit units) are dummy grades afterwards, for generating the reset of previous stage needs Signal, i.e. the second pulse signal RST.The third signal input part of the shift register cell of the first order connects the second enabling signal Line STV2.The fourth signal input terminal of the shift register cell of the first order connects the first enabling signal line STV1.The first order First signal output end of shift register cell is connect with the third signal input part of next stage shift register cell.First The second signal output end of shift register cell of grade is connect with the fourth signal input terminal of next stage shift register cell. The third signal input part of N+1 grades of shift register cells and the first signal output end of previous stage shift register cell connect It connects.The fourth signal input terminal of N+1 grades of shift register cells and the second signal of previous stage shift register cell export End connection.The second signal input terminal of N+1 grades of shift register cells and the second signal of next stage shift register cell Output end connection.Wherein, clock signal CK1-CK4 is the not overlapping clock signal that four duty ratios are 25%, STV1 and STV2 For starting impulse signal, VSS and VSSL are global power line.
It as shown in Figure 10, is a kind of gate driving circuit cascade operation time diagram of embodiment, including pumping signal STV1, STV2, clock signal CK1-CK4, low level signal VSS and VSSL.O<1>-O<5>is Pyatyi before the gate driving circuit The line scan signals of shift register cell circuit output.O<n+1>-O<n+3>is that the last three-level displacement of gate driving circuit is posted The reset signal of (i.e. dummy grades) of storage unit output.Starting impulse signal STV1 and STV2 are coupled in first order shift LD The input terminal of device makes the gate driving circuit for being pre-charged when STV1 and STV2 signal is high level to internal node Q It is sequentially generated line scan signals.At the same time, STV1 signal is coupled in the reset of dummy grades of the gate driving circuit afterbody End sequentially generates next frame for dummy grades of afterbody being resetted and being generated when STV1 signal is high level when a frame end The waveform of line scan signals.
Figure 11 is that a kind of gate driving circuit internal node QB current potential of embodiment compares schematic diagram.In the threshold value electricity of TFT When pressure life drift, gate driving circuit is when with/without T25 transistor and the second capacitor Cs in the embodiment of the present application, phase inverter There are significant differences for transient response on the output port of module.Positive feedback reinforced pipe T25 and in the phase inverter of the present embodiment Two capacitor Cs play a role when the threshold voltage of transistor is born with polarization partially respectively.When threshold voltage is partially negative, phase inverter mould The output QB point high potential of block can reach 17V, and when without positive feedback reinforced pipe, current potential can only achieve 9V.Work as threshold voltage When polarization, the output QB point current potential of inverter modules can be raised to 20V by the second capacitor Cs, without the effect of bootstrap capacitor, Its current potential can be only sustained at 8V, this can weaken the function that low level maintains pipe significantly.
Figure 12 is a kind of output waveform diagram of the gate driving circuit of embodiment, and this is shown for 160 grades of grids to drive The part line scan signals output waveform of dynamic circuit.It can be seen that the threshold voltage shift -8V when transistor from the simulation result When with+9V, the gate driving circuit of the present embodiment remains to output complete waveform.This shows the adaptable threshold of the gate driving circuit Threshold voltage working range be -8V arrive+9V, and gate driving circuit as shown in Figure 1 only workable threshold voltage ranges be - 7.1V to+5V.
As shown in figure 13, schematic diagram is compared for a kind of output waveform of the gate driving circuit of embodiment, when there are threshold values When voltage drift, the output waveform of gate driving circuit and gate driving circuit shown in FIG. 1 in the embodiment of the present application is compared Figure, wherein the size and simulated conditions of transistor are all the same.From simulation result as can be seen that the threshold voltage shift-of transistor When 8V, the circuit output waveform of the present embodiment is not deformed, and the output waveform of gate driving circuit shown in FIG. 1 is existing tight It is distorted again, it was demonstrated that the gate driving circuit of the present embodiment can bear larger range of threshold voltage shift, this is largely The working life of circuit can be extended.
As previously mentioned, the grid Q point and phase inverter of driving tube can be inhibited when the threshold voltage of transistor drifts about Output QB point charge leakage it is particularly important to the reliability and stability of integrated gate drive circuitry.
According to the gate driving circuit of above-described embodiment, it is mainly characterized by:
1) inverter modules have the function of positive feedback enhancing.When the threshold voltage of transistor is partially negative, positive feedback reinforced pipe The control electrode of the upper trombone slide of phase inverter is maintained high potential by T25, so that the output QB point of phase inverter is directly connected to direct current Source VDD, it is ensured that the output high potential of QB point.
2) inverter modules have the function of bootstrapping.When the threshold voltage polarization of transistor, the second capacitor Cs of phase inverter The control electrode of the upper trombone slide of phase inverter will be booted to higher current potential, so that the high potential of QB point accordingly mentions when QB point increases It is high.
3) DC channel is not present in inverter modules.The inverters work in a dynamic mode, the cascade Mach-Zehnder interferometer of previous stage Signal controls the lower trombone slide conducting of phase inverter, exports low potential.The upper trombone slide of the cascade Mach-Zehnder interferometer signal control phase inverter of next stage Conducting exports high potential, and the upper trombone slide that will not be worked at the same time and lower trombone slide avoid DC channel.
4) precharge of .Q point is more abundant.The control signal of the lower trombone slide of phase inverter is not controlled by Q point, but by being pre-charged Signal control, while Q point preliminary filling, phase inverter has exported low level, conducive to the precharge of Q point.
5) driving capability of the integrated gate drive circuitry and cascade ability are stronger.Output driving module utilizes bootstrapping electricity Hold, so that the line scan signals OUTn and cascade Mach-Zehnder interferometer signal COUTn of output can rail-to-rail outputs.
Disclosed herein as well is a kind of display devices, including panel and gate driving circuit as described above.Panel includes The two-dimensional array being made of multiple pixels, and the multiple data lines of first direction that are connected with pixel each in array and The a plurality of controlling grid scan line of second direction.Gate driving circuit as described above provides gate drive signal for controlling grid scan line.
Use above specific case is illustrated the present invention, is merely used to help understand the present invention, not to limit The system present invention.For those skilled in the art, according to the thought of the present invention, can also make several simple It deduces, deform or replaces.

Claims (10)

1. a kind of shift register cell, which is characterized in that including input module (21), inverter modules (22), pull-down module (23), output module (24) and low level maintenance module (25)；
Further include:
First signal input part, for receiving the first clock signal (CLK)；
Second signal input terminal, for receiving the second pulse signal (RST)；
Third signal input part, for receiving line scan signals (OUTn-1)；
Fourth signal input terminal, for receiving cascade Mach-Zehnder interferometer signal (COUTn-1)；
First signal output end, for exporting line scan signals (OUTn)；
Second signal output end controls signal (COUT for output cascaden)；
First current potential input terminal is used for the input of the first low potential (VSSL)；
Second current potential input terminal is used for the input of the second low potential (VSS)；
Third current potential input terminal is used for the input of the first high potential (VGH)；
First internal node (Q) is between the input module (21) and the pull-down module (23), the output module (24) Connecting node；
Second internal node (QB) is the connecting node between the inverter modules (22) and the pull-down module (23)；
The input module (21) is connected between third signal input part, fourth signal input terminal and the first internal node (Q), For being pre-charged to first internal node (Q)；
The inverter modules (22) are connected to second signal input terminal, fourth signal input terminal, the first current potential input terminal, third Between current potential input terminal and second signal output end, saved for being generated in second internal node (QB) with first inside The electric signal of point (Q) reverse phase；
The pull-down module (23) is connected to the first internal node (Q), the second internal node (QB), the first current potential input terminal and Between binary signal output end, for the current potential of first internal node (Q) to be down to the first current potential (VSSL)；
The output module (24) is connected to the first signal input part, the first internal node (Q), the first signal output end and second Between signal output end, signal (COUT is controlled for output cascaden) and output line scan signals (OUTn)；
The low level maintenance module (25) is connected to the second internal node (QB), the second current potential input terminal, the output of the first signal Between end and second signal output end, for the current potential of the first signal output end and second signal output end to be down to second respectively Current potential (VSS) and the first current potential (VSSL).
2. shift register cell as described in claim 1, which is characterized in that the inverter modules (22) include the tenth brilliant Body pipe (T21), the 13rd transistor (T24), the 14th transistor (T25) and the 15th transistor (T26)；Described 13rd is brilliant The control electrode of body pipe (T24) is connect with the second signal input terminal；13rd transistor (T24) and the 14th crystalline substance First pole of body pipe (T25) is connect with the third current potential input terminal；13rd transistor (T24) and the 14th crystalline substance Second pole of body pipe (T25) is connect with second internal node (QB)；The control electrode of 14th transistor (T25) and Two extremely short connect；The control electrode of tenth transistor (T21) is connect with the fourth signal input terminal；Tenth transistor (T21) the first pole is connect with second internal node (QB)；The second pole and described first of tenth transistor (T21) The connection of current potential input terminal；The control electrode of 15th transistor (T26) is connect with the second signal output end；Described tenth First pole of five transistors (T26) is connect with second internal node (QB)；Second pole of the 15th transistor (T26) It is connect with the first current potential input terminal；
Or, the inverter modules (22) include the tenth transistor (T21), the 13rd transistor (T24) and the 15th transistor (T26)；The second pole of the tenth transistor (T21) is stated in the control electrode of tenth transistor (T21) and fourth signal input It is connect with the first current potential input terminal；13rd transistor (T24) is double gate transistor, including the first control electrode With the second control electrode；First control electrode of the 13rd transistor (T24) is connect with the second signal input terminal；Described Second control electrode of 13 transistors (T24) with second it is extremely short connect, and connect with the second internal node (QB)；Described 13rd is brilliant First pole of body pipe (T24) is connect with the third current potential input terminal；The control electrode of 15th transistor (T26) with it is described The connection of second signal output end；First pole of the 15th transistor (T26) is connect with second internal node (QB)；Institute The second pole for stating the 15th transistor (T26) is connect with the first current potential input terminal；
Or, the inverter modules (22) include the tenth transistor (T21), the 11st transistor (T22), the tenth two-transistor (T23), the 13rd transistor (T24) and the 15th transistor (T26)；
The control electrode of tenth transistor (T21) and the tenth two-transistor (T23) and the fourth signal input terminal connect It connects；The first electrode of tenth transistor (T21) is connect with second internal node (QB)；Tenth transistor (T21) second electrode is connect with the first current potential input terminal；The second electrode of tenth two-transistor (T23) with it is described Second internal node (QB) connection；The first electrode of tenth two-transistor (T23) and the 11st transistor (T22) Second electrode connection；The control electrode of 11st transistor (T22) is connect with the second signal input terminal；Described 11st The first electrode of transistor (T22) is connect with the third current potential input terminal；13rd transistor (T24) is double gate Transistor, including the first control electrode and the second control electrode；The first control electrode and the described tenth of 13rd transistor (T24) Second pole of one transistor (T22) connects；Second control electrode of the 13rd transistor (T24) is connected with second electrode, and It is connect with second internal node (QB)；The first electrode of 13rd transistor (T24) and the third current potential input End connection；The control electrode of 15th transistor (T26) is connect with the second signal output end；15th transistor (T26) the first pole is connect with second internal node (QB)；Second pole of the 15th transistor (T26) and described the The connection of one current potential input terminal；
Or, the inverter modules (22) include the tenth transistor (T21), the 11st transistor (T22), the tenth two-transistor (T23), the 13rd transistor (T24), the 14th transistor (T25) and the 15th transistor (T26)；
The control electrode of tenth transistor (T21) and the tenth two-transistor (T23) and the fourth signal input terminal connect It connects；The first electrode of tenth transistor (T21) is connect with second internal node (QB)；Tenth transistor (T21) second electrode is connect with the first current potential input terminal；The second electrode of tenth two-transistor (T23) with it is described Second internal node (QB) connection；The first electrode of tenth two-transistor (T23) and the 11st transistor (T22) The connection of second pole；The control electrode of 11st transistor (T22) is connect with the second signal input terminal；Described 11st is brilliant The first electrode of body pipe (T22) is connect with the third current potential input terminal；The control electrode of 13rd transistor (T24) and institute State the second pole connection of the 11st transistor (T22)；First pole of the 13rd transistor (T24) and the third current potential are defeated Enter end connection；Second pole of the 13rd transistor (T24) is connect with second internal node (QB)；Described 14th is brilliant First pole of body pipe (T25) is connected with the second pole of the 11st transistor (T22)；14th transistor (T25) Second pole is connect with the third current potential input terminal；The control electrode of 14th transistor (T25) and second inside are saved The connection of second pole of point (QB) or the 11st transistor (T22)；The control electrode of 15th transistor (T26) with it is described The connection of second signal output end；First pole of the 15th transistor (T26) is connect with second internal node (QB)；Institute The second pole for stating the 15th transistor (T26) is connect with the first current potential input terminal；
Or, the inverter modules (22) include the tenth transistor (T21), the 11st transistor (T22), the tenth two-transistor (T23), the 13rd transistor (T24) and the 15th transistor (T26)；
Tenth transistor (T21) is double gate transistor, including the first control electrode and the second control electrode；Described tenth is brilliant First control electrode of body pipe (T21) and the control electrode of the tenth two-transistor (T23) are connect with the fourth signal input terminal； Second control electrode of the tenth transistor (T21) is connect with first internal node (Q)；Tenth transistor (T21) First electrode connect with second internal node (QB)；The second electrode and described first of tenth transistor (T21) The connection of current potential input terminal；The second electrode of tenth two-transistor (T23) is connect with second internal node (QB)；It is described The first electrode of tenth two-transistor (T23) is connected with the second pole of the 11st transistor (T22)；11st crystal The control electrode of pipe (T22) is connect with the second signal input terminal；The first electrode of 11st transistor (T22) with it is described The connection of third current potential input terminal；13rd transistor (T24) is double gate transistor, including the first control electrode and second Control electrode；First control electrode of the 13rd transistor (T24) is connected with the second pole of the 11st transistor (T22)； Second control electrode of the 13rd transistor (T24) is connected with second electrode, and is connect with second internal node (QB)； The first electrode of 13rd transistor (T24) is connect with the third current potential input terminal；15th transistor (T26) It is double gate transistor, including the first control electrode and the second control electrode；First control electrode of the 15th transistor (T26) It is connect with the second signal output end；Second control electrode of the 15th transistor (T26) and first internal node (Q) it connects；The first electrode of 15th transistor (T26) is connect with second internal node (QB)；Described tenth is brilliant The second electrode of body pipe (T21) is connect with the first current potential input terminal.
3. shift register cell as claimed in claim 2, which is characterized in that the inverter modules (22) further include second Capacitor (Cs) is connected between the first control electrode and the second pole of the 13rd transistor (T24).
4. shift register cell as described in claim 1, which is characterized in that the input module (21) includes first crystal It manages (T11), for being pre-charged to first internal node (Q)；
The control electrode of the first transistor (T11) is connect with the fourth signal input terminal；The first transistor (T11) First pole is connect with the third signal input part；Second pole of the first transistor (T11) and first internal node (Q) it connects.
5. shift register cell as described in claim 1, which is characterized in that the pull-down module (23) includes the second crystal (T31), third transistor (T32) and the 4th transistor (T33) are managed, for the current potential of first internal node (Q) to be down to First current potential (VSSL)；
The control electrode of the second transistor (T31) and third transistor (T32) is connect with second internal node (QB)；Institute The first pole for stating second transistor (T31) is connect with first internal node (Q)；The second of the second transistor (T31) Pole is connect with the first pole of the third transistor (T32)；Second pole of the third transistor (T32) and first current potential Input terminal connection；The control electrode of 4th transistor (T33) is connect with the second signal output end；4th transistor (T33) the first pole and control electrode is shorted；Second pole of the 4th transistor (T33) and the second transistor (T31) The connection of second pole.
6. shift register cell as described in claim 1, which is characterized in that the output module (24) includes the 5th crystal (T41), the 6th transistor (T42) and first capacitor (Cb) are managed, controls signal (COUT for output cascaden) and output row scanning Signal (OUTn)；
The control electrode of 5th transistor (T41) and the 6th transistor (T42) and first internal node (Q) are even It connects；First pole of the 5th transistor (T41) and the 6th transistor (T42) is connect with first signal input part； Second pole of the 5th transistor (T41) is connect with the second signal output end；The second of 6th transistor (T42) Pole is connect with first signal output end；The first capacitor (Cb) is connected to the control electrode of the 6th transistor (T42) And second between pole.
7. shift register cell as described in claim 1, which is characterized in that the low level maintenance module (25) includes the Seven transistors (T51) and the 8th transistor (T52), for distinguishing the current potential of the first signal output end and second signal output end It is down to the second current potential (VSS) and the first current potential (VSSL)；
The control electrode of 7th transistor (T51) and the 8th transistor (T52) and second internal node (QB) are even It connects；7th transistor (T51), first pole is connect with the second signal output end；7th transistor (T51) second Pole is connect with the first current potential input terminal；8th transistor (T52), first pole is connect with first signal output end； 8th transistor (T52), second pole is connect with the second current potential input terminal.
8. shift register cell as described in any one of claim 1 to 7, which is characterized in that the second signal input terminal The cascade Mach-Zehnder interferometer that next stage shift register cell for receiving second clock signal or the shift register cell exports Signal (COUTn)；
The line scan signals of the third signal input part and the shift register cell previous stage shift register cell are defeated Outlet connection, for receiving the line scan signals of the shift register cell previous stage shift register cell output (OUTn)；
The cascade Mach-Zehnder interferometer signal of the fourth signal input terminal and the shift register cell previous stage shift register cell Output end connection, for receiving the cascade Mach-Zehnder interferometer signal of the shift register cell previous stage shift register cell output (COUTn)；
The line scan signals of the next stage shift register cell of first signal output end and the shift register cell Input terminal connection, for exporting line scan signals to the next stage shift register cell of the shift register cell；
The cascade Mach-Zehnder interferometer of the next stage shift register cell of the second signal output end and the shift register cell is believed The next stage shift register cell of the shift register cell is given in the connection of number input terminal for output cascade control signal.
9. a kind of gate driving circuit, which is characterized in that when including the first clock line (CK1), second clock line (CK2), third Clock line (CK3), the 4th clock line (CK4), the first enabling signal line (STV1), the first enabling signal line (STV2) and the first low electricity Bit line (VSSL), the second low potential line (VSS), third equipotential line (VGH), line scan signals line (OUTn), cascade Mach-Zehnder interferometer signal Line (COUTn)；
The gate driving circuit further includes N+1 grades of cascade shift register cells as claimed in claim 8, and wherein N is Positive integer；
The first current potential input terminal, the second current potential input terminal and the third current potential input terminal of every level-one shift register cell respectively with First low potential line (VSSL), the second low potential line (VSS) and third equipotential line (VGH) connection, are used for the first low potential (VSSL), the input of the second low potential (VSS) and the first high potential (VGH)；
First clock line (CK1) connect with the first signal input part of N grades of shift register cells, for being described the N grades of shift register cells transmit clock signal；First letter of second clock line (CK2) and N+1 grades of shift register cells Number input terminal connection, for for N+1 grade shift register cells transmission clock signal；Third clock line (CK3) and N The first signal input part connection of+2 grades of shift register cells, for transmitting clock for the N+2 shift register cell Signal；4th clock line (CK4) is connect with the first signal input part of N+3 grades of shift register cells, is moved for the N+3 Bit register unit transmits clock signal；
The third signal input part of the shift register cell of the first order connects the second enabling signal line (STV2)；The shifting of the first order The fourth signal input terminal of bit register unit connects the first enabling signal line (STV1)；The shift register list of the first order First signal output end of member is connect with the third signal input part of next stage shift register cell；The displacement of the first order The second signal output end of register cell is connect with the fourth signal input terminal of next stage shift register cell；
The third signal input part of the N+1 grades of shift register cells and the first of previous stage shift register cell Signal output end connection；The fourth signal input terminal and previous stage shift LD of the N+1 grades of shift register cells The second signal output end of device unit connects；
The second signal input terminal of the N+1 grades of shift register cells and the second of next stage shift register cell Signal output end connection.
10. a kind of display device, comprising:
Panel, the panel include the two-dimensional array being made of multiple pixels, and be connected with pixel each in array The multiple data lines of first direction and a plurality of controlling grid scan line of second direction；It is characterized by further comprising:
Gate driving circuit as claimed in claim 9 provides gate drive signal for the controlling grid scan line.
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