CN104464645A - Shifting register and display device - Google Patents
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- CN104464645A CN104464645A CN201510007408.6A CN201510007408A CN104464645A CN 104464645 A CN104464645 A CN 104464645A CN 201510007408 A CN201510007408 A CN 201510007408A CN 104464645 A CN104464645 A CN 104464645A
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Abstract
The invention provides a shifting register and a display device. The shifting register comprises a plurality of stages of shifting register units, and each shifting register unit comprises a first output control module, a second output control module, a graded output module and a pull-up node level maintaining capacitor, wherein the graded output module is connected with pull-up nodes, pull-down nodes, a carry signal output end and a driving signal output end and used for outputting carry signals and driving signals in a graded mode so that the driver signals can maintain a high level in the valuation stage and maintain a low level in the reset stage, the pre-charging stage and the non-work stage, the pull-up node level maintaining capacitor is connected between the first low level output end and the source of a first thin film transistor of the first output control module and used for maintaining the level of the pull-up nodes being a high level through the first output control module in the valuation state so that the driving signals can maintain the high level. The shifting register can solve the problem that a shifting register is affected by current leakage of the depletion-type TFT.
Description
The present invention is the applying date is on July 30th, 2012, and application number is 201210266145.7, and denomination of invention is the divisional application of the invention of " shift register cell, shift register and display device ".
Technical field
The present invention relates to organic light emitting display field, particularly relate to a kind of shift register and display device.
Background technology
Along with the development of flat pannel display, high resolving power, narrow frame becomes the trend of development, and will realize high resolving power, and narrow frame display, on panel, integrated gate drive circuitry is most important solution.For a-si (amorphous silicon) and p-si (polysilicon) technology, existing various ripe shift register circuit can well realize this target.Oxide TFT (transistor) is as the very potential semiconductor technology of one, simpler compared to p-si technique, cost is lower, higher compared to a-si mobility, thus more and more come into one's own, be likely OLED (Organic Light Emitting Diode) future, the main flow backboard Driving technique of Flexible Displays.But oxide TFT is a kind of depletion mode transistor, and above-mentioned a-si TFT and p-si TFT is the transistor of enhancement mode.
Fig. 1 is the circuit diagram of traditional basic shift register cell.As shown in Figure 1, this basic shift register cell comprises pull-up thin film transistor (TFT) T1, pull-down thin film T2, bootstrap capacitor C1, pull-up control thin film transistor (TFT) T3, drop-down control thin film transistor (TFT) T4, memory capacitance C2, the first clock signal input terminal CK, second clock signal input part CKB, input end Input, reset terminal Reset and output terminal Output;
Pull-up node (PU point) is the node be connected with the grid of T1, and pull-down node (PD point) is the node be connected with the grid of T2;
And inputting start signal STV, VGL from input end Input is low level.
Fig. 2 is the sequential chart of basic shift register cell as shown in Figure 1 operationally each signal, and VGH is high level.
When using enhancement mode TFT technology to make the circuit of this basic shift register cell, the circuit of this basic shift register cell can normally work, see Fig. 2 bold portion, if but use oxide transistor (depletion mode transistor) when making this circuit, because pull-down transistor cannot be closed, circuit malfunction, is shown in Fig. 2 dotted portion.
The difference of enhancement transistor and depletion mode transistor is shown in Fig. 3 and Fig. 4, and Fig. 3 is the performance diagram of enhancement transistor, and the longitudinal axis of Fig. 3 is the drain current i of enhancement transistor
d, the transverse axis of Fig. 3 is the gate source voltage V of enhancement transistor
gs, can see from Fig. 3, when Vgs is zero, i
dbe zero, when illustrating that Vgs is zero, enhancement transistor is closed completely; Fig. 4 is the performance diagram of depletion mode transistor, and the longitudinal axis of same Fig. 4 is the drain current i of depletion mode transistor
d, the transverse axis of Fig. 4 is the gate source voltage Vgs of depletion mode transistor, but Fig. 4 display be Vgs be zero time, i
dmuch larger than zero, and only when gate source voltage Vgs is-6V, i
dbe just zero, therefore, when gate source voltage Vgs is 0, depletion mode transistor is still in conducting state, cannot close, therefore the existing circuit using a-si technology or p-si technology normally to work, when using oxide transistor to make, because oxide transistor can not be closed, leakage current is comparatively large, and therefore the circuit of traditional basic shift register cell is as described in Figure 1 just no longer applicable.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of shift register and display device, to solve the impact of leakage problem on shift register of depletion type TFT.
In order to achieve the above object, the invention provides a kind of shift register, comprise multi-stage shift register unit;
Except first order shift register cell, the input end of every one-level shift register cell is connected with the carry signal output end of upper level shift register cell;
Except afterbody shift register cell, the reset terminal of every one-level shift register cell is connected with the carry signal output end of next stage shift register cell;
The input end access start signal of first order shift register cell;
The drive singal of the reset terminal access afterbody shift register cell output of afterbody shift register cell;
Described shift register cell comprises:
First output control module, it is connected with pull-up node, for pull-up node being pulled upward to high level in evaluate phase, and pulls down to the first low level at reseting stage;
Second output control module, it is connected with pull-down node, for pull-down node being pulled upward to high level at reseting stage and non-operational phase;
Classification output module, be connected with pull-up node, pull-down node, carry signal output end and drive singal output terminal respectively, for passing through classification output carry signal and drive singal, and make maintain high level at described drive singal in evaluate phase and maintain low level at reseting stage, pre-charging stage and non-operational phase;
Pull-up node level maintains electric capacity, and being connected between described first low level output end and the source electrode of described the first film transistor, is high level for the level maintaining described pull-up node by described first output control module in evaluate phase.
During enforcement, described first output control module comprises the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT); Described the first film transistor, grid is connected with described input end with drain electrode, and source electrode is connected with the drain electrode of described second thin film transistor (TFT); Described second thin film transistor (TFT), grid is connected with described input end, and source electrode is connected with described pull-up node; Described 3rd thin film transistor (TFT), grid is connected with reset terminal, and source electrode is connected with the described drain electrode of the 4th thin film transistor (TFT) and the source electrode of the first film transistor respectively, and drain electrode is connected with described pull-up node; Described 4th thin film transistor (TFT), grid is connected with described reset terminal, and source electrode is connected with the first low level output end.
During enforcement, described classification output module comprises:
Carry output unit, for making carry signal output end export the first low level under the control at described first output control module and the second output control module of pre-charging stage, reseting stage and non-operational phase, and carry signal output end is made to export high level under the control of evaluate phase at described first output control module and the second output control module;
Driver output unit, for making drive singal output terminal export high level under the control of evaluate phase at described first output control module and the second output control module, and drive singal output terminal is made to export the second low level under the control at described first output control module and the second output control module of pre-charging stage, reseting stage and non-operational phase.
During enforcement, described carry output unit comprises the first carry output film transistor and the second carry output film transistor; Described driver output unit comprises the first driving thin film transistor (TFT), second and drives thin film transistor (TFT) and bootstrap capacitor;
Described first carry exports and controls thin film transistor (TFT), and grid is connected with described first output control module, and source electrode is connected with described carry signal output end, and drain electrode is connected with clock signal input terminal;
Described second carry output film transistor, grid is connected with described second output control module, and source electrode is connected with the first low level output end, and drain electrode is connected with described carry signal output end;
Described bootstrap capacitor is parallel with between the grid of described first driving thin film transistor (TFT) and source electrode;
Described first drives thin film transistor (TFT), and grid is connected with described first output control module, and source electrode is connected with described drive singal output terminal, and drain electrode is connected with described clock signal input terminal;
Described second drives thin film transistor (TFT), and grid is connected with described second output control module, and source electrode is connected with the second low level output end, and drain electrode is connected with described drive singal output terminal.
During enforcement, the second low level is greater than the first low level.
During enforcement, described second output control module comprises drop-down control thin film transistor (TFT) and drop-down electric capacity, wherein:
Described drop-down control thin film transistor (TFT), grid is connected with described pull-up node, and source electrode is connected with the first low level output end, and drain electrode is connected with the first end of described pull-down node and described drop-down electric capacity respectively;
Second end of described drop-down electric capacity is connected with described clock signal input terminal.
During enforcement, described first carry output film transistor, described second carry output film transistor, described first drive thin film transistor (TFT) and described second to drive thin film transistor (TFT) to be all depletion type thin film transistor (TFT).
Present invention also offers a kind of display device, it is characterized in that, comprise above-mentioned shift register.
Compared with prior art, shift register of the present invention and display device, using pull-up node level to maintain electric capacity at the level of evaluate phase maintenance pull-up node is high level, thus remove the existing current potential of the source electrode stablizing the thin film transistor (TFT) for pulling drive be connected with pull-up node that described classification output module comprises, make this thin film transistor (TFT) for pulling drive signal when grid potential is drop-down, the voltage difference of grid and source electrode is less than zero and is less than threshold voltage simultaneously, therefore for depletion mode transistor, it is in closed condition, greatly reduce leakage current, prevent pull-up node potential drop-down, thus solve the electrical leakage problems of depletion type shift register circuit, ensure that the normal work of shift register cell, and have employed classification output module, by classification output carry signal and drive singal, and make maintain high level at described drive singal in evaluate phase and maintain low level at reseting stage, pre-charging stage and non-operational phase, thus the leakage problem of solution depletion type TFT is on the impact of the drive singal of shift register cell.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of traditional basic shift register cell;
Fig. 2 is the sequential chart of this basic shift register cell operationally each signal;
Fig. 3 is the performance diagram of enhancement transistor;
Fig. 4 is the performance diagram of depletion mode transistor;
Fig. 5 is the circuit diagram of the first embodiment of the shift register cell that shift register of the present invention comprises;
Fig. 6 is the circuit diagram of the second embodiment of the shift register cell that shift register of the present invention comprises;
Fig. 7 is the circuit diagram of the 3rd embodiment of the shift register cell that shift register of the present invention comprises;
Fig. 8 is the sequential chart of the 3rd embodiment each signal operationally of the shift register cell that shift register of the present invention comprises;
Fig. 9 is the circuit diagram of the 4th embodiment of the shift register cell that shift register of the present invention comprises;
Figure 10 is the circuit diagram of an embodiment of shift register of the present invention.
Embodiment
Expressing for making the object, technical solutions and advantages of the present invention clearly clear, below in conjunction with drawings and the specific embodiments, the present invention being further described in detail again.
The invention provides a kind of shift register and display device, to solve the impact of leakage problem on shift register of depletion type TFT.
As shown in Figure 5, the first embodiment of the shift register cell that shift register of the present invention comprises, comprising:
First output control module 51, it is connected with pull-up node PU, for pull-up node being pulled upward to high level in evaluate phase, at reseting stage, pull-up node is pulled down to the first low level;
Second output control module 52, it is connected with pull-down node PD, for pull-down node being pulled upward to high level at reseting stage and non-operational phase;
Described first output control module 51 comprises the first film transistor T1, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3 and the 4th thin film transistor (TFT) T4;
Described the first film transistor T1, grid is connected with input end Input (n) with drain electrode, and the drain electrode of the second thin film transistor (TFT) T2 described in source electrode connects;
Described second thin film transistor (TFT) T2, grid is connected with described input end Input (n), and source electrode is connected with described pull-up node PU;
Described 3rd thin film transistor (TFT) T3, grid is connected with reset terminal RST (n), and source electrode is connected with the drain electrode of described 4th thin film transistor (TFT) T4 and the source electrode of the first film transistor T1 respectively, and drain electrode is connected with described pull-up node PU;
Described 4th thin film transistor (TFT) T4, grid is connected with reset terminal RST (n), and source electrode is connected with the first low level output end;
First embodiment of the shift register cell that shift register of the present invention comprises also comprises:
Classification output module 53, be connected with pull-up node (PU point), pull-down node (PD point), carry signal output end CA (n) and drive singal output terminal OUT (n) respectively, for by classification output carry signal and drive singal, and make maintain high level at described drive singal in evaluate phase and maintain low level in reseting stage and pre-charging stage and non-operational phase;
Pull-up node level maintains electric capacity C1, being connected between described first low level output end and the source electrode T1 of described the first film transistor, is high level for the level maintaining described pull-up node (PU point) by described first output control module 51 in evaluate phase;
The carry signal output end of the first embodiment of the shift register cell that shift register of the present invention comprises is connected with the input end Input (n+1) of next stage shift register cell, is also connected (not showing in Fig. 5) with the reset terminal RST (n-1) of upper level shift register cell;
M point is the node be connected with the source electrode of described the first film transistor T1, and described first low level output end exports the first low level VGL1.
First embodiment of the shift register cell that shift register of the present invention comprises, the level mainly using pull-up node level maintenance electric capacity C1 to maintain described pull-up node (PU point) in evaluate phase is high level.The existing current potential of the source electrode of the thin film transistor (TFT) (not showing in Fig. 5) be connected with PU point is mainly stablized in concrete operation by electric capacity C1, make this thin film transistor (TFT) when grid potential is drop-down, the voltage difference of grid and source electrode is less than zero and is less than threshold voltage simultaneously, therefore for depletion mode transistor, it is in closed condition, greatly reduce leakage current, prevent PU point current potential drop-down, thus solve the electrical leakage problems of depletion type shift register circuit, ensure that the normal work of shift register cell.
And, in first embodiment of the shift register cell comprised at shift register of the present invention, have employed described classification output module 53, by classification output carry signal and drive singal, and make maintain high level at described drive singal in evaluate phase and maintain low level in reseting stage and pre-charging stage and non-operational phase, thus the leakage problem solving depletion type TFT is on the impact of the drive singal of shift register cell.
As shown in Figure 6, the circuit diagram of the second embodiment of shift register cell that comprises of shift register of the present invention.Second embodiment of shift register cell of the present invention is based on the first embodiment of shift register cell of the present invention.In this second embodiment, described classification output module 53 comprises driver output unit 531 and carry output unit 532, wherein,
Described carry output unit 532 adopts the first low level output end to drive;
Described driver output unit 531 adopts the second low level output end to drive;
Described carry output unit 532, for making carry signal output end CA (n) export the first low level VGL1 at pre-charging stage, reseting stage and non-operational phase under the control of described first output control module 51, and under the control of the second output control module, carry signal output end is made to export high level in evaluate phase;
Described driver output unit 531, for making drive singal output terminal OUT (n) export high level under the control of evaluate phase at described second output control module 52 and the first output control module 51, and drive singal output terminal OUT (n) is made to export the second low level VGL2 under the control of reseting stage at the first output control module 51 and the second output control module 52.
Described first low level output end exports the first low level VGL1, and described second low level output end exports the second low level VGL2;
Described first low level VGL1 is different with the second low level VGL2, thus avoids the leakage problem of depletion type TFT on the impact of the drive singal of shift register cell.
As shown in Figure 7, the circuit diagram of the 3rd embodiment of shift register cell that comprises of shift register of the present invention.Second embodiment of the shift register cell that the 3rd embodiment of the shift register cell that shift register of the present invention comprises comprises based on shift register of the present invention.In the 3rd embodiment,
Described carry output unit 532 comprises the first carry output film transistor T5 and the second carry output film transistor T6;
Described driver output unit 531 comprises the first driving thin film transistor (TFT) T7, second and drives thin film transistor (TFT) T8 and bootstrap capacitor C2;
Described first carry output film transistor T5, grid is connected with described first output control module 51, and source electrode is connected with described carry signal output end CA (n), and drain electrode is connected with clock signal input terminal;
Described bootstrap capacitor C2 is parallel with between the grid of described first driving thin film transistor (TFT) T7 and source electrode;
Described first drives thin film transistor (TFT) T7, and grid is connected with described first output control module 51, and source electrode is connected with described drive singal output terminal OUT (n), and drain electrode is connected with described clock signal input terminal;
Described second carry output film transistor T6, grid is connected with described second output control module 52, and source electrode is connected with the first low level output end, and drain electrode is connected with described carry signal output end CA (n);
Described second drives thin film transistor (TFT) T8, and grid is connected with described second output control module 52, and source electrode is connected with the second low level output end, and drain electrode is connected with described drive singal output terminal OUT (n);
Described first output control module 51 is also connected with the first low level output end and described input end Input (n) respectively;
Described second output control module 52 is also connected with the first low level output end.
Further, T5, T6, T7 and T8 are N-shaped TFT (thin film transistor (TFT)s);
Further, described first carry output film transistor T5, described second carry output film transistor T6, described first drive thin film transistor (TFT) T7 and described second to drive thin film transistor (TFT) T8 to be depletion type thin film transistor (TFT);
Wherein, from clock signal input terminal input clock signal CK, described first low level output end exports the first low level VGL1, and described second low level output end exports the second low level VGL2, and VGL1<VGL2.
In 3rd embodiment of the shift register cell comprised at shift register of the present invention, PU point exports the node that the grid that controls thin film transistor (TFT) T5 is connected, and PD point exports the node that the grid that controls thin film transistor (TFT) T6 is connected.PU point current potential, PD point current potential are controlled by the first output control module 51, second output control module 52 respectively.
3rd embodiment of the shift register cell that shift register of the present invention comprises employs two different drop-down current potentials: VGL1 and VGL2, a drop-down current potential VGL2 is used for drive singal and exports, a drop-down current potential VGL1 is used for feedback and carry signal output, and VGL2 is greater than VGL1, simultaneously the importation of shift register cell at the corresponding levels and reset part employ two TFT series connection, the centre of two TFT connects together, and is connected to M point with electric capacity C1.The clock signal C K of the 3rd embodiment needs of shift register cell that comprises of shift register of the present invention in addition, high level is VGH, and low level is VGL1; The signal function that second output control module 52 exports is in PD point, and high level is VGH, and low level is VGL1; According to the connection of shift register cell at the corresponding levels and the reset terminal RST (n-1) of upper level shift register cell and the input end Input (n+1) to next stage shift register cell, the high level of the signal that input end Input (n) of known shift register cell at the corresponding levels and reset terminal RST (n) receive, low level are respectively VGH, VGL1.
As shown in Figure 8, the course of work of the 3rd embodiment of shift register cell that shift register of the present invention comprises is divided into three phases:
First stage is pre-charging stage S1: clock signal input terminal and reset terminal RST (n) export the first low level VGL1, input end Input (n) exports high level VGH, therefore T1, T2 open, by PU point, bootstrap capacitor C2 is charged, also by M point, C1 is charged simultaneously, source voltage due to T4 is VGL1, the current potential of RST (n) is also VGL1 simultaneously, therefore for T4, Vgs (gate source voltage) is 0, T4 is in certain opening (its family curve corresponding, can see that it is in linear zone, there is certain resistance), along with input end Input (n) is to the charging of C1, M point current potential raises rapidly, for T3, its source potential is the current potential of M point, and the grid potential of T3 is VGL1, therefore the Vgs of T3 is less than 0, after M point current potential rises to certain value, T3 thoroughly closes, because T3 closes, the current potential of PU point can arrive VGH very soon, and the current potential of PD point is VGL1, the Vgs of T6 is that 0, T6 opens, for T8, because VGL2 is greater than VGL1, the Vgs of T8 is less than 0, and therefore T8 closes.Due to the rising of PU point current potential, T5, T7 open, OUT (n) output low level VGL1, CA (n) output low level VGL1;
Second stage is evaluate phase S2:CK saltus step is high level, the jump in potential of input end Input (n) is the first low level VGL1, RST (n) still exports the first low level VGL1, the Vgs of Vgs and T4 of T1 is 0, therefore T1 and T4 is in certain opening (be in linear zone, have certain resistance), the grid potential of T2 and the grid potential of T3 are all VGL1, the source potential of T2 and the source potential of T3 are M point current potential, M point is owing to being connected with C1, although C1 slowly can be discharged by T1 and T4, but M point current potential very fast saltus step can not become VGL1, but slowly decline, as long as the capacitance of C1 reaches a certain predetermined value, within the time of half pulsewidth, the potential difference (PD) at C1 two ends can keep being greater than VGL1 certain value, therefore the gate source voltage Vgs of gate source voltage Vgs and T3 of T2 is less than 0 and can ensures that it is in closed condition, the closedown of T2 and T3 can make PU point current potential continue as high level to remain unchanged, therefore T5 and T7 continues to open, the current potential of PD point continues to keep low level VGL1, therefore T8 continues to close, T6 keeps certain opening, now CK is high level, by C2, PU point current potential is improved further, T5 and T7 opens further, therefore OUT (n) exports high level VGH, CA (n) exports high level VGH simultaneously,
Phase III is reseting stage S3:CK saltus step is the first low level VGL1, RST (n) and PD point export high level VGH, therefore T6 and T8 fully opens, T3 and T4 fully opens, therefore PU point and M point current potential are pulled down to VGL1, the unlatching of T6 and T8 makes OUT (n) export VGL2, and CA (n) exports VGL1;
Operation to this shift register cell terminates, and after PU point current potential is pulled down to VGL1, because OUT (n) exports VGL2, the Vgs of T7 is less than 0, T7 and closes, therefore when CK is again for also having influence on the output of OUT (n) when high level.And although T5 is likely in crack opening, due to the unlatching of T6, therefore CA (n) exports VGL1.
Fig. 9 is the circuit diagram of the 4th embodiment of the shift register cell that shift register of the present invention comprises.3rd embodiment of the shift register cell that the 4th embodiment of the shift register cell that shift register of the present invention comprises comprises based on shift register of the present invention.
As shown in Figure 9, in the 4th embodiment, described second output control module 52 comprises drop-down control thin film transistor (TFT) T9 and pull-up electric capacity C3, wherein:
Drop-down control thin film transistor (TFT) T9, grid is connected with described pull-up node (PU point), and source electrode is connected with the first low level output end, and drain electrode is connected with the first end of described pull-down node (PD point) and described pull-up electric capacity C3 respectively;
Second end of described pull-up electric capacity C3 is connected with described clock signal input terminal.
Should be noted: the second output control module 52 of the present invention has a variety of scheme; the second output control module is as shown in Figure 9 exactly one of embodiment; but the difference of the second output control module is not the essential distinction of this patent and other schemes; as long as employ technical scheme of the present invention, which kind of embodiment the second output control module uses all in the protection domain of patent of the present invention.
Present invention also offers a kind of shift register, comprise multistage above-mentioned shift register cell;
Except first order shift register cell, the input end of every one-level shift register cell is connected with the carry signal output end of upper level shift register cell;
Except afterbody shift register cell, the reset terminal of every one-level shift register cell is connected with the carry signal output end of next stage shift register cell;
The input end access start signal of first order shift register cell;
The drive singal of the reset terminal access afterbody shift register cell output of afterbody shift register cell.
As shown in Figure 10, an embodiment of shift register of the present invention is connected and composed by N level shift register cell, and using the line scanner as active matrix, N is generally the line number of active matrix, and N is positive integer;
S1, S2 ..., Sn ..., SN indicates respectively is first order shift register cell, second level shift register cell ..., n-th grade of shift register cell ..., N level shift register cell;
The clock signal phase of the clock signal that the first clock signal input terminal exports and the input of second clock signal input part is contrary, and dutycycle is 50%;
Wherein, the input end IN of first order shift register accesses inceptive impulse signal STV, and STV is that high level is effective;
The drive singal of the reset terminal access afterbody shift register cell output of afterbody shift register cell;
Except first order shift register cell, the input end of every one-level shift register cell is connected with the carry signal output end of upper level shift register cell; Every one-level shift register has two output terminal: CA (n) to be carry signal output end, and it is connected with the input end Input (n+1) of next stage shift register cell and the reset terminal RST (n-1) of upper level shift register cell respectively; OUT (n) is drive singal output terminal, and it is connected with the horizontal scanning line Gn of active matrix; Wherein, n is positive integer, and n is less than or equal to N;
The clock control signal of adjacent two-stage shift register cell is anti-phase each other, such as: if the input end of clock of first order shift register cell connects clock signal C K, the clock signal input terminal of the second level shift register cell adjacent with this first order shift register cell is connected clock signal C KB, and clock signal C K and clock signal C KB is anti-phase each other.
Embodiments of the invention also provide a kind of display device, comprise shift register as described above in Example, and described display device can comprise liquid crystal indicator, such as liquid crystal panel, LCD TV, mobile phone, liquid crystal display.Except liquid crystal indicator, described display device can also comprise the display device of organic light emitting display or other types, such as electronic reader etc.Sweep signal as the sweep circuit of display device or gate driver circuit etc., to provide function of lining by line scan, can be delivered to viewing area by this shift register.
More than illustrate just illustrative for the purpose of the present invention; and nonrestrictive, those of ordinary skill in the art understand, when not departing from the spirit and scope that claims limit; many amendments, change or equivalence can be made, but all will fall within the scope of protection of the present invention.
Claims (8)
1. a shift register, is characterized in that, comprises multi-stage shift register unit;
Except first order shift register cell, the input end of every one-level shift register cell is connected with the carry signal output end of upper level shift register cell;
Except afterbody shift register cell, the reset terminal of every one-level shift register cell is connected with the carry signal output end of next stage shift register cell;
The input end access start signal of first order shift register cell;
The drive singal of the reset terminal access afterbody shift register cell output of afterbody shift register cell;
Described shift register cell comprises:
First output control module, it is connected with pull-up node, for pull-up node being pulled upward to high level in evaluate phase, and pulls down to the first low level at reseting stage;
Second output control module, it is connected with pull-down node, for pull-down node being pulled upward to high level at reseting stage and non-operational phase;
Classification output module, be connected with pull-up node, pull-down node, carry signal output end and drive singal output terminal respectively, for passing through classification output carry signal and drive singal, and make maintain high level at described drive singal in evaluate phase and maintain low level at reseting stage, pre-charging stage and non-operational phase;
Pull-up node level maintains electric capacity, and being connected between described first low level output end and the source electrode of described the first film transistor, is high level for the level maintaining described pull-up node by described first output control module in evaluate phase.
2. shift register as claimed in claim 1, it is characterized in that, described first output control module comprises the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT); Described the first film transistor, grid is connected with described input end with drain electrode, and source electrode is connected with the drain electrode of described second thin film transistor (TFT); Described second thin film transistor (TFT), grid is connected with described input end, and source electrode is connected with described pull-up node; Described 3rd thin film transistor (TFT), grid is connected with reset terminal, and source electrode is connected with the described drain electrode of the 4th thin film transistor (TFT) and the source electrode of the first film transistor respectively, and drain electrode is connected with described pull-up node; Described 4th thin film transistor (TFT), grid is connected with described reset terminal, and source electrode is connected with the first low level output end.
3. shift register as claimed in claim 2, it is characterized in that, described classification output module comprises:
Carry output unit, for making carry signal output end export the first low level under the control at described first output control module and the second output control module of pre-charging stage, reseting stage and non-operational phase, and carry signal output end is made to export high level under the control of evaluate phase at described first output control module and the second output control module;
Driver output unit, for making drive singal output terminal export high level under the control of evaluate phase at described first output control module and the second output control module, and drive singal output terminal is made to export the second low level under the control at described first output control module and the second output control module of pre-charging stage, reseting stage and non-operational phase.
4. shift register as claimed in claim 3, is characterized in that,
Described carry output unit comprises the first carry output film transistor and the second carry output film transistor; Described driver output unit comprises the first driving thin film transistor (TFT), second and drives thin film transistor (TFT) and bootstrap capacitor;
Described first carry exports and controls thin film transistor (TFT), and grid is connected with described first output control module, and source electrode is connected with described carry signal output end, and drain electrode is connected with clock signal input terminal;
Described second carry output film transistor, grid is connected with described second output control module, and source electrode is connected with the first low level output end, and drain electrode is connected with described carry signal output end;
Described bootstrap capacitor is parallel with between the grid of described first driving thin film transistor (TFT) and source electrode;
Described first drives thin film transistor (TFT), and grid is connected with described first output control module, and source electrode is connected with described drive singal output terminal, and drain electrode is connected with described clock signal input terminal;
Described second drives thin film transistor (TFT), and grid is connected with described second output control module, and source electrode is connected with the second low level output end, and drain electrode is connected with described drive singal output terminal.
5. shift register as claimed in claim 4, it is characterized in that, the second low level is greater than the first low level.
6. the shift register as described in claim 4 or 5, is characterized in that, described second output control module comprises drop-down control thin film transistor (TFT) and drop-down electric capacity, wherein:
Described drop-down control thin film transistor (TFT), grid is connected with described pull-up node, and source electrode is connected with the first low level output end, and drain electrode is connected with the first end of described pull-down node and described drop-down electric capacity respectively;
Second end of described drop-down electric capacity is connected with described clock signal input terminal.
7. shift register as claimed in claim 6, is characterized in that,
Described first carry output film transistor, described second carry output film transistor, described first drive thin film transistor (TFT) and described second to drive thin film transistor (TFT) to be all depletion type thin film transistor (TFT).
8. a display device, is characterized in that, comprises the shift register as described in claim arbitrary in claim 1 to 7.
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