CN109240978B - FPGA system and equipment for building acceleration platform and acceleration platform - Google Patents
FPGA system and equipment for building acceleration platform and acceleration platform Download PDFInfo
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Abstract
The application provides a build FPGA system, equipment and platform with higher speed of platform with higher speed, this system includes: the system comprises an acceleration logic module, a controller, a routing module, an interface module and a monitoring and configuration module; the acceleration logic module is used for executing an acceleration algorithm, processing input information and sending output information to the controller; the controller is used for converting the output information into first communication information and sending the first communication information to the routing module, converting second communication information sent by the routing module into input information and sending the input information to the acceleration logic module; the routing module is used for sending the first communication information to the interface module and sending the second communication information sent by the interface module to the controller; the interface module is used for carrying out data communication with external equipment according to the first communication information and acquiring second communication information from the external equipment; and the monitoring and configuration module is used for carrying out customized development and debugging. The system can improve the efficiency of constructing the hardware acceleration platform by using the FPGA.
Description
Technical Field
The invention relates to the field of FPGA design, in particular to an FPGA system and device for building an acceleration platform and the acceleration platform.
Background
With the continuous development and evolution of algorithms, the traditional method of computing by using a CPU has met a bottleneck in performance, and the computing method of accelerating application by using an FPGA, a GPU and a customized ASIC chip is more and more widely applied. Compared with the acceleration mode of a customized AISC (automatic identification system) chip, the FPGA (Field-Programmable Gate Array) has very good reusability, is suitable for richer application scenes, and can greatly reduce the period from design to application. Compared with the GPU, the FPGA can be designed in a customized mode aiming at specific applications, so that better performance and power consumption optimization space can be obtained.
In the existing FPGA design flow, most of the design flow adopts the standard design idea from top to bottom. The method comprises the steps of starting from system level design, dividing functions to be realized into a plurality of secondary units, then dividing each secondary unit into basic units of the next layer, and so on until the functions can be directly realized by using basic modules or IP cores. However, for the FPGA definitely to be applied to a certain acceleration platform, the development process is complicated by adopting a general top-down design flow, because the FPGA applied to the acceleration platform has a fixed general function, and the main difference is the implementation of the core acceleration algorithm. And the adoption of a top-down design flow is to take the core acceleration algorithm as a sub-function and decompose the core acceleration algorithm and all the sub-functions together step by step, so that the workload of design is increased, and the transplantation of FPGA designs of different acceleration platforms is not facilitated.
Disclosure of Invention
In order to solve the technical problems in the prior art, the application provides an FPGA system, equipment and an acceleration platform for building the acceleration platform, the time for building a hardware acceleration platform by using an FPGA can be shortened, and the building efficiency is improved.
The application provides a build FPGA system of accelerating platform, the system includes: the system comprises an acceleration logic module, a controller, a routing module, an interface module and a monitoring and configuration module;
the acceleration logic module is used for executing an acceleration algorithm, processing input information and sending output information to the controller;
the controller is used for converting the output information into first communication information and sending the first communication information to the routing module, and is also used for converting second communication information sent by the routing module into input information and sending the input information to the acceleration logic module; the controller can realize conversion of general data types
The routing module is configured to send the first communication information to the interface module, and is further configured to send the second communication information sent by the interface module to the controller; the routing module applies a general routing protocol;
the interface module is used for carrying out data communication with external equipment according to the first communication information and acquiring the second communication information from the external equipment; the interface module corresponds to a universal interface protocol and an interface architecture;
and the monitoring and configuration module is used for customized development and debugging.
Optionally, a FIFO memory is integrated in the routing module;
the FIFO memory is used for buffering and controlling the flow of the first communication information and the second communication information.
Optionally, the routing module stops receiving the first communication information and the second communication information when the storage space of the FIFO memory is exhausted.
Optionally, the definition manner of the routing module for each interface width of the interface module is macro definition.
Optionally, the interface module includes: a high speed serial interface.
Optionally, the interface module further includes: a memory controller.
Optionally, the memory controller is connected to the acceleration logic module; the memory controller is used for carrying out data exchange between the acceleration logic module and the storage device.
Optionally, the interface module further includes: a host interface;
the host interface is used for connecting the main control equipment.
The embodiment of the application further provides a device for building the acceleration platform, and the equipment comprises: a peripheral interface layer, a core acceleration layer and a storage device;
the peripheral interface layer comprises the routing module, the interface module and the detection and configuration module;
the core acceleration layer comprises the acceleration logic module and the controller;
the storage device is used for storing the data of the acceleration logic module.
The embodiment of the present application further provides an acceleration platform, the acceleration platform is built by the FPGA system for building the acceleration platform, the acceleration platform further includes: a master control device;
the main control device is used for accessing the acceleration logic module.
Compared with the prior art, the invention has at least the following advantages:
the FPGA system for building the acceleration platform provided by the invention comprises: the system comprises an acceleration logic module, a controller, a routing module, an interface module and a monitoring and configuration module; the acceleration logic module is used for executing an acceleration algorithm, processing input information and sending output information to the controller, and is a core module for realizing the acceleration algorithm; the controller is used for converting the output information into first communication information and sending the first communication information to the routing module, and is also used for converting second communication information sent by the routing module into input information and sending the input information to the acceleration logic module, and the processing process realizes the conversion between the input and output information of the acceleration logic module and the communication information of an external module; the routing module is used for sending the first communication information to the interface module and sending the second communication information sent by the interface module to the controller, so that data communication between the system modules is realized; the interface module is used for carrying out data communication with external equipment according to the first communication information and acquiring second communication information from the external equipment; and the monitoring and configuration module is used for carrying out customized development and debugging. By using the method and the device, the design steps of the FPGA can be simplified, when different acceleration platforms are built, the acceleration logic module is often designed again, and other modules can not be designed again, so that the transplantation and the reuse of each module on different acceleration platforms are ensured to a great extent, and the efficiency of building the acceleration platforms is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram of an FPGA system for building an acceleration platform according to an embodiment of the present application;
fig. 2 is a schematic diagram of another FPGA system for building an acceleration platform according to a second embodiment of the present application;
fig. 3 is a schematic diagram of an FPGA device for building an acceleration platform according to a third embodiment of the present application;
fig. 4 is a schematic diagram of an acceleration platform according to a fourth embodiment of the present application.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment is as follows:
the embodiment of the application provides an FPGA system for building an acceleration platform, which is specifically described below with reference to the accompanying drawings.
Referring to fig. 1, the figure is a schematic diagram of an FPGA system for building an acceleration platform according to an embodiment of the present application.
The system 100 according to the embodiment of the present application includes: an acceleration logic module 101, a controller 102, a routing module 103, an interface module 104 and a monitoring and configuration module 105;
the acceleration logic 101 is configured to execute an acceleration algorithm, process input information, and send output information to the controller 102.
The acceleration logic module 101 includes a logic implementation of an acceleration algorithm used in an actual application scenario, and the logic implementation of this portion should be implemented by constructing a logic computation unit as small as possible, so that an accelerated computation task is divided into several stages of computations, each stage of computations is composed of several small computation units, and the computation stages perform pipeline processing, so that it is easier to accelerate the performance evaluation and optimization of the logic module 101, and meanwhile, the design of the small logic computation units and the overall pipeline stage can realize a great degree of multiplexing in different application scenarios.
The controller 102 is configured to convert the output information into first communication information and send the first communication information to the routing module 103, and is further configured to convert second communication information sent by the routing module 103 into input information and send the input information to the acceleration logic module 101, and in addition, the controller 102 can implement conversion of a general data type.
The first communication information includes information that the acceleration logic module 101 needs to call other modules or external devices after implementing an acceleration algorithm, and the second communication information includes feedback of the call information of the acceleration logic module 101 by the other modules or the external devices and related information of the operating conditions of the other modules or the external devices.
The routing module 103 is configured to send the first communication information to the interface module 104, and is further configured to send the second communication information sent by the interface module 104 to the controller 103.
The routing module 103 can maintain data communication between the modules in the FPGA system, and under the framework of the present invention, the routing module 103 applies a general routing Protocol, that IS, a fixed routing rule may be adopted, and the general routing Protocol may include protocols such as RIP (Route Information Protocol), OSPF (Open Shortest Path First), IS-IS (Intermediate system to Intermediate system), BGP (Border Gateway Protocol), and the like, which IS not specifically limited in this application.
In different application scenarios, along with different use of the interfaces IP in the interface module 104, the data widths of the paths of the interfaces in the routing module 103 and the interface module 104 also change, and for this point, in the design of the routing module, the definition of the width of each interface in the interface module 104 may adopt a macro definition mode, and the value of the macro definition is consistent with that of the corresponding interface, and the macro definition is a name for batch processing, and may be performed according to a series of predefined rules, for example, as follows:
when the interface module 104 includes a memory controller, the interface width of the path between the routing module 103 and the memory controller may be defined by a macro definition of the interface width of the memory controller, and when the interface module 104 includes a host interface, the interface width of the path between the routing module 103 and the memory controller may be defined by a macro definition of the interface width of the host, and at this time, the mode replacement is completed without modifying the code of the routing module to ensure the data width of the interface actually connected.
The interface module 104 is configured to perform data communication with an external device according to the first communication information, and acquire the second communication information from the external device, where the interface module corresponds to a general interface protocol and an interface architecture.
The monitoring and configuration module 105 is used for customized development and debugging, and can consider the requirement of generalization as much as possible in the development and debugging process, and even can keep partial function redundancy, namely some functions are only useful in some specific application scenarios and are not activated in other usage scenarios. Through the redundancy design, the change of the system under different application scenes can be reduced, and the portability of the system is increased.
In the FPGA system for building the acceleration platform provided by the embodiment of the application, the acceleration logic module is used for executing an acceleration algorithm, processing input information and sending output information to the controller, and is a core module for realizing the acceleration algorithm; the controller is used for converting the output information into first communication information and sending the first communication information to the routing module, and is also used for converting second communication information sent by the routing module into input information and sending the input information to the acceleration logic module, and the processing process realizes the conversion between the input and output information of the acceleration logic module and the communication information of an external module; the routing module is used for sending the first communication information to the interface module and sending the second communication information sent by the interface module to the controller, so that data communication between the system modules is realized; the interface module is used for carrying out data communication with external equipment according to the first communication information and acquiring second communication information from the external equipment; and the monitoring and configuration module is used for customized development and debugging, and part of functions can be designed redundantly in consideration of the requirement of generalization. Through the module, the design steps of the FPGA can be simplified, when different accelerating platforms are built, the accelerating logic module is often designed only again, other modules can not be redesigned, transplantation and multiplexing of each module on different accelerating platforms are guaranteed to a great extent, and the efficiency of building the accelerating platforms is improved.
Example two:
the embodiment of the application also provides an FPGA system for building the acceleration platform, which is specifically described below by combining the attached drawings.
Referring to fig. 2, the figure is a schematic diagram of another FPGA system for building an acceleration platform according to the second embodiment of the present application.
The system 200 according to the embodiment of the present application includes various modules of the system according to the First embodiment, wherein a First Input First Output (FIFO) memory 201 is integrated in the routing module 103. In addition, the interface module 104 specifically includes: a high-speed serial interface 202, a memory controller 203, and a host interface 204.
The FIFO memory 201 is configured to perform buffering and flow control on the first communication information and the second communication information.
In the FIFO memory 201, the communication information is arranged into a queue, the communication information of the first-in routing module 103 is processed and retired first, and then the processed communication information enters, and when the routing module 103 is not in time to process all the communication information for a certain period of time, the unprocessed communication information is arranged into the first-in first-out queue of the FIFO memory 201 to wait for processing. Examples are as follows:
when the routing module 103 finishes processing the No. 0 communication information, the No. 1 communication information will take over the position of the No. 0 communication information, and the No. 2 communication information and the No. 3 communication information will take over the position of the previous communication information.
It should be noted that the FIFO memory 201 may divide storage spaces with different sizes according to actual application scenarios to perform buffering and flow control on the first communication information and the second communication information respectively; the FIFO memory 201 may also perform caching and flow control after uniformly combining the received first communication information and the second communication information; the FIFO memory 201 may also perform buffering and flow control after sequencing the received first communication information and the second communication information according to different priorities required by an actual application scenario, and the FIFO memory 201 may also perform buffering and flow control by using other rules, which is not specifically limited in this application.
The routing module 103 stops receiving the first communication information and the second communication information when the storage space of the FIFO memory 201 is exhausted.
It should be noted that the routing module defines the width of each interface of the interface module 104 in a macro definition.
The high-speed serial interface 202 has low transmission noise and high information transmission speed.
The memory controller 203 is connected with the acceleration logic module 101; the memory controller 203 is configured to perform data exchange between the acceleration logic 101 and a storage device.
The memory controller 203 is configured to control the memory and enable the storage device to exchange data with the acceleration logic module 101. The memory controller 203 determines the maximum memory capacity, the number of memory BANKs, the memory type and speed, the memory granularity data depth and the data width, etc. of the acceleration logic 101, i.e. determines the memory performance of the acceleration logic 101.
The host interface 204 is used for connecting a master device. The host interface 204 enables the FPGA system to be accessed by processors of other main control devices, and the FPGA system can conveniently receive control information downloaded by the main control devices and upload processing results through the host interface 204.
Optionally, the host interface 204 may be connected to the Memory controller 203 through a DMA (Direct Memory Access) device to obtain the allocated Memory.
According to the FPGA system for building the acceleration platform, the routing module is integrated with the FIFO memory. In addition, its interface module still includes: a high-speed serial interface, a memory controller and a host interface. The routing module can transmit the communication information by sending the first communication information to each interface of the interface module or receiving the second communication information sent by each interface of the interface module, and meanwhile, in the transmission process of the communication information, the FIFO memory is used for caching and controlling the flow of the communication information, so that the efficiency of the routing module for processing the communication information is improved.
Example three:
based on the FPGA system for building an acceleration platform provided by the above embodiment, the embodiment of the present application further provides an FPGA device for building an acceleration platform, which is specifically described below with reference to the accompanying drawings.
Referring to fig. 3, the figure is a schematic diagram of an FPGA device for building an acceleration platform according to a third embodiment of the present application.
The apparatus 300 comprises: a peripheral interface layer 301, a core acceleration layer 302, and a storage device 303;
the peripheral interface layer 301, including the routing module 103, the interface module 104, and the detection and configuration module 105;
the core acceleration layer 302, which includes the acceleration logic module 101 and the controller 102;
the storage device 303 is configured to store data of the acceleration logic module 101.
The FPGA equipment for building the acceleration platform provided by the embodiment of the application divides FPGA logic into two layers: a peripheral interface layer and 301 a core acceleration layer 302. When the method is applied to different acceleration scenes, the peripheral interface layer 301 basically does not need to be changed or replaced by taking the module IP as a unit, and the time for building different platforms is fully reduced. The routing module 101 of the core acceleration layer 302 may also have a logic design that does not need to be changed, and only the acceleration logic module 101 needs to be developed for an application scenario.
By utilizing the equipment provided by the embodiment of the application, the design steps of the FPGA can be simplified, the transportability of each module on different acceleration platforms is increased, and the efficiency of building the acceleration platforms is improved.
Example four:
based on the FPGA system for building the acceleration platform provided by the above embodiment, the embodiment of the present application further provides an acceleration platform, which is specifically described below with reference to the accompanying drawings.
Referring to fig. 4, the figure is a schematic view of an acceleration platform provided in the fourth embodiment of the present application.
The acceleration platform 400 further comprises: a master control device 401;
the main control device 401 is configured to implement access to the acceleration logic module 101 through the host interface 204.
The acceleration platform provided in the embodiment of the present application utilizes the host interface 204 to connect with the master control device 401. The host interface 204 enables the FPGA system to be accessed by processors of other main control devices, and through the host interface 204, the acceleration logic module 101 can conveniently receive control information downloaded by the main control device 401 and upload a processing result.
It should be understood that in the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" for describing an association relationship of associated objects, indicating that there may be three relationships, e.g., "a and/or B" may indicate: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (9)
1. An FPGA system for building an acceleration platform, the system comprising: the system comprises an acceleration logic module, a controller, a routing module, an interface module and a monitoring and configuration module;
the acceleration logic module is used for executing an acceleration algorithm, processing input information and sending output information to the controller;
the controller is used for converting the output information into first communication information and sending the first communication information to the routing module, and is also used for converting second communication information sent by the routing module into input information and sending the input information to the acceleration logic module; the controller can realize the conversion of the general data types;
the routing module is configured to send the first communication information to the interface module, and is further configured to send the second communication information sent by the interface module to the controller; the routing module applies a general routing protocol;
the interface module is used for carrying out data communication with external equipment according to the first communication information and acquiring the second communication information from the external equipment; the interface module corresponds to a universal interface protocol and an interface architecture;
the monitoring and configuration module is used for customized development and debugging;
an FIFO memory is integrated in the routing module;
and the FIFO memory is used for carrying out buffering and flow control on the first communication information and the second communication information, and when the routing module cannot process all the communication information, unprocessed communication information is arranged in a first-in first-out queue arranged in the FIFO memory to wait for processing.
2. The system of claim 1, wherein the routing module stops receiving the first communication and the second communication when the storage space of the FIFO memory is exhausted.
3. The system of claim 1, wherein the routing module defines the width of each interface of the interface module in a macro definition.
4. The system of claim 1, wherein the interface module comprises: a high speed serial interface.
5. The system of claim 1, wherein the interface module further comprises: a memory controller.
6. The system of claim 5, wherein the memory controller is coupled to the acceleration logic module; the memory controller is used for carrying out data exchange between the acceleration logic module and the storage device.
7. The system of claim 1, wherein the interface module further comprises: a host interface; the host interface is used for connecting the main control equipment.
8. An apparatus for building an acceleration platform, the apparatus comprising: a peripheral interface layer, a core acceleration layer and a storage device;
the peripheral interface layer comprising the routing module of any one of claims 1-7, the interface module of any one of claims 1-7, and the monitoring and configuration module of any one of claims 1-7;
the core acceleration layer comprising the acceleration logic module of any one of claims 1-7 and the controller of any one of claims 1-7;
the storage device is used for storing the data of the acceleration logic module.
9. An acceleration platform built from the FPGA system building acceleration platform of any one of claims 1 to 7, further comprising: a master control device;
the main control device is used for accessing the acceleration logic module.
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| CN108319563A (en) * | 2018-01-08 | 2018-07-24 | 华中科技大学 | A kind of network function acceleration method and system based on FPGA |
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| JP2004157986A (en) * | 2002-10-17 | 2004-06-03 | Renesas Technology Corp | Logical verification system and fpga module |
| US20120265515A1 (en) * | 2011-04-12 | 2012-10-18 | Reuven Weintraub | Method and system and computer program product for accelerating simulations |
| CN104657330A (en) * | 2015-03-05 | 2015-05-27 | 浪潮电子信息产业股份有限公司 | High-performance heterogeneous computing platform based on x86 architecture processor and FPGA (Field Programmable Gate Array) |
| CN107766286A (en) * | 2017-09-28 | 2018-03-06 | 浙江大学 | A kind of Systemon-board implementation method based on FPGA |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106528490A (en) * | 2016-11-30 | 2017-03-22 | 郑州云海信息技术有限公司 | FPGA (Field Programmable Gate Array) heterogeneous accelerated computing device and system |
| CN107423030A (en) * | 2017-07-28 | 2017-12-01 | 郑州云海信息技术有限公司 | Markov Monte carlo algorithm accelerated method based on FPGA heterogeneous platforms |
| CN108319563A (en) * | 2018-01-08 | 2018-07-24 | 华中科技大学 | A kind of network function acceleration method and system based on FPGA |
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