CN109240978A - It is a kind of to build the FPGA system for accelerating platform, equipment and accelerate platform - Google Patents
It is a kind of to build the FPGA system for accelerating platform, equipment and accelerate platform Download PDFInfo
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- CN109240978A CN109240978A CN201811109151.5A CN201811109151A CN109240978A CN 109240978 A CN109240978 A CN 109240978A CN 201811109151 A CN201811109151 A CN 201811109151A CN 109240978 A CN109240978 A CN 109240978A
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
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Abstract
The FPGA system for accelerating platform, equipment and acceleration platform are built this application provides a kind of, which includes: acceleration logic module, controller, routing module, interface module and monitoring and configuration module；Acceleration logic module, for executing accelerating algorithm, processing input information and sending output information to controller；Controller is sent to routing module for output information to be converted to first communication information, and second communication information that routing module is sent is converted to input information and is sent to acceleration logic module；Routing module for sending interface module for first communication information, and sends controller for second communication information that interface module is sent；Interface module for carrying out data communication according to first communication information and external equipment, and obtains second communication information from external equipment；Monitoring and configuration module melt hair and debugging for being customized.The efficiency that hardware-accelerated platform is built using FPGA can be improved using the system.
Description
Technical field
The present invention relates to FPGA design field more particularly to a kind of FPGA system, device and acceleration for building acceleration platform
Platform.
Background technique
With the continuous development and evolution of algorithm, tradition has been encountered in performance using the mode that CPU is calculated
Bottleneck, and obtained using the calculation that FPGA, GPU and the asic chip of customization are application acceleration more and more extensive
Using.FPGA (Field-Programmable Gate Array, field programmable gate array) and customization AISC chip
Accelerated mode is compared, and has extraordinary reusability, is suitable for application scenarios more abundant, from the period for being designed into application
Also it can substantially reduce.Compared with GPU, FPGA can carry out the design of some customization for concrete application, to obtain better
The optimization space of performance and power consumption.
In existing FPGA design process, top-down design philosophy that is most of or using standard.I.e. from being
Irrespective of size design starts, and is several secondary units the function division to be realized, then each secondary unit is divided into down again
The basic unit of one level so divides, until being able to use basic module or IP kernel is directly realized by always.But
Accelerate the FPGA on platform for be clearly applied to certain, development process can be made using general top-down design flow
It complicates, because being applied to the FPGA accelerated on platform, function substantially is fixed, primary difference is that being core
The realization of accelerating algorithm.And top-down design flow is used, it is core accelerating algorithm as a subfunction, and own
Subfunction is decomposed step by step together, not only increases the workload of design, and is unfavorable for the different shiftings for accelerating platform FPGA design
It plants.
Summary of the invention
In order to solve above-mentioned technical problem of the existing technology, this application provides a kind of FPGA for building acceleration platform
System, equipment and acceleration platform, can shorten the time for building hardware-accelerated platform using FPGA, improve the efficiency built.
This application provides a kind of build to accelerate the FPGA system of platform, and the system comprises: acceleration logic modules, control
Device, routing module, interface module and monitoring and configuration module；
The acceleration logic module, for executing accelerating algorithm, processing input information and sending output to the controller
Information；
The controller is sent to the routing module for the output information to be converted to first communication information, also
Second communication information for sending the routing module is converted to input information and is sent to the acceleration logic module；It is described
Controller is able to achieve the conversion to general data type
The routing module is also used to connect described for sending the interface module for first communication information
Second communication information that mouth mold block is sent is sent to the controller；The routing module applies general Routing Protocol；
The interface module, for carrying out data communication according to first communication information and external equipment, and from described
External equipment obtains second communication information；The interface module corresponds to general interface protocol and interface architecture；
The monitoring and configuration module melt hair and debugging for being customized.
Optionally, FIFO memory is integrated in the routing module；
The FIFO memory, for carrying out caching and flow to first communication information and second communication information
Control.
Optionally, the routing module stops receiving described first when the memory space of the FIFO memory is used up
The communication information and second communication information.
Optionally, the routing module is macrodefinition to the definition mode of each interface width of the interface module.
Optionally, the interface module includes: HSSI High-Speed Serial Interface.
Optionally, the interface module further include: Memory Controller Hub.
Optionally, the Memory Controller Hub is connect with the acceleration logic module；The Memory Controller Hub is for carrying out institute
It states acceleration logic module and stores the data exchange between equipment.
Optionally, the interface module further include: host interface；
The host interface is for connecting main control device.
The embodiment of the present application also provides a kind of devices for building acceleration platform, and the equipment includes: peripheral interface layer, core
Cadion-acceleration layer and storage equipment；
The peripheral interface layer, including the routing module, the interface module and the detection and configuration module；
The core acceleration layer, including the acceleration logic module and the controller；
The storage equipment, for storing the data of the acceleration logic module.
It is described that platform is accelerated to accelerate platform by described building the embodiment of the present application also provides a kind of acceleration platform
FPGA system is built, the acceleration platform further include: main control device；
The main control device, for accessing the acceleration logic module.
Compared with prior art, the present invention has at least the following advantages:
It is provided by the invention build accelerate platform FPGA system, comprising: acceleration logic module, controller, routing module,
Interface module and monitoring and configuration module；Wherein acceleration logic module, for executing accelerating algorithm, processing input information and to control
Device processed sends output information, is the nucleus module for realizing accelerating algorithm；Controller, for output information to be converted to the first communication
Information is sent to routing module, be also used to by routing module send second communication information be converted to input information be sent to acceleration
Logic module, the treatment process realize acceleration logic module and input, between output information and the external module communication information
Conversion；Routing module, for sending interface module for first communication information, be also used to send interface module second is led to
Letter information is sent to controller, realizes the data communication between the system module；Interface module, according to first communication information
Data communication is carried out with external equipment, and obtains second communication information from external equipment；Monitoring and configuration module, for being determined
Inhibition and generation exploitation and debugging.Using the present invention, the design procedure of FPGA can simplify, when building different acceleration platforms, often
It only needs again to be designed acceleration logic module, and other modules can largely guarantee without redesigning
Transplanting and multiplexing of the modules on different acceleration platforms, improve the efficiency built and accelerate platform.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The some embodiments recorded in application, for those of ordinary skill in the art, without creative efforts,
It can also be obtained according to these attached drawings other attached drawings.
Fig. 1 is a kind of schematic diagram for FPGA system for building acceleration platform that the embodiment of the present application one provides；
Fig. 2 is that the another kind that the embodiment of the present application two provides builds the schematic diagram for accelerating the FPGA system of platform；
Fig. 3 is a kind of schematic diagram for FPGA device for building acceleration platform that the embodiment of the present application three provides；
Fig. 4 is a kind of schematic diagram for acceleration platform that the embodiment of the present application four provides.
Specific embodiment
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only this
Invention a part of the embodiment, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art exist
Every other embodiment obtained under the premise of creative work is not made, shall fall within the protection scope of the present invention.
Embodiment one:
The embodiment of the present application provides a kind of FPGA system built and accelerate platform, illustrates with reference to the accompanying drawing.
Referring to Fig. 1, which is a kind of schematic diagram for FPGA system for building acceleration platform that the embodiment of the present application one provides.
System 100 described in the embodiment of the present application includes: acceleration logic module 101, controller 102, routing module 103, connects
Mouth mold block 104 and monitoring and configuration module 105；
The acceleration logic module 101, for executing accelerating algorithm, processing input information and being sent out to the controller 102
Send output information.
What acceleration logic module 101 included is the logic realization of accelerating algorithm used in practical application scene, this part
Logic realize and realize by the way of logic computing unit as small as possible using constructing that the calculating task for accelerating one is divided
The calculating that solution is several grades, every grade of calculating are made of several small computing units, calculate stream treatment between grade, it is easier to add
Fast logic module 101 carries out performance and evaluates and optimizes, while the design of small logic computing unit and whole pipelining-stage, in difference
It may be implemented significantly to be multiplexed under application scenarios.
The controller 102 is sent to the routing module for the output information to be converted to first communication information
103, it is also used to be converted to second communication information that the routing module 103 is sent input information and is sent to the acceleration logic
Module 101, in addition, the controller 102 is able to achieve the conversion to general data type.
First communication information includes that the acceleration logic module 101 needs after realizing accelerating algorithm to other moulds
The information of block or external equipment being called, second communication information include that other modules or external equipment patrol acceleration
The relevant information of the feedback of volume 101 recalls information of module and his module or the operating condition of external equipment.
The routing module 103, for sending the interface module 104 for first communication information, be also used to by
Second communication information that the interface module 104 is sent is sent to the controller 103.
Routing module 103 can safeguard the data communication inside the FPGA system between modules, of the invention
Under framework, routing module 103 applies general Routing Protocol, it can using fixed routing rule, general Routing Protocol
It may include that agreement has RIP (Route Information Protocol, routing information protocol), OSPF (Open Shortest
Path First, ospf), IS-IS (Intermediate system to intermediate
System, intermediate system build system in), BGP (Border Gateway Protocol, Border Gateway Protocol) etc., the application
It is not specifically limited in this embodiment.
Under different application scenarios, with the difference for using interface IP in interface module 104, routing module 103 with connect
The data width of the access of interface can be also varied in mouth mold block 104, right in the design of routing module for this point
The definition of each interface width can be by the way of macrodefinition in interface module 104, the value of macrodefinition and corresponding interface
Unanimously, the macrodefinition is a kind of appellation of batch processing, can be carried out, be illustrated such as according to a series of predefined rules
Under:
When in interface module 104 including Memory Controller Hub, routing module 103 and the interface of the access of Memory Controller Hub are wide
Degree, can be defined with the macrodefinition of memory controller interface width, and when in interface module 104 including host interface, road
By the interface width of module 103 and the access of Memory Controller Hub, it can be defined with the macrodefinition of host interface width, be existed at this time
It does not need to complete interface data width one of the replacement of mode to guarantee with actually connect under the premise of modification routing module code
It causes.
The interface module 104, for carrying out data communication according to first communication information and external equipment, and from institute
It states external equipment and obtains second communication information, the interface module corresponds to general interface protocol and interface architecture.
The monitoring and configuration module 105, melt hair and debugging for being customized, can during exploitation is with debugging
To consider general-purpose demand as much as possible, it might even be possible to which the functional redundancy of holding part, i.e., some functions are certain specific
It is just useful under application scenarios, it is not activated when being used for scene in other.Redundancy Design in this way can reduce described
The change that system carries out under different application scenarios increases the portability of the system.
It is provided by the embodiments of the present application to build the FPGA system for accelerating platform, acceleration logic module therein, for executing
Accelerating algorithm, processing input information simultaneously send output information to controller, are the nucleus modules for realizing accelerating algorithm；Controller,
It is sent to routing module for output information to be converted to first communication information, the second communication for being also used to send routing module
Information is converted to input information and is sent to acceleration logic module, the treatment process realize acceleration logic module and input, defeated
Conversion between information and the external module communication information out；Routing module, for sending interface module for first communication information,
It is also used to send controller for second communication information that interface module is sent, the data realized between the system module are logical
Letter；Interface module carries out data communication according to first communication information and external equipment, and obtains the second communication letter from external equipment
Breath；Monitoring and configuration module melt hair and debugging for being customized, consider unitized requirement, partial function wherein
Have Redundancy Design.By above-mentioned module, the design procedure of FPGA can simplify, when building different acceleration platforms, often
It only needs again to be designed acceleration logic module, and other modules can largely guarantee without redesigning
Transplanting and multiplexing of the modules on different acceleration platforms, improve the efficiency built and accelerate platform.
Embodiment two:
The embodiment of the present application also provides a kind of FPGA systems for building acceleration platform, illustrate with reference to the accompanying drawing.
Referring to fig. 2, which is that the another kind that the embodiment of the present application two provides builds the signal for accelerating the FPGA system of platform
Figure.
System 200 described in the embodiment of the present application includes the modules of system described in embodiment one, routing module therein
FIFO (First Input First Output, first in first out) memory 201 is integrated in 103.In addition, interface mould therein
Block 104 is specific further include: HSSI High-Speed Serial Interface 202, Memory Controller Hub 203 and host interface 204.
The FIFO memory 201, for first communication information and second communication information carry out caching with
Flow control.
In the FIFO memory 201, the queue that the communication information is lined up is introduced into the communication letter of routing module 103
Breath is first handled and is retired from office, the communication information entered after and then just handling, when routing module 103 has little time to locate in a certain period
When managing all communication informations, the untreated communication information will be arranged at the first in, first out team that FIFO memory 201 is lined up
It arranges medium to be processed.It is illustrated below:
The 0 advanced enqueue of signal communication information from a certain moment is logical followed by 1 signal communication information, 2 signal communication information and No. 3
Letter information, routing module 103 can first carry out the processing to 0 signal communication information, remaining communication information wait in the queue it is processed,
After routing module 103 completes the processing to 0 signal communication information, 1 signal communication information will take over the position of 0 signal communication information,
Same 2 signal communication information, 3 signal communication information can take over the position of previous signal communication information.
It should be noted that the FIFO memory 201 can mark off different size of storage according to practical application scene
It deposits space and caching and flow control is carried out to first communication information and second communication information respectively；The FIFO storage
Device 201 is cached and is flowed after first communication information received and second communication information can also being integrated
Amount control；The FIFO memory 201 can also by first communication information received and second communication information by
The different priorities required according to practical application scene carry out carrying out caching and flow control, the FIFO memory after successively sorting
201 can also using other rules carry out caching and flow control, the application be not specifically limited in this embodiment.
It is logical to stop reception described first when the memory space of the FIFO memory 201 is used up for the routing module 103
Letter information and second communication information.
It should be noted that the routing module is to the definition mode of each interface width of the interface module 104
Macrodefinition.
The transmitted noise of the HSSI High-Speed Serial Interface 202 is small, and the speed for transmitting information is fast.
The Memory Controller Hub 203 is connect with the acceleration logic module 101；The Memory Controller Hub 203 is for carrying out
Data exchange between the acceleration logic module 101 and storage equipment.
The Memory Controller Hub 203 is carried out for controlling memory and making to store between equipment and acceleration logic module 101
The exchange of data.Memory Controller Hub 203 determines maximum memory capacity, the memory BANK that acceleration logic module 101 can use
The important parameters such as several, type of memory and speed, memory grain data depth and data width, that is, determine acceleration logic module
101 internal memory performance.
The host interface 204 is for connecting main control device.Host interface 204 can enable the FPGA system by other
The processor of main control device accesses, and by host interface 204, the FPGA system can easily receive what main control device passed down
Control information and upload process result.
Optionally, the host interface 204 can pass through DMA (Direct Memory Access, direct memory access)
Equipment is connected to obtain the memory of distribution with the Memory Controller Hub 203.
Provided by the embodiments of the present application to build the FPGA system for accelerating platform, routing module is integrated with FIFO memory.
In addition, its interface module further include: HSSI High-Speed Serial Interface, Memory Controller Hub and host interface.The routing module can pass through
First communication information is sent to each interface of interface module or is received described in each interface transmission of the interface module
Second communication information completes the transmission of the communication information, at the same time in communication information transmission process, using FIFO memory to logical
Letter information carries out caching and flow control, improves the efficiency of the routing module processing communication information.
Embodiment three:
What is provided based on the above embodiment builds the FPGA system for accelerating platform, and the embodiment of the present application also provides one kind to take
The FPGA device for accelerating platform is built, is illustrated with reference to the accompanying drawing.
Referring to Fig. 3, which is a kind of schematic diagram for FPGA device for building acceleration platform that the embodiment of the present application three provides.
The equipment 300 includes: peripheral interface layer 301, core acceleration layer 302 and storage equipment 303；
The peripheral interface layer 301, including the routing module 103, the interface module 104 and the detection and configuration
Module 105；
The core acceleration layer 302, including the acceleration logic module 101 and the controller 102；
The storage equipment 303, for storing the data of the acceleration logic module 101.
It is provided by the embodiments of the present application to build the FPGA device for accelerating platform, fpga logic is divided into two layers: peripheral interface
Layer and 301 core acceleration layers 302.Wherein, be applied to different acceleration scenes, peripheral interface layer 301 do not need substantially change or
Person is replaced as unit of module I P, substantially reduces the used time for building different platform.The routing module of core acceleration layer 302
101 can also have the logical design for not needing change, and only acceleration logic module 101 needs to be developed for application scenarios.
Using above equipment provided by the embodiments of the present application, the design procedure of FPGA can simplify, increase modules and exist
Difference accelerates the portability on platform, improves the efficiency built and accelerate platform.
Example IV:
What is provided based on the above embodiment builds the FPGA system for accelerating platform, and the embodiment of the present application also provides one kind to add
Fast platform, illustrates with reference to the accompanying drawing.
Referring to fig. 4, which is a kind of schematic diagram for acceleration platform that the embodiment of the present application four provides.
The acceleration platform 400 further include: main control device 401；
The main control device 401 accesses the acceleration logic module 101 for realizing by host interface 204.
Acceleration platform provided by the embodiments of the present application connects the main control device 401 using the host interface 204.It is main
Machine interface 204 can enable the FPGA system be accessed by the processor of other main control devices, described by host interface 204
Acceleration logic module 101 can easily receive the control information that main control device 401 passes down and upload process result.
It should be appreciated that in this application, " at least one (item) " refers to one or more, and " multiple " refer to two or two
More than a."and/or" indicates may exist three kinds of relationships, for example, " A and/or B " for describing the incidence relation of affiliated partner
It can indicate: only exist A, only exist B and exist simultaneously tri- kinds of situations of A and B, wherein A, B can be odd number or plural number.Word
Symbol "/" typicallys represent the relationship that forward-backward correlation object is a kind of "or"." at least one of following (a) " or its similar expression, refers to
Any combination in these, any combination including individual event (a) or complex item (a).At least one of for example, in a, b or c
(a) can indicate: a, b, c, " a and b ", " a and c ", " b and c ", or " a and b and c ", and wherein a, b, c can be individually, can also
To be multiple.
The above described is only a preferred embodiment of the present invention, being not intended to limit the present invention in any form.Though
So the present invention has been disclosed as a preferred embodiment, and however, it is not intended to limit the invention.It is any to be familiar with those skilled in the art
Member, without departing from the scope of the technical proposal of the invention, all using the methods and technical content of the disclosure above to the present invention
Technical solution makes many possible changes and modifications or equivalent example modified to equivalent change.Therefore, it is all without departing from
The content of technical solution of the present invention, according to the technical essence of the invention any simple modification made to the above embodiment, equivalent
Variation and modification, all of which are still within the scope of protection of the technical scheme of the invention.
Claims (10)
1. a kind of build the FPGA system for accelerating platform, which is characterized in that the system comprises: acceleration logic module, controller,
Routing module, interface module and monitoring and configuration module；
The acceleration logic module, for executing accelerating algorithm, processing input information and sending output information to the controller；
The controller is sent to the routing module for the output information to be converted to first communication information, is also used to
Second communication information that the routing module is sent is converted to input information and is sent to the acceleration logic module；The control
Device is able to achieve the conversion to general data type；
The routing module is also used to for sending the interface module for first communication information by the interface mould
Second communication information that block is sent is sent to the controller；The routing module applies general Routing Protocol；
The interface module, for carrying out data communication according to first communication information and external equipment, and from the outside
Equipment obtains second communication information；The interface module corresponds to general interface protocol and interface architecture；
The monitoring and configuration module melt hair and debugging for being customized.
2. system according to claim 1, which is characterized in that be integrated with FIFO memory in the routing module；
The FIFO memory, for carrying out caching and flow control to first communication information and second communication information
System.
3. system according to claim 2, which is characterized in that the routing module is empty in the storage of the FIFO memory
Between when using up, stop receiving first communication information and second communication information.
4. system according to claim 1, which is characterized in that each interface of the routing module to the interface module
The definition mode of width is macrodefinition.
5. system according to claim 1, which is characterized in that the interface module includes: HSSI High-Speed Serial Interface.
6. system according to claim 1, which is characterized in that the interface module further include: Memory Controller Hub.
7. system according to claim 6, which is characterized in that the Memory Controller Hub and the acceleration logic module connect
It connects；The Memory Controller Hub is used to carry out the acceleration logic module and stores the data exchange between equipment.
8. system according to claim 1, which is characterized in that the interface module further include: host interface；
The host interface is for connecting main control device.
9. it is a kind of build accelerate platform device, which is characterized in that the equipment include: peripheral interface layer, core acceleration layer and
Store equipment；
The peripheral interface layer, including the routing module, the interface module and the detection and configuration module；
The core acceleration layer, including the acceleration logic module and the controller；
The storage equipment, for storing the data of the acceleration logic module.
10. a kind of acceleration platform, which is characterized in that the acceleration platform builds acceleration by claim 1-8 is described in any item
The FPGA system of platform is built, the acceleration platform further include: main control device；
The main control device, for accessing the acceleration logic module.
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