CN109216312A - 半导体组件 - Google Patents
半导体组件 Download PDFInfo
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- CN109216312A CN109216312A CN201810673212.4A CN201810673212A CN109216312A CN 109216312 A CN109216312 A CN 109216312A CN 201810673212 A CN201810673212 A CN 201810673212A CN 109216312 A CN109216312 A CN 109216312A
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- 230000002093 peripheral effect Effects 0.000 claims abstract description 55
- 239000004020 conductor Substances 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 description 22
- 229910052751 metal Inorganic materials 0.000 description 22
- 238000005516 engineering process Methods 0.000 description 12
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 238000010586 diagram Methods 0.000 description 2
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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Abstract
一种半导体组件,具有:半导体基板;第一电极,所述第一电极在所述半导体基板的第一表面的除外周区域以外的范围内接合到所述第一表面上;第二电极,所述第二电极接合到作为所述第一表面的相反侧的所述半导体基板的表面的第二表面上;第一导电体,所述第一导电体经由第一焊料层连接于所述第一电极;以及第二导电体,所述第二导电体经由第二焊料层连接于所述第二电极。当沿着所述半导体基板的厚度方向观察时,所述第二电极与整个所述第一电极重叠,并且,比所述第一电极宽。在所述第二导电体的接合于所述第二焊料层的接合面上设置有凹部,所述凹部以当沿着厚度方向观察所述半导体基板时与所述第一电极的外周缘重叠的方式沿着所述外周缘配置。
Description
技术领域
本说明书公开的技术涉及半导体组件。
背景技术
在日本特开2016-046497中公开了一种半导体组件,所述半导体组件具有导电体通过钎焊被接合于半导体芯片的两个面的结构。图18放大地表示出日本特开2016-046497的半导体组件的一部分。如图18所示,半导体组件160具有半导体基板150、接合于半导体基板150的一个表面150a上的第一电极110、以及接合于半导体基板150的另一个表面150b上的第二电极120。第一电极110被焊料层112接合于第一导电体114,第二电极120被焊料层122接合于第二导电体124。第一导电体114和第二导电体124分别起着作为从半导体基板150放热的散热构件的作用。
发明内容
由于在半导体基板150的一个表面150a设置除第一电极110以外的其它电极(例如,信号电极等),因此,第一电极110的尺寸比第二电极120的尺寸小。在半导体基板150发热时,第一导电体114、第二导电体124及半导体基板150分别热膨胀。这时,由于第一导电体114的线膨胀系数和第二导电体124的线膨胀系数比半导体基板150的线膨胀系数大,因此,第一导电体114的膨胀量和第二导电体124的膨胀量变得比半导体基板150的膨胀量大。通过第一导电体114的热膨胀,焊料层112被向外周侧拉伸。通过第二导电体124的热膨胀,焊料层122被向外周侧拉伸。通过半导体基板150反复发热,向焊料层112、122反复施加应力。这样,由于焊料的蠕变现象,如图18的箭头所示,在焊料层112的内部,焊料向外周侧移动,在焊料层122的内部,焊料向外周侧移动。当焊料的蠕变现象进一步进行时,如图19的箭头190所示,在焊料层112的内部向外周侧移动的焊料,在第一电极110的外周缘110a附近对半导体基板150向下方加压。其结果是,如图19所示,半导体基板150在第一电极110的外周缘110a处向下方翘曲。通过被向下方翘曲的半导体基板150加压,焊料层122内的焊料从被加压的部分向周围移动。其结果是,如图19的箭头192所示,焊料层122内的焊料的一部分向第一电极110的中央部的下部移动。因此,在第一电极110的中央部的位置,焊料层122对半导体基板150向上方加压,半导体基板150向上方翘曲。由于在半导体基板150上产生如图19所示的翘曲,半导体基板150恶化。由于上述原因,半导体组件的可靠性降低。在图18、19中,半导体芯片160被绝缘树脂覆盖,但是,已经确认了即使在半导体芯片不被绝缘树脂覆盖的情况下,也产生与图19同样的翘曲。从而,在本说明书中,提出了在半导体组件中抑制由焊料的蠕变现象引起的半导体基板的翘曲的技术。
根据本公开的方式的半导体组件具有:半导体基板;第一电极,所述第一电极在所述半导体基板的第一表面的除外周区域以外的范围内接合到所述第一表面上;第二电极,所述第二电极接合到作为所述第一表面的相反侧的所述半导体基板的表面的第二表面上;第一导电体,所述第一导电体经由第一焊料层连接于所述第一电极;以及第二导电体,所述第二导电体经由第二焊料层连接于所述第二电极。当沿着所述半导体基板的厚度方向观察时,所述第二电极与整个所述第一电极重叠,并且,比所述第一电极宽。在所述第二导电体的接合于所述第二焊料层的接合面上设置有凹部,所述凹部以当沿着厚度方向观察所述半导体基板时与所述第一电极的外周缘重叠的方式沿着所述外周缘配置。
在所述半导体组件中,在第二导电体的接合于第二焊料层的接合面上设置有凹部,所述凹部以当沿着厚度方向观察所述半导体基板时与第一电极的外周缘重叠的方式沿着所述外周缘配置。由于凹部内的第二焊料层(即,第一电极的外周缘的下部的第二焊料层)厚,因此,凹部内的第二焊料层相对地具有高的弹性。因此,即使因第一焊料层的蠕变现象而使得在第一电极的外周缘的下部,半导体基板被向下方加压,在凹部的内部的第二焊料层中也不易产生蠕变现象。因此,不易产生由第二焊料层的蠕变现象引起的对半导体基板的压力,能够抑制半导体基板的翘曲。从而,在根据本公开的形式的半导体组件中,不易发生半导体基板的随着时间的劣化。
附图说明
下面,将参照附图描述本发明的示范性的实施方式的特征、优点、技术和工业上的意义,在附图中,类似的附图标记表示类似的部件,其中:
图1是半导体组件的剖视图。
图2是半导体芯片及其周边的放大剖视图。
图3是从上侧观察半导体芯片的俯视图。
图4是凹部和凸部的立体图。
图5是凹部和凸部的形成工序的说明图。
图6是凹部和凸部的形成工序的说明图。
图7是变形例的半导体组件的对应于图2的放大剖视图。
图8是变形例的半导体组件的对应于图2的放大剖视图。
图9是变形例的半导体组件的对应于图2的放大剖视图。
图10是变形例的半导体组件的对应于图2的放大剖视图。
图11是变形例的半导体组件的对应于图1的剖视图。
图12是变形例的半导体组件的对应于图1的剖视图。
图13是变形例的半导体组件的对应于图1的剖视图。
图14是变形例的半导体组件的对应于图1的剖视图。
图15是变形例的半导体组件的对应于图3的俯视图。
图16是变形例的半导体组件的对应于图3的剖视图。
图17是变形例的半导体组件的对应于图3的剖视图。
图18是相关技术的半导体组件的半导体芯片及其周边的放大剖视图。
图19是相关技术的半导体组件的半导体芯片及其周边的放大剖视图。
具体实施方式
如图1所示,实施方式的半导体组件10具有:上部引线框12、金属块16、半导体芯片20、下部引线框24以及绝缘树脂26。
如图2所示,半导体芯片20具有SiC基板30、上部电极32和下部电极34。上部电极32接合于SiC基板30的上表面30a。图3表示从上侧观察半导体芯片20的俯视图。如图3所示,上部电极32覆盖SiC基板30的上表面30a的中央部,不覆盖上表面30a的外周部。尽管图中未示出,但在上表面30a的外周部的一部分上设置有信号电极。信号电极由导线连接于图中未示出的信号端子。如图2所示,下部电极34覆盖SiC基板30的下表面30b的全部区域。从而,如图3所示,在沿着SiC基板30的厚度方向观察时,下部电极34(即,在图3中与SiC基板30相同尺寸的范围)与整个上部电极32重叠,并且,比上部电极32宽。在SIC基板30的内部,形成大电流控制用的MOSFET(金属氧化物半导体场效应晶体管)或者二极管等半导体元件。
金属块16由金属(更详细地说,铜)构成。如图1、2所示,金属块16被配置于半导体芯片20的上部。金属块16的下表面由第一焊料层18连接于半导体芯片20的上部电极32。
上部引线框12由金属(更详细地说,铜)构成。如图1所示,上部引线框12被配置于金属块16的上部。上部引线框12的下表面由焊料层14连接于金属块16的上表面。
下部引线框24由金属(更详细地说,铜)构成。如图1、2所示,下部引线框24被配置于半导体芯片20的下部。下部引线框24的上表面24a由第二焊料层22连接于半导体芯片20的下部电极34。在下部引线框24的上表面24a,设置有凹部40和凸部42。如图3、4所示,凹部40在上表面24a中包围凸部42。在图3中,用斜线表示设置有凹部40的范围。如图3所示,在沿着SiC基板30的厚度方向观察时,上部电极32的整个外周缘32a与凹部40重叠。凸部42设置在被凹部40包围的范围内。如图2、4所示,凸部42比凹部40的外周侧的上表面24a向上侧突出。凹部40和凸部42全部被第二焊料层22覆盖。第二焊料层22与凸部42的表面、凹部40的内面以及凹部40的外周侧的上表面24a(凹部40附近的上表面24a)接合。
如图1所示,上部引线框12、金属块16、半导体芯片20以及下部引线框24的叠层体被绝缘树脂26覆盖。除上部引线框12的上表面和下部引线框24的下表面以外的叠层体的整个表面被绝缘树脂26覆盖。上部引线框12的上表面和下部引线框24的下表面与图中未示出的冷却器连接。
上部引线框12和下部引线框24起着作为半导体组件10的配线的作用。电流能够经由上部引线框12和下部引线框24流动于半导体芯片20。上部引线框12和下部引线框24还起着作为散热板的作用。当电流在半导体芯片20中流动时,半导体芯片20发热。由半导体芯片20产生的热经由下部引线框24散热,并且,经由金属块16和上部引线框12散热。因此,当电流在半导体芯片20中流动时,下部引线框24、金属块16以及上部引线框12变成比较高的温度。下部引线框24的线膨胀系数和金属块16的线膨胀系数比SiC基板30的线膨胀系数高。因此,下部引线框24和金属块16的膨胀量变得比SiC基板30的膨胀量大。由于SiC基板30的膨胀量小,下部引线框24的膨胀量大,因此,对SiC基板30和下部引线框24之间的第二焊料层22施加高的热应力。因此,当对半导体芯片20反复通电时,对第二焊料层22反复施加热应力,因焊料层的蠕变现象,在第二焊料层22的内部,焊料向外周侧移动。由于SiC基板30的膨胀量小,金属块16的膨胀量大,因此,对SiC基板30与金属块16之间的第一焊料层18施加高的热应力。因此,当对半导体芯片20反复通电时,对第一焊料层18反复施加热应力,因焊料的蠕变现象,在第一焊料层18的内部,焊料向外周侧移动。当在第一焊料层18的内部,焊料向外周侧移动时,在第一焊料层18的外周缘(即,上部电极32的外周缘32a附近),压力变高。因此,第一焊料层18在上部电极32的外周缘32a附近对SiC基板30向下方加压。压力施加于上部电极32的外周缘32a的下部的第二焊料层22。由于在上部电极32的外周缘32a的下部配置有凹部40,因此,压力施加于凹部40内的第二焊料层22。由于凹部40内的第二焊料层22的厚度厚,因此,凹部40内的第二焊料层22具有相对高的弹性,不易塑性变形。因此,即使对凹部40内的第二焊料层22反复施加压力,也不易因压力而导致焊料的移动。由于在下部引线框24设置有凸部42,因此,第二焊料层22的内部的焊料向中央部的移动受到凸部42的侧面的阻碍。因此,在第二焊料层22,几乎不发生像图19的箭头192所示那样的焊料向中央部的移动。因此,在实施方式的半导体组件10中,不易产生第二焊料层22将SiC基板30的中央部向上侧顶起的压力。因此,在实施方式的半导体组件10中,图19所示那样的半导体基板的翘曲得以抑制。从而,采用半导体组件10,能够抑制SiC基板30的随着时间的恶化,能够保持高的可靠性。
对于进行了规定次数的热循环时的SiC基板30的翘曲的模拟结果进行说明。在下部引线框24上不设置凹部40及凸部42的半导体组件(样品1)(即,如相关技术那样,下部引线框24的上表面24a是平坦的半导体组件)中,获得在SiC基板30中产生约6.82×10-4mm的翘曲的结果。由于一般的SiC基板的厚度在150μm以下,是极薄的,因此,在SiC基板中特别容易产生上述那样的翘曲。在下部引线框24上设置有凹部40但不设置凸部42的半导体组件(样品2)中,在与样品1同样的条件下,获得在SiC基板30中产生约3.78×10-4mm的翘曲的结果。如通过比较样品1、2所看出的那样,通过设置凹部40,能够有效地抑制SiC基板30的翘曲。在下部引线框24上设置有凹部40及凸部42的半导体组件(样品3)(即,图1、2的结构)中,在与样品2同样的条件下,获得在SiC基板30中产生约1.74×10-4mm的翘曲的结果。如通过比较样品2、3所看出的那样,通过设置凸部42,能够更有效地抑制SiC基板30的翘曲。
图5、6表示形成上述的凹部40及凸部42的工序。首先,利用图5所示的模具90,对加工前的下部引线框24的平坦的上表面24a加压,通过上述方式形成凹部40和凸部42。在图5的阶段,凸部42的上表面变成呈曲面状***的形状。在图5的阶段,在凹部40的外周缘形成有飞边94。利用图6所示的模具92,对凸部42的上表面和飞边94加压。通过上述方式,凸部42的上表面被平坦化,并且,消除飞边94。
下面,对于变形例进行说明。在下面说明的变形例的半导体组件中,除了特别提到的部分之外,具有与上述实施方式的半导体组件10同样的结构。
凹部40的截面形状可以适当地改变。图7表示变形例的凹部40的截面形状。在图7中,凹部40的截面具有U字形形状。在图7中,如箭头96所示,凹部40的最深部40a位于上部电极32的外周缘32a的内周侧(更详细地说,在沿着厚度方向观察SiC基板30时,最深部40a位于上部电极32的外周缘32a的内周侧。)。在图7的半导体组件的结构(样品4)中,进行与上述样品1同样的模拟,获得在SiC基板30中产生约2.35×10-4mm的翘曲的结果。在最深部40a位于上部电极32的外周缘32a的外周侧的结构(样品5)中,进行与上述样品4同样的模拟,获得在SiC基板中产生约2.49×10-4mm的翘曲的结果。如通过比较样品4、5所看出的那样,通过将凹部40的最深部40a配置在上部电极32的外周缘32a的内周侧,能够提高对SiC基板30的翘曲的抑制效果。
在图7中,如箭头98所示,凹部40的外周缘40b位于SiC基板30的外周缘30c的内周侧(更详细地说,在沿着厚度方向观察SiC基板30时,外周缘40b位于外周缘30c的内周侧。)。在图7的结构(即,样品4)中的SiC基板30的翘曲,如上所述,为2.35×10-4mm。与上面所述相对,在凹部40的外周缘40b位于SiC基板30的外周缘30c的外周侧的结构(样品6)中,进行与上述样品4同样的模拟,获得在SiC基板30中产生约4.56×10-4mm的翘曲的结果。如通过比较样品4、6所看出的那样,通过将凹部40的外周缘40b配置在SiC基板30的外周缘30c的内周侧,能够提高对SiC基板30的翘曲的抑制效果。
如图8所示,凹部40也可以具有V字形的截面形状。如图9所示,凹部40也可以具有矩形的截面形状。如图10所示,凹部40也可以具有阶梯状的截面形状。
在图1中,金属块16与上部引线框12被焊料层14连接起来。但是,如图11所示,也可以利用金属块16与上部引线框12一体化了的形状的金属部件19构成半导体组件。如图12所示,也可以没有金属块16,上部引线框12经由第一焊料层18被连接于半导体芯片20的上部电极。如图13所示,也可以将比上述的上部引线框12薄的端子12a连接于金属块16的上表面。如图14所示,也可以不经由金属块16,而将薄的端子12b连接于半导体芯片20的上部电极。
如图4所示,在上述实施方式的半导体组件10中,凹部40形成框状,以便在下部引线框24的上表面24a中包围某个范围。但是,只要是凹部40沿着上部电极32的外周缘32a的下部配置,则凹部40也可以不为框状。例如,如图15所示,凹部40也可以沿着上部电极32的外周缘32a的下部断续地分布。如图16所示,凹部40也可以沿着上部电极32的外周缘32a的下部部分断续地延伸。在图16中,表示出在下部引线框24上安装有两个半导体芯片20x、20y的结构。例如,也可以是半导体芯片20x构成MOSFET,半导体芯片20y构成二极管。在这种情况下,也可以在半导体芯片20x的上部电极32和半导体芯片20y的上部电极32中,在相互对向的边中不设置凹部40。如图17所示,凹部40也可以是断续的。
在上述实施方式中,凹部40的全部被第二焊料层22覆盖,但是,凹部40的一部分也可以不被第二焊料层22覆盖。
在上述实施方式中,半导体芯片20被绝缘树脂26覆盖,但是,半导体芯片20也可以不被绝缘树脂26覆盖。也可以代替绝缘树脂26而由硅凝胶等覆盖半导体芯片20。
对于上述实施方式的半导体组件的结构部件和本公开的半导体组件的结构部件的关系进行说明。实施方式的上部电极是本公开的第一电极的一个例子。实施方式的下部电极是本公开的第二电极的一个例子。实施方式的上部引线框是本公开的第一导电体的一个例子。实施方式的下部引线框是本公开的第二导电体的一个例子。实施方式的凸部是本公开的被凹部包围的范围内的接合面的一个例子。
对于本说明书公开的技术要素列举如下。下面的各个技术要素分别独立地起作用。
在本说明书公开的一个例子的半导体组件中,也可以在接合面处,凹部呈框状地延伸。也可以当沿着厚度方向观察半导体基板时,第一电极的整个外周缘与凹部重叠。
根据所述结构,能够更合适地抑制半导体基板的翘曲。
在本说明书公开的一个例子的半导体组件中,被凹部包围的范围内的接合面也可以与比凹部靠外周侧的第二导电体的表面相比向半导体基板侧突出。
根据所述结构,能够更恰当地抑制半导体基板的翘曲。
在本说明书公开的一个例子的半导体组件中,在沿着厚度方向观察半导体基板时,凹部的最深部也可以位于第一电极的外周缘的内周侧。
根据所述结构,可以更恰当地抑制半导体基板的翘曲。
在本说明书公开的一个例子的半导体组件中,第二焊料层也可以覆盖凹部和比凹部靠外周侧的第二导电体的表面。
上面,对于实施方式详细地进行了说明,但是,上面所述只不过是例子,并不限定专利的权利要求范围。在专利的权利要求范围中所记载的技术中,包括将以上列举的具体的例子进行各种各样的变形及变更。本说明书或者附图中说明的技术要素,可以单独地或者通过各种组合发挥其技术有效性,并不被申请时的权利要求所记载的组合所限定。本说明书或者附图中列举的技术可以同时达到多个目的,达到其中的一个目的这本身具有技术上的有效性。
Claims (8)
1.一种半导体组件,其特征在于,包括:
半导体基板;
第一电极,所述第一电极在所述半导体基板的第一表面的除外周区域以外的范围内接合到所述第一表面上;
第二电极,所述第二电极接合到作为所述第一表面的相反侧的所述半导体基板的表面的第二表面上;
第一导电体,所述第一导电体经由第一焊料层连接于所述第一电极;以及
第二导电体,所述第二导电体经由第二焊料层连接于所述第二电极,其中
当沿着所述半导体基板的厚度方向观察时,所述第二电极与整个所述第一电极重叠,并且,比所述第一电极宽,
在所述第二导电体的接合于所述第二焊料层的接合面上设置有凹部,所述凹部以当沿着厚度方向观察所述半导体基板时与所述第一电极的外周缘重叠的方式沿着所述外周缘配置。
2.如权利要求1所述的半导体组件,其特征在于,
在所述接合面,所述凹部呈环状延伸,
当沿着厚度方向观察所述半导体基板时,所述第一电极的所述外周缘全部与所述凹部重叠。
3.如权利要求2所述的半导体组件,其特征在于,
被所述凹部包围的范围内的所述接合面与比所述凹部靠外周侧的所述第二导电体的表面相比更向所述半导体基板侧突出。
4.如权利要求3所述的半导体组件,其特征在于,
当沿着厚度方向观察所述半导体基板时,所述凹部的最深部位于所述第一电极的所述外周缘的内周侧。
5.如权利要求2~4中任一项所述的半导体组件,其特征在于,
所述第二焊料层覆盖所述凹部和比所述凹部靠外周侧的所述第二导电体的表面。
6.如权利要求1~5中任一项所述的半导体组件,其特征在于,
当沿着厚度方向观察所述半导体基板时,所述凹部的外周缘位于所述半导体基板的外周缘的内周侧。
7.如权利要求1~6中任一项所述的半导体组件,其特征在于,
所述半导体基板是SiC基板。
8.如权利要求1所述的半导体组件,其特征在于,在所述第二导电体的接合于所述第二焊料层的接合面上设置有多个凹部,所述多个凹部以当沿着厚度方向观察所述半导体基板时与所述第一电极的外周缘重叠的方式沿着所述外周缘配置。
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JP2021005692A (ja) * | 2019-06-27 | 2021-01-14 | 株式会社デンソー | 半導体装置 |
US11776871B2 (en) * | 2020-12-15 | 2023-10-03 | Semiconductor Components Industries, Llc | Module with substrate recess for conductive-bonding component |
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JP2015095561A (ja) * | 2013-11-12 | 2015-05-18 | 株式会社デンソー | 半導体装置及びその製造方法 |
JP2016219532A (ja) * | 2015-05-18 | 2016-12-22 | 株式会社デンソー | 半導体装置 |
CN108630652A (zh) * | 2017-03-21 | 2018-10-09 | 丰田自动车株式会社 | 半导体装置、用于半导体装置的制造方法以及电极板 |
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EP3425666A1 (en) | 2019-01-09 |
US20190013261A1 (en) | 2019-01-10 |
TW201917851A (zh) | 2019-05-01 |
BR102018013849A2 (pt) | 2019-04-16 |
JP6834815B2 (ja) | 2021-02-24 |
JP2019016686A (ja) | 2019-01-31 |
CN109216312B (zh) | 2022-04-12 |
KR20190005736A (ko) | 2019-01-16 |
RU2686443C1 (ru) | 2019-04-25 |
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