CN109166878A - Nano-pore LED array chip and preparation method thereof with anti-reflection passivation layer - Google Patents
Nano-pore LED array chip and preparation method thereof with anti-reflection passivation layer Download PDFInfo
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- CN109166878A CN109166878A CN201811151396.4A CN201811151396A CN109166878A CN 109166878 A CN109166878 A CN 109166878A CN 201811151396 A CN201811151396 A CN 201811151396A CN 109166878 A CN109166878 A CN 109166878A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
Abstract
The present invention discloses the nano-pore LED array chip and preparation method thereof with anti-reflection passivation layer.LED array chip of the invention is made of N × N number of luminescence unit, and the anode of each luminescence unit is individually drawn, all luminescence unit common cathodes；The active area of luminescence unit has deeper nano-pore, and the depth of nano-pore is more than quantum well layer；Shallower nano-pore is also distributed in the dielectric thin film layer on GaN material surface, and dielectric film is arranged at the bottom of nano-pore.The present invention passes through dielectric passivation layer fluting on active region, in conjunction with mantle nanometer embossing, so that the deep nano-pore of active region and the shallow nano-pore of passivation layer can prepare completion simultaneously, the deep nano-pore of active region improves radiative recombination rate, the shallow nano-pore of passivation layer constitutes antireflective passivation layer, the evolution for being all conducive to improve photon mode, improves light extraction efficiency and modulation bandwidth.In addition, preparation method of the invention avoids deep etching process, have the advantages that simple process, yield are high.
Description
Technical field
The present invention relates to LED chip fields, and in particular to the micro-dimension with nano-pore structure for visible light communication
LED array chip and preparation method thereof.
Background technique
Visible light communication is LED(light emitting diode) in an important breakthrough point for surmounting lighting area.It can in order to improve
The modulation bandwidth of light-exposed communication system can optimize the feed circuit of signal receiver, or was lost using equalizing circuit lifting
Big Frequency point.This technical costs is cheap, significant effect, but due to Frequency point to be treated not only with LED component etc.
It imitates resistance and equivalent capacity is closely related and closely related with the dead resistance of whole system and parasitic capacitance, the tune of circuit
Section is often only applicable to specific LED component and system component, is not suitable for producing in batches.In addition, the tune of high-order also can be used
Technology processed, such as quadrature amplitude modulation technology (QAM), discrete Multi-tone Technology (DMT), orthogonal frequency division multiplexi (OFDM) and wavelength-division
Multiplexing technology (WDM).But these modulation techniques are dependent on complicated modulation circuit.
In order to improve the modulation bandwidth of visible light communication light source, micro-dimension LED chip can be used, and brilliant using such as photon
The technologies such as body, resonant cavity, surface phasmon improve Carrier recombination rate.But the formation of photonic crystal needs the stringent period
The nanostructure of distribution, GaN base resonant cavity need laser lift-off Sapphire Substrate or epitaxial layer distribution Bragg reflector etc.
Complex technology, surface phasmon are limited to Localized field enhancement characteristic and hole/biggish contradiction of electron injecting layer thickness, this is several
The technology difficulty of kind technology is all larger.Further, since GaN material and air refraction difference are larger, light is emitted inside LED chip
When, light escape cone is smaller, and light extraction efficiency is lower, is also unfavorable for high s/n ratio and high speed visible light communication.
Summary of the invention
In view of the above-mentioned deficiencies in the prior art, it is an object of the present invention to provide a kind of nano-pore with anti-reflection passivation layer
LED array chip.The chip is formed by N × N number of luminescence unit, wherein N >=2, and the anode of each luminescence unit individually draws
Out, all luminescence unit common cathodes；The active area of luminescence unit has deeper nano-pore, and the depth of nano-pore is more than Quantum Well
Layer, improves radiative recombination rate；Shallower nano-pore is distributed in the passivation layer of chip surface, constitutes anti-reflection passivation layer.
The object of the invention is also to provide a kind of systems of nano-pore LED array chip with anti-reflection passivation layer
Preparation Method.This method is using " preparation media insulating layer à prepares dielectric passivation layer on electrode à preparation media passivation layer à active region
The process flow of à mantle nano impression à etching of slotting nano-pore ", the deep nano-pore and chip list of the active region of luminescence unit
The shallow nano-pore of the passivation layer in the other regions in face can prepare completion simultaneously.
The purpose of the present invention is achieved through the following technical solutions.
Nano-pore LED array chip provided by the invention with anti-reflection passivation layer, by N × N number of luminescence unit, N ×
N number of anode bond pad and two cathode pads form, wherein N >=2, between electrode pad and metal contact wires and semiconductor material
It is isolated by dielectric insulation layer；The diameter of the active area of luminescence unit is between 100 μm to 200 μm；The active area of luminescence unit has
There is deeper nano-pore, the depth of nano-pore is more than quantum well layer, and the diameter of nano-pore is 300nm between 1000nm；GaN material
Shallower nano-pore is also distributed in the dielectric thin film layer on material surface, constitutes anti-reflection passivation layer, the depth of nano-pore be 200nm extremely
Dielectric film is arranged at the bottom of 500nm, nano-pore.
Further, from substrate to light exit direction, the active region of luminescence unit successively includes Sapphire Substrate, GaN
It is buffer layer, unintentional doped gan layer, n-type doping GaN layer, quantum well layer, p-type doping AlGaN layer, p-type doped gan layer, transparent
Current extending and dielectric passivation layer.
Further, from substrate to light exit direction, electrode pad region successively include Sapphire Substrate, GaN buffer layer,
Unintentional doped gan layer, n-type doping GaN layer, dielectric insulation layer, metal electrode.
Further, luminescence unit is in frustum cone structure form, and the anode of luminescence unit is in the form of annular discs, is distributed in the upper of rotary table
Centre of surface；The cathode of luminescence unit is annular in shape, is distributed around rotary table；Cathode ring has a notch, anode and anode
Metal contact wires between pad pass through this notch and realize connection, and the width of metal contact wires is 20 μm or more, the width of notch
20 μm bigger than the width of metal contact wires of degree or more；The anode of each luminescence unit individually leads to anode bond pad, all to shine
Unit common cathode and respectively there is a cathode pad in the first row and Nth row.
Further, dielectric insulation layer is distributed in the upper surface of the semiconductor material of entire chip, in electrode pad and gold
Belong to being formed between connecting line and semiconductor material and be electrically insulated, but slots in the anode and cathode region of luminescence unit；The medium
Insulating layer is SiO2, one or more of SiN, SiON, thickness is 300nm or more；The semiconductor material includes transparent electric current
Extension layer, p-type doped gan layer, p-type adulterate AlGaN layer, quantum well layer, n-type doping GaN layer.
The preparation method of nano-pore LED array chip provided by the invention with anti-reflection passivation layer, includes the following steps:
(1) GaN base LED epitaxial wafer is prepared using metal oxide vapor phase deposition method, the structure of GaN base LED epitaxial wafer is successively wrapped
Include Sapphire Substrate, GaN buffer layer, unintentional doped gan layer, n-type doping GaN layer, quantum well layer, p-type doping AlGaN layer and
P-type doped gan layer.
(2) transparent current extending is deposited in GaN base LED epitaxial wafer using electron beam evaporation, formed through short annealing
Ohmic contact reuses ultraviolet photolithographic and wet etching, forms the transparent electric current being only distributed in the active region of luminescence unit and expands
Open up layer disk.The annealing temperature of the rta technique is 500 ~ 650 DEG C, and heating rate is 5 ~ 15 DEG C/sec, and atmosphere is nitrogen
The gaseous mixture of gas and oxygen, annealing time are 60 ~ 300sec.
(3) sense coupling is used, exposure n-type doping GaN layer forms the frustum cone structure of luminescence unit.
(4) plasma enhanced chemical vapor deposition preparation media insulating layer is used, ultraviolet photolithographic and induction coupling are reused
Plasma etching is closed, is slotted in the anode and cathode region of luminescence unit.
(5) disk is prepared using negtive photoresist removing and electron beam evaporation, the anode grooving region on the rotary table of luminescence unit
The anode of shape in the cathode that the preparation of cathode slot area is circular, and prepares anode bond pad, cathode pad on electrode dielectric layer
And metal contact wires.
(6) plasma enhanced chemical vapor deposition preparation media passivation layer is used, ultraviolet photolithographic and induction are then used
Dielectric passivation layer fluting of the coupled plasma etch on active region is used for nano impression；The range of slot area is:
Within the rotary table of luminescence unit, except the anode grooving region of the luminescence unit and metal contact wires region of luminescence unit it
Outside.
(7) spin coating tackifier and nano impression glue in dielectric passivation layer, reuse mantle nano impression in entire chip
Upper surface imprinting moulding nanometer sectional hole patterns；Then using sense coupling removal, airport bottom is remaining receives
Rice coining glue.
(8) the nanometer sectional hole patterns on nano impression glue are transferred to dielectric passivation using sense coupling
Layer.
(9) sense coupling machine is reused to perform etching.In active region, nanometer sectional hole patterns successively from compared with
Thin dielectric passivation layer is transferred to transparent current extending and GaN semiconductor material layer, and the etching depth of GaN semiconductor material is super
Cross the depth 50nm or more of Quantum Well；In other regions, nanometer sectional hole patterns continue to extend in thicker dielectric passivation layer toward depths.
(10) ultraviolet photolithographic and wet etching are used, in anode, cathode, electrode pad and metal contact wires region exposed gold
Belong to electrode.
Further, in step (4), the plasma enhanced chemical vapor deposition point four steps preparation of dielectric insulation layer, the
LED epitaxial wafer is put into the sample load plate of plasma enhanced chemical vapor deposition equipment, deposition medium film to target by one step
The 1/4 of thickness；LED epitaxial wafer is rotated by 90 °, the 1/2 of deposition medium film to target thickness by second step on load plate；Third
Step, LED epitaxial wafer is rotated by 90 ° again on load plate, the 3/4 of deposition medium film to target thickness；4th step, by LED extension
Piece is rotated by 90 ° again on load plate, deposition medium film to target thickness.
Compared with prior art, the invention has the advantages that and the utility model has the advantages that
(1) the nano-pore LED array chip prepared by the present invention with anti-reflection passivation layer, using individually controllable N × N number of micro-
Size luminescence unit, on the basis of keeping modulation bandwidth, in conjunction with multiple-input and multiple-output (MIMO) technology and simple on & off switch
Control (OOK) coding techniques can improve message capacity；It is exhausted that the anode bond pad and metal contact wires of luminescence unit are distributed in medium
On edge layer, and all luminescence unit common cathodes, so that the semiconductor epitaxial layers of each luminescence unit can be realized without isolation
It is individually controllable, avoid adjacent light-emitting units semiconductor epitaxial layers it is mutually isolated when deep etching process, so array chip
Integration mode have the advantages that simple process, yield are high.
(2) the nano-pore LED array chip prepared by the present invention with anti-reflection passivation layer, using " preparation media insulating layer à
Prepare the fluting à mantle nano impression à etching of dielectric passivation layer on electrode à preparation media passivation layer à active region nano-pore " work
Skill process.On the one hand, in order to formed between metal wire and semiconductor material it is good be isolated, need using thicker medium every
Absciss layer；In order to protect metal electrode injury-free in nano-pore etching technics, need using thicker dielectric passivation layer；Medium
Separation layer and dielectric passivation layer are covered with the active region of luminescence unit；When active region etches nano-pore, this two layers all
It needs to be etched away, therefore it is required that nano impression glue is sufficiently thick or coining glue/dielectric layer etching selection ratio is sufficiently large, thus
Very big difficulty is caused to nano-imprint process or nano-pore etching technics；By on active region dielectric passivation layer open
The thickness of the passivation layer of active region suitably can be thinned for slot；When active area nano-pore etching after the completion of, other regions it is blunt
Although changing layer to be also etched to obtain nano-pore, the bottom of nano-pore has the dielectric film of adequate thickness to avoid damage metal electricity
Pole or GaN material.On the other hand, using mantle nano impression, ups and downs chip surface is all imprintable is received entire
The shallow nano-pore of metre hole pattern, the passivation layer of the deep nano-pore and surface GaN of the active region of luminescence unit can have been prepared simultaneously
At the deep nano-pore of active region improves radiative recombination rate, and the shallow nano-pore of passivation layer constitutes antireflective passivation layer, all
The evolution for being conducive to improve photon mode, improves light extraction efficiency and modulation bandwidth.
(3) preparation method of the nano-pore LED array chip proposed by the present invention with anti-reflection passivation layer, in preparation media
When insulating layer, using " 1/4 thickness à of deposition, which is rotated by 90 ° 1/4 thickness à of redeposition and is rotated by 90 ° 1/4 thickness à of redeposition, to be rotated by 90 ° again
Deposit 1/4 thickness " four step process processes, advantageously reduce SiO2In pin hole, reduce electric leakage, it is relatively thin so as to use
SiO2Dielectric layer can meet isolation effect.
Detailed description of the invention
Fig. 1 a is the top view illustration of the nano-pore LED array chip in specific embodiment with anti-reflection passivation layer；
Fig. 1 b is that cross section of the nano-pore LED array chip at transversal AA ' in specific embodiment with anti-reflection passivation layer shows
It is intended to；
Fig. 2 a be embodiment 1 the nano-pore LED array chip preparation process with anti-reflection passivation layer in prepare ohmic contact layer
And the top view illustration after the rotary table of luminescence unit；
Fig. 2 b is preparation media insulating layer in the nano-pore LED array chip preparation process with anti-reflection passivation layer of embodiment 1
And open the top view illustration after slot electrode；
After Fig. 2 c is prepares metal electrode in the nano-pore LED array chip preparation process with anti-reflection passivation layer of embodiment 1
Top view illustration；
Fig. 2 d is preparation media mask layer in the nano-pore LED array chip preparation process with anti-reflection passivation layer of embodiment 1
And open the top view illustration after nano impression slot；
Fig. 2 e is nano impression and dry method in the nano-pore LED array chip preparation process with anti-reflection passivation layer of embodiment 1
Top view illustration after etching；
Fig. 2 f is fluting exposing metal electricity in the nano-pore LED array chip preparation process with anti-reflection passivation layer of embodiment 1
Top view illustration behind pole and electrode pad；
Fig. 3 a be embodiment 1 the nano-pore LED array chip preparation process with anti-reflection passivation layer in prepare ohmic contact layer
And the cross-sectional view after the rotary table of luminescence unit；
Fig. 3 b is preparation media insulating layer in the nano-pore LED array chip preparation process with anti-reflection passivation layer of embodiment 1
And open the cross-sectional view after slot electrode；
After Fig. 3 c is prepares metal electrode in the nano-pore LED array chip preparation process with anti-reflection passivation layer of embodiment 1
Cross-sectional view；
Fig. 3 d is preparation media mask layer in the nano-pore LED array chip preparation process with anti-reflection passivation layer of embodiment 1
And open the cross-sectional view after nano impression slot；
Fig. 3 e is nano impression and dry method in the nano-pore LED array chip preparation process with anti-reflection passivation layer of embodiment 1
Cross-sectional view after etching；
Fig. 3 f is fluting exposing metal electricity in the nano-pore LED array chip preparation process with anti-reflection passivation layer of embodiment 1
Cross-sectional view behind pole and electrode pad；
In figure, 1-Sapphire Substrate；2-GaN buffer layers；3-unintentional doped gan layer；4-n-type doping GaN layers；5-amounts
Sub- well layer；6-p-types adulterate AlGaN layer；7-p-type doped gan layer；8-transparent current extendings；100-dielectric insulation layers；
The dielectric passivation layer on the 101-surfaces GaN；Dielectric passivation layer on 102-metal electrodes；The dielectric passivation of 103-active regions
Layer；200-anodes；201-cathodes；202-metal contact wires；203-cathode pads；204-anode bond pads；300-media
The fluting of insulating layer Anodic；The fluting of cathode on 301-dielectric insulation layers；Active region opens in 302-dielectric passivation layers
Slot；The fluting of 303-passivation layer Anodics；The fluting of cathode on 304-passivation layers；305-passivation layer Anodic pads are opened
Slot；The fluting of cathode pad on 306-passivation layers；The passivation layer on the surface GaN after 401-nano-pores etching；402-the surfaces GaN
Passivation layer nano-pore；Passivation layer after 403-nano-pores etching on metal electrode；Passivation layer on 404-metal electrodes
Nano-pore；The passivation layer of active region after 405-nano-pores etching；The nano-pore of 406-active areas；81-luminescence units
Rotary table.
Specific embodiment
Specific implementation of the invention is described further below in conjunction with attached drawing, but implementation and protection scope of the invention is not
It is limited to this.
LED gusts of nano-pore for one of specific embodiment of the invention with anti-reflection passivation layer as illustrated in figs. 1A and ib
Column chip, GaN base LED chip are made of 2 × 2 luminescence units, 2 × 2 anode bond pads and two cathode pads, anode bond pad
204, it is isolated between cathode pad 203 and metal contact wires 202 and semiconductor material by dielectric insulation layer 100；Luminescence unit
Dielectric passivation layer 103 on active region has slot area 302, and slot area 302 has nano-pore 406, the diameter of nano-pore
It is 450nm, the depth of nano-pore is 900nm, and the thickness of the dielectric passivation layer 405 of slot area 302 is 70nm；GaN material table
The SiO in face2Nano-pore 402 is also distributed in dielectric thin film layer, and the diameter of nano-pore is 450nm, and the depth of nano-pore is 280nm,
The thickness of the dielectric film of the bottom of nano-pore is 70nm, and the thickness of dielectric thin film layer 401 is 750nm；The anode of luminescence unit
On have the fluting 303 of dielectric passivation layer, the fluting 304 for having dielectric passivation layer on cathode, have dielectric passivation layer in anode bond pad
There is the fluting 306 of dielectric passivation layer on fluting 305, cathode pad.
From substrate to light exit direction, the active region of luminescence unit successively include Sapphire Substrate 1, GaN buffer layer 2,
Unintentional doped gan layer 3, n-type doping GaN layer 4, quantum well layer 5, p-type adulterate AlGaN layer 6, p-type doped gan layer 7, transparent electricity
Flow extension layer 8 and dielectric passivation layer 405.
From substrate to light exit direction, electrode pad region successively includes Sapphire Substrate 1, GaN buffer layer 2, unintentional
Doped gan layer 3, n-type doping GaN layer 4, dielectric insulation layer 100, anode bond pad 204 or cathode pad 203.
Luminescence unit is in frustum cone structure form, and the diameter of rotary table 81 is 120 μm, and the anode 200 of luminescence unit is in the form of annular discs,
Diameter is 40 μm, is distributed in the upper surface center of rotary table 81；The cathode 201 of luminescence unit is annular in shape, and width is 10 μm, surrounds
Rotary table 81 be distributed；Cathode ring 201 has a notch, and gap width is 40 μm, between anode 200 and anode bond pad 204
Metal contact wires 202 pass through this notch and realize connection, and the width of metal contact wires 202 is 20 μm.The sun of each luminescence unit
Pole 200 individually leads to anode bond pad 204, all luminescence unit common cathodes and respectively has a cathode weldering in the first row and the 2nd row
Disk 203.
SiO2Dielectric insulation layer 100 is distributed in the upper surface of the semiconductor material of entire chip, with a thickness of 400nm, in sun
It is formed and is electrically insulated between pole pad 204, cathode pad 203 and metal contact wires 202 and semiconductor material.GaN material surface
SiO2Dielectric thin film layer 401 is by SiO2Dielectric insulation layer 100 and SiO2Dielectric passivation layer 101 forms, SiO2Dielectric insulation layer 100
Thickness be 400nm, SiO2The thickness of dielectric passivation layer 101 after deposit is 480nm, after nano-pore etch process flow,
SiO2The thickness of dielectric passivation layer 101 is 350nm, and passivation layer contains nano-pore 402, the SiO of nano-pore bottom2Thickness is 70nm,
Therefore the thickness of SiO2 dielectric thin film layer 401 is 750nm.There is slot area 300 in the anode region 200 of luminescence unit, is shining
The cathode zone 201 of unit has slot area 301.
The preparation step of embodiment 1, the nano-pore LED array chip with anti-reflection passivation layer is as follows.
(1) prepare GaN base LED epitaxial wafer using metal oxide vapor phase deposition method, the structure of GaN base LED epitaxial wafer according to
Secondary includes Sapphire Substrate 1, GaN buffer layer 2, unintentional doped gan layer 3, n-type doping GaN layer 4, quantum well layer 5, p-type doping
AlGaN layer 6 and p-type doped gan layer 7.As shown in Figure 3a.
(2) transparent current extending ITO 8 is deposited in GaN base LED epitaxial wafer using electron beam evaporation, with a thickness of
100nm, in N2 200sccm、O2 Short annealing 3min forms Ohmic contact under the mixed atmosphere of 35sccm, reuses ultraviolet light
Quarter and wet etching impregnate 15min using ITO corrosive liquid at normal temperature, are formed only in the active region distribution of luminescence unit
ITO disk, 116 μm of disk diameter.As shown in Figure 3a.
(3) sense coupling is used, etch period 7min, exposes n-type doping GaN by 1.2 μm of etching depth
Layer, forms the rotary table MESA structure 81 of luminescence unit, MESA diameter is 120 μm.As shown by figures 2 a and 3.
(4) SiO is prepared using plasma enhanced chemical vapor deposition2Dielectric insulation layer 100, at 350 DEG C, point four steps
Deposition: the first step deposits 7min；LED epitaxial wafer is rotated by 90 ° by second step on load plate, deposits 7min；Third step, will be outside LED
Prolong piece to be rotated by 90 ° again on load plate, deposits 7min；LED epitaxial wafer is rotated by 90 ° by the 4th step again on load plate, deposits 7min；
Four step overall thickness 400nm.Ultraviolet photolithographic and sense coupling are reused, is formed in the anode region of luminescence unit
Slot area 300 and cathode zone form slot area 301.As shown in Fig. 2 b and Fig. 3 b.
(5) using negtive photoresist removing and electron beam evaporation Cr/Al/Ti/Au, the thickness difference 50/8000/ of four layers of metallic film
200/100nm, discoid anode 200 is prepared in the anode grooving region 300 of luminescence unit, and electrode diameter is 40 μm；It is sending out
The cathode slot area 301 of light unit prepares circular cathode 201, and width is 10 μm；It is prepared in electrode pad region rectangular
Cathode pad 203, the side length of pad is 100 μm, prepares circular anode bond pad 204, and the diameter of pad is 90 μm；And it prepares
Metal contact wires 202 between cathode or between electrode and pad, width are 20 μm；Anode bond pad 204, cathode pad 203
SiO is distributed in metal contact wires 2022On dielectric insulation layer 100.As shown in Fig. 2 c and 3c.
(6) SiO is prepared using plasma enhanced chemical vapor deposition2Dielectric passivation layer 101 deposits at 350 DEG C
480nm；Then the dielectric passivation of ultraviolet photolithographic and sense coupling on the active region of luminescence unit is used
Layer fluting, groove depth is 280nm, and the range of slot area 302 is: within the rotary table MESA 81 of luminescence unit, luminescence unit
Anode grooving region 300 except and the metal contact wires region 202 of luminescence unit except.As shown in Fig. 2 d and 3d.This
When, the SiO on LED chip surface2There are three thickness altogether for dielectric film.In slot area 302 on the active region of luminescence unit
SiO2The thickness of dielectric film 103 is 200nm, metal anode 200, metallic cathode 201, metal anode pad 203, metallic cathode
SiO on pad 204, metal contact wires 2022The thickness of dielectric film 102 is 480nm, the SiO on GaN material surface2Dielectric film
It is SiO2Dielectric insulation layer 100 and SiO2The summation of dielectric passivation layer 101, thickness are 880nm.
(7) spin coating tackifier and nano impression glue in dielectric passivation layer, glue thickness 305nm；Reuse mantle nanometer pressure
It is imprinted on the upper surface imprinting moulding nanometer sectional hole patterns of entire chip, imprint time 5min, uv-exposure amount 4000mJ/cm2, coining
Depth is 280nm；
Then it is handled under CHF3 and Ar mixed atmosphere using sense coupling, CHF3 flow 15sccm, Ar stream
50sccm, lower electrode radio-frequency power 500W, plasma rf power 200W are measured, time 60sec is handled, removes airport bottom
Remaining nano impression glue.At this point, the depth of the nano-pore in nano impression glue has penetrated coining glue-line, glue thickness is imprinted
280nm, nanometer hole depth 280nm.
(8) it reuses sense coupling and the nanometer sectional hole patterns on nano impression glue is transferred to dielectric passivation
Layer, lower electrode radio-frequency power 100W, plasma rf power 400W, CHF3 50sccm, Ar 100sccm, time
4min30sec.At this point, the depth of nano-pore has penetrated SiO in the slot area 302 of luminescence unit2Dielectric film 103, it is other
The SiO in region2The depth of nano-pore extends at 200nm in dielectric passivation layer.
(9) sense coupling is reused, nanometer sectional hole patterns are transferred to transparent electric current from dielectric passivation layer
Extension layer ITO 8, lower electrode radio-frequency power 150W, plasma rf power 500W, BCl3 30sccm, Ar 60sccm, when
Between 1min.At this point, the depth of nano-pore has penetrated transparent current extending ITO 8 in the slot area 302 of luminescence unit, it is other
The SiO in region2The depth of nano-pore extends at 260nm in dielectric passivation layer.
Sense coupling continues, and nanometer sectional hole patterns are transferred to GaN semiconductor material layer, lower electrode
Radio-frequency power 500W, plasma rf power 365W, Cl2 90sccm, BCl3 10 sccm, time 4min.At this point, shining
The depth of nano-pore arrived at GaN material depth 900nm in the slot area 302 of unit, the SiO in other regions2Dielectric passivation
The depth of nano-pore extends at 410nm on layer, SiO2130nm is thinned in the thickness of dielectric passivation layer.As shown in Fig. 2 e and 3e.
(10) ultraviolet photolithographic and wet etching are used, in anode region fluting 303, cathode zone fluting 304, anode bond pad
Region fluting 305, cathode pad region 306 exposing metal electrodes of fluting.As shown in Fig. 2 f and 3f.
Claims (8)
1. a kind of nano-pore LED array chip with anti-reflection passivation layer, it is characterised in that: including N × N number of luminescence unit, N
× N number of anode bond pad and two cathode pads, wherein N >=2, square array distribution pass through between the electrode pad
Metal contact wires connection, is isolated between the metal contact wires and semiconductor material by dielectric insulation layer；The luminescence unit
Active area diameter be 100~200 μm；Nano-pore, the active area nano-pore are distributed on the active area of the luminescence unit
Depth be more than quantum well layer, diameter be 300~1000nm；Distribution is received simultaneously on the dielectric thin film layer on the GaN material surface
Metre hole, constitutes anti-reflection passivation layer, and the depth in GaN material nano surface hole is 200~500nm.
2. a kind of nano-pore LED array chip with anti-reflection passivation layer according to claim 1, it is characterised in that: from
To light exit direction, the active region of the luminescence unit successively includes Sapphire Substrate, GaN buffer layer, unintentional mixes substrate
Miscellaneous GaN layer, n-type doping GaN layer, quantum well layer, p-type doping AlGaN layer, p-type doped gan layer, transparent current extending and Jie
Matter passivation layer.
3. a kind of nano-pore LED array chip with anti-reflection passivation layer according to claim 1, it is characterised in that: from
For substrate to light exit direction, the electrode pad region successively includes Sapphire Substrate, GaN buffer layer, unintentional doping GaN
Layer, n-type doping GaN layer, dielectric insulation layer and metal electrode.
4. a kind of nano-pore LED array chip with anti-reflection passivation layer according to claim 1, it is characterised in that: institute
Luminescence unit is stated in frustum cone structure form, the anode of the luminescence unit is in the form of annular discs, is distributed in the upper surface center of rotary table；Yin
It is extremely annular in shape, it is distributed around rotary table；The annular shape of cathode is equipped with notch, the metal between the anode and anode bond pad
Connecting line is connected across notch, and the width of the metal contact wires is greater than 20 μm, and the width of the notch is than metal contact wires
Big 20 μm of width or more；The anode of each luminescence unit is connected individually to anode bond pad, all luminescence unit common cathodes and
A line and Nth row respectively have a cathode pad.
5. a kind of nano-pore LED array chip with anti-reflection passivation layer according to claim 1, which is characterized in that institute
The semiconductor material upper surface that dielectric insulation layer is covered on entire chip is stated, in electrode pad and metal contact wires and semiconductor material
Electrical isolation is formed between material；The dielectric insulation layer is SiO2, SiN or SiON, thickness is more than or equal to 300nm；The semiconductor
Material includes transparent current extending, p-type doped gan layer, p-type doping AlGaN layer, quantum well layer, n-type doping GaN layer.
6. a kind of preparation method of the nano-pore LED array chip with anti-reflection passivation layer, which is characterized in that including walking as follows
It is rapid:
Step 1 prepares GaN base LED epitaxial wafer using metal oxide vapor phase deposition method, and the structure of GaN base LED epitaxial wafer is successively
AlGaN layer is adulterated including Sapphire Substrate, GaN buffer layer, unintentional doped gan layer, n-type doping GaN layer, quantum well layer, p-type
With p-type doped gan layer；
Step 2 deposits transparent current extending using electron beam evaporation in GaN base LED epitaxial wafer, forms Europe through short annealing
Nurse contact, reuses ultraviolet photolithographic and wet etching, forms the transparent current expansion being only distributed in the active region of luminescence unit
Layer disk；
Step 3, using sense coupling, exposure n-type doping GaN layer forms the frustum cone structure of luminescence unit；
Step 4, using plasma enhanced chemical vapor deposition preparation media insulating layer, reuse ultraviolet photolithographic and inductively
Plasma etching is slotted in the anode and cathode region of luminescence unit；
Step 5 prepares discoid using negtive photoresist removing and electron beam evaporation, the anode grooving region on the rotary table of luminescence unit
Anode, in the cathode that the preparation of cathode slot area is circular, and prepare on electrode dielectric layer anode bond pad, cathode pad with
And metal contact wires；
Step 6, using plasma enhanced chemical vapor deposition preparation media passivation layer, then using ultraviolet photolithographic and induction coupling
It closes dielectric passivation layer fluting of the plasma etching on active region and is used for nano impression；The range of slot area is included in hair
Within the rotary table of light unit, except the anode grooving region of luminescence unit and except the metal contact wires region of luminescence unit；
Step 7, spin coating tackifier and nano impression glue in dielectric passivation layer, reuse mantle nano impression in entire chip
Upper surface imprinting moulding nanometer sectional hole patterns；Then the remaining nanometer in airport bottom is removed using sense coupling
Imprint glue；
Nanometer sectional hole patterns on nano impression glue are transferred to dielectric passivation layer using sense coupling by step 8；
Step 9 reuses sense coupling machine and performs etching；In active region, nanometer sectional hole patterns successively from compared with
Thin dielectric passivation layer is transferred to transparent current extending and GaN semiconductor material layer, and the etching depth of GaN semiconductor material is super
Cross the depth 50nm or more of Quantum Well；In other regions, nanometer sectional hole patterns continue to extend in thicker dielectric passivation layer toward depths；
Step 10, using ultraviolet photolithographic and wet etching, in anode, cathode, electrode pad and metal contact wires region exposed gold
Belong to electrode.
7. preparation method according to claim 6, which is characterized in that in the step 4, comprising the following steps:
Step 41, the sample load plate that LED epitaxial wafer is put into plasma enhanced chemical vapor deposition equipment, deposition medium film
To the 1/4 of target thickness；
LED epitaxial wafer is rotated by 90 °, the 1/2 of deposition medium film to target thickness by step 42 on load plate；
LED epitaxial wafer is rotated by 90 °, the 3/4 of deposition medium film to target thickness by step 43 again on load plate；
LED epitaxial wafer is rotated by 90 °, deposition medium film to target thickness by step 44 again on load plate.
8. preparation method according to claim 6, which is characterized in that the annealing temperature of the rta technique is 500 ~
650 DEG C, heating rate is 5 ~ 15 DEG C/sec, and atmosphere is the gaseous mixture of nitrogen and oxygen, and annealing time is 60 ~ 300sec.
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| CN113488573A (en) * | 2021-06-04 | 2021-10-08 | 北京大学 | Preparation method for improving light emitting efficiency of LED packaging device by using amorphous photon structure |
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