CN109166507A - Testing element group, electrical performance test method, array substrate, display device - Google Patents
Testing element group, electrical performance test method, array substrate, display device Download PDFInfo
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- CN109166507A CN109166507A CN201811296862.8A CN201811296862A CN109166507A CN 109166507 A CN109166507 A CN 109166507A CN 201811296862 A CN201811296862 A CN 201811296862A CN 109166507 A CN109166507 A CN 109166507A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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Abstract
The invention discloses testing element group, electrical performance test method, array substrate, display devices.Specifically, the invention proposes a kind of testing element groups, comprising: the multiple thin film transistor (TFT)s and multiple test interfaces for the electric connection being disposed on the substrate, wherein the grid of at least two thin film transistor (TFT)s is connected with the same test interface.As a result, when carrying out electrical performance testing to array substrate using the testing element group, multiple thin film transistor (TFT)s can be detected every time, and then the time for detecting certain amount thin film transistor (TFT) can greatly reduce, and improve testing efficiency.
Description
Technical field
The present invention relates to field of display technology, and in particular, to testing element group, electrical performance test method, array base
Plate, display device.
Background technique
Thin film transistor (TFT) (Thin Film Transistor, TFT) is that current liquid crystal display device and active matrix drive
The performance of main driving element in dynamic formula organic light-emitting display device, thin film transistor (TFT) will have a direct impact on the display of display device
Performance.Therefore, it during the manufacturing of TFT substrate (i.e. array substrate), needs to be monitored the characteristic value of TFT substrate
Test.TFT characteristic due to directly testing viewing area (i.e. effective luminous zone, the area AA, Active Area) has that difficulty is big, surveys
Examination slowly, destructive testing the disadvantages of, therefore, during making TFT substrate, it will usually (i.e. non-around viewing area
Viewing area) some testing element groups (Test Element Group, TEG) of design, electrical testing equipment (EPM) is by TFT
The testing element group (TEG) of the periphery substrate (Panel) is tested, and the characteristic value to thin film transistor (TFT) in viewing area can be realized
Monitoring.
However, current testing element group, array substrate and display device still has much room for improvement.
Summary of the invention
The present invention be based on inventor couple on the fact that and problem discovery and understanding make:
Inventors have found that currently with electrical testing equipment (EPM) to the testing element group of the periphery TFT substrate (Panel)
(TEG) method tested, and then monitor thin film transistor (TFT) (TFT) characteristic value in viewing area, it is lower that there are testing efficiencies
Problem.In current TFT substrate, a testing element group (TEG) generally includes a thin film transistor (TFT), the thin film transistor (TFT) and
Thin film transistor (TFT) in viewing area is made by same technique, film layer structure having the same, therefore, should by test
The characteristic value of thin film transistor (TFT) in testing element group, it can the characteristic value of the thin film transistor (TFT) in viewing area is supervised
It surveys.Grid (Gate), source electrode (Sourse) and the drain electrode (Drain) of a general thin film transistor (TFT) pass through individual lead point
It is not connected to three testing cushions (PAD, i.e. test interface), the corresponding characteristic test position of a testing cushion (PAD) is (i.e. corresponding
A test fingers (Pin) in electrical testing equipment (EPM)), subsequent electrical testing equipment (EPM) passes through to the testing cushion
(PAD) signal loading is carried out, the characteristic value of the thin film transistor (TFT) can be measured.
When testing currently with electrical testing equipment (EPM) testing element group (TEG), electrical testing equipment
(EPM) multiple test fingers (Pin) in arrange in a certain way and position be it is fixed, therefore, testing element group (TEG)
In multiple testing cushions (PAD) arrangement mode need it is consistent with the arrangement mode of test fingers (Pin), to just can be carried out
Corresponding test.Current testing cushion (PAD) is typically designed to four point independence pads, i.e. four testing cushion (PAD) correspondences are one thin
Film transistor, as previously mentioned, the grid (Gate) of a thin film transistor (TFT), source electrode (Sourse) and drain electrode (Drain) pass through
Individual lead is connected to three testing cushions (PAD), and the free time goes out a testing cushion (PAD), thus an each pair of thin film transistor (TFT)
When being detected, just the free time goes out a test fingers (Pin).It is thus impossible to make full use of test fingers (Pin), single is caused
The number for testing the thin film transistor (TFT) that can be detected is less, and testing efficiency is lower.Therefore, if a kind of new test member can be proposed
Part group, can increase the number of the thin film transistor (TFT) of single test, and the testing cushion of mentioned-above free time (can be surveyed
Try mouth) it is used, testing efficiency will be largely improved, will largely be solved the above problems.
The present invention is directed to alleviate or solve the problems, such as at least one in above-mentioned refer at least to some extent.
In one aspect of the invention, the invention proposes a kind of testing element groups.According to an embodiment of the invention, the survey
Examination element group includes: the multiple thin film transistor (TFT)s and multiple test interfaces for the electric connection being disposed on the substrate, wherein at least
The grid of two thin film transistor (TFT)s is connected with the same test interface.It is poised for battle as a result, using the testing element group
When column substrate carries out electrical performance testing, the utilization rate of test interface can be improved, multiple thin film transistor (TFT)s can be carried out every time
Detection, and then the time for detecting certain amount thin film transistor (TFT) can greatly reduce, and improve testing efficiency, and survey can be improved
The accuracy of examination.
According to an embodiment of the invention, the source electrode of at least two thin film transistor (TFT)s and the same test interface phase
Even.Thus, it is possible to further increase the utilization rate of test interface, increase the number of detectable thin film transistor (TFT) in single test
Mesh further increases testing efficiency.
According to an embodiment of the invention, the test interface includes grid interface, source electrode interface and drain junction, connection
To multiple source electrodes of multiple thin film transistor (TFT)s of the same grid interface, with the same source electrode interface phase
Even.It is convenient for cabling as a result, and mentioned-above multiple thin film transistor (TFT)s is detected convenient for test equipment single, further
Improve testing efficiency.
According to an embodiment of the invention, the grid of multiple thin film transistor (TFT)s in the testing element group connects
It is connected to the grid interface, the source electrode of multiple thin film transistor (TFT)s in the testing element group is connected to one
A source electrode interface.Thus, it is possible to largely improve the utilization rate of test interface, the film crystal of single test is improved
The number of pipe further increases testing efficiency, and improves test accuracy.
According to an embodiment of the invention, multiple thin film transistor (TFT)s are arranged along first direction, multiple test interfaces
It is arranged on the two sides of multiple thin film transistor (TFT)s and is arranged in two rows along the first direction, extend from the grid interface
Gate connection line out, the gate connection line setting extend between the test interface described in two rows and along the first direction；From
The source electrode interface extends source connection lines, and the source connection lines setting is between the test interface described in two rows and along institute
State first direction extension.The gate connection line is connected to the same grid convenient for the grid of multiple thin film transistor (TFT)s and connects as a result,
Mouthful, it is connected to the same source electrode interface convenient for the source electrode of multiple thin film transistor (TFT)s, is also convenient for the drain electrode point of multiple thin film transistor (TFT)s
It is not connected with multiple test interfaces, the cabling in the testing element group more succinctly and conveniently, and compares and saves space, further
Improve the service performance of the testing element group.
According to an embodiment of the invention, the multiple thin film transistor (TFT) is arranged as two rows, extend from the grid interface
Two gate connection lines out, the orthographic projection of the thin film transistor (TFT) on the substrate is with the gate connection line described
There is overlapping region between orthographic projection on substrate；The source connection lines are arranged between two gate connection lines.By
This, further saves space, and cabling is more succinct, further improves the service performance of the testing element group.
In another aspect of this invention, the invention proposes a kind of array substrates.According to an embodiment of the invention, the array
Substrate includes: substrate, and viewing area and non-display area are limited on the substrate；And mentioned-above testing element group, institute
Testing element group is stated to be arranged in the non-display area.There is the array substrate mentioned-above testing element group to be had as a result,
The whole features and advantage having, details are not described herein.Generally speaking, the array substrate is being carried out using the testing element group
When electrical performance testing, multiple thin film transistor (TFT)s can be detected every time, improve testing efficiency, and test can be improved
Accuracy.
In still another aspect of the invention, the invention proposes a kind of display devices.According to an embodiment of the invention, described aobvious
Showing device includes mentioned-above array substrate.The display device has complete possessed by mentioned-above array substrate as a result,
Portion's feature and advantage, details are not described herein.
In still another aspect of the invention, electrical property is carried out using mentioned-above testing element group the invention proposes a kind of
The method that can be tested.According to an embodiment of the invention, this method comprises: a test interface is based on, to multiple described thin
The grid of film transistor applies gate voltage, to detect to multiple thin film transistor (TFT)s.This method single can measure as a result,
Multiple thin film transistor (TFT)s improve testing efficiency, and improve test accuracy.
According to an embodiment of the invention, the method further includes: it is based on a test interface, to the grid
The source electrode input test signal for the multiple thin film transistor (TFT)s being connected with the same test interface.Thus, it is possible into one
Step improves testing efficiency.
Detailed description of the invention
Above-mentioned and/or additional aspect of the invention and advantage will become from the description of the embodiment in conjunction with the following figures
Obviously and it is readily appreciated that, in which:
Fig. 1 shows the structural schematic diagram of testing element group according to an embodiment of the invention；
Fig. 2 shows the structural schematic diagram of the testing element group of the prior art；
Fig. 3 shows the structural schematic diagram of thin film transistor (TFT) according to an embodiment of the invention；
Fig. 4 shows the structural schematic diagram of testing element group in accordance with another embodiment of the present invention；
Fig. 5 shows the structural schematic diagram of the testing element group of another embodiment according to the present invention；
Fig. 6 shows the structural schematic diagram of the testing element group of another embodiment according to the present invention；
Fig. 7 shows the method stream according to an embodiment of the invention that electrical performance testing is carried out using testing element group
Cheng Tu；And
Fig. 8 shows the structural schematic diagram of array substrate according to an embodiment of the invention.
Description of symbols:
100: substrate；200: thin film transistor (TFT)；210: glass substrate；220: grid；230: source electrode；240: drain electrode；250:
Gate insulating layer；260: intrinsic amorphous silicon layer；270: doped amorphous silicon layer；280: insulating protective layer；300: test interface；400:
Gate connection line；500: source connection lines；600: drain bond wires；10: test fingers；1000: testing element group；2300: battle array
Column substrate；2000: substrate；2100: viewing area；2200: non-display area.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and for explaining only the invention, and is not considered as limiting the invention.
In one aspect of the invention, the invention proposes a kind of testing element groups.According to an embodiment of the invention, with reference to
Fig. 1, the testing element group 1000 include: multiple thin film transistor (TFT)s 200 of setting electric connection on the substrate 100 and multiple
Test interface 300, wherein the grid (not shown) of at least two thin film transistor (TFT)s 200 and same 300 phase of test interface
Even (grid of 2 thin film transistor (TFT)s 200A and 200B as illustrated in FIG. 1 pass through gate connection line 400 and the same test
Interface 300A is connected).As a result, when carrying out electrical performance testing to array substrate using the testing element group 1000, Ke Yiti
The utilization rate of high test interface 300 (i.e. testing cushion (PAD)), every time can detect multiple thin film transistor (TFT)s 200, Jin Erjian
The time for surveying certain amount thin film transistor (TFT) 200 can greatly reduce, and improve testing efficiency, and the accurate of test can be improved
Property.
In order to make it easy to understand, can be realized above-mentioned beneficial effect to testing element group according to an embodiment of the present invention below
Principle is described in detail:
As previously mentioned, electricity is surveyed when testing currently with electrical testing equipment (EPM) testing element group (TEG)
The multiple test fingers (Pin) tried on equipment (EPM) are arranged in fixed form, and multiple tests in testing element group (TEG) connect
Mouth (i.e. testing cushion (PAD)) and multiple test fingers (Pin) correspond arrangement, to carry out corresponding detection.Specifically, ginseng
Examine Fig. 2, in testing element group, a thin film transistor (TFT) usually corresponding 4 test interfaces in fixed position arrangement (refer to Fig. 2
Shown in thin film transistor (TFT) 200, test interface 300A, 300B, 300C and 300D), the grid of a thin film transistor (TFT)
(Gate), source electrode (Sourse) and drain electrode (Drain) can be connected to 3 test interfaces (with reference to Fig. 2 by individual lead
Shown, the grid of thin film transistor (TFT) 200 is connected to test interface 300A (i.e. test interface G) by gate connection line 400,
The source electrode of thin film transistor (TFT) 200 is connected to test interface 300C (i.e. test interface S), film crystal by source connection lines 500
The drain electrode of pipe 200 is connected to test interface 300B (i.e. test interface D) by drain bond wires 600), therefore, thin to one
When film transistor carries out electrical testing, the free time goes out a test interface, and (with reference to shown in Fig. 2, the free time goes out test interface
300D), i.e., an idle test fingers (Pin) out.Therefore, current method cannot make full use of test fingers (Pin), and
The number for the thin film transistor (TFT) that single test can be detected is less, and testing efficiency is lower.And test according to an embodiment of the present invention
Element group, by the way that the grid of multiple (i.e. at least two) thin film transistor (TFT)s is connected with the same test interface, subsequent electricity is surveyed
In examination, gate voltage can be applied to the grid of multiple thin film transistor (TFT)s by the same test interface, improve test interface
Utilization rate, multiple thin film transistor (TFT)s can be detected every time, and then the time for detecting certain amount thin film transistor (TFT) can be with
It greatly reduces, improves testing efficiency, and after the number increase of the thin film transistor (TFT) of single detection, it can be to testing every time
The test result of multiple thin film transistor (TFT)s is averaged, so can more accurately reactive film transistor characteristic value, i.e.,
The accuracy of test can be improved.
As previously mentioned, the thin film transistor (TFT) in thin film transistor (TFT) and viewing area in testing element group is by same work
Skill production, film layer structure having the same, therefore, by the characteristic value for the thin film transistor (TFT) tested in the testing element group,
The characteristic value of thin film transistor (TFT) in viewing area can be monitored.According to an embodiment of the invention, with reference to Fig. 3, along Fig. 3
Shown in by D ' to D direction, thin film transistor (TFT) 200 may include the glass substrate 210 set gradually, grid 220, grid
Pole insulating layer 250, intrinsic amorphous silicon layer 260, doped amorphous silicon layer 270, source electrode 230 and 240 (same layers) of drain electrode and insulation are protected
Sheath 280.According to an embodiment of the invention, grid 220 can pass through gate connection line (not shown) and test interface phase
Even, source electrode 230 can be connected by source connection lines (not shown) with test interface, and drain electrode 240 can be connected by drain electrode
Wiring (not shown) is connected with test interface.
According to an embodiment of the invention, with reference to Fig. 4, the grid (not shown) of at least two thin film transistor (TFT)s 200 with
The same test interface 300A is connected, the source electrode (not shown)s of at least two thin film transistor (TFT)s 200 can also with it is same
Test interface 300B is connected.The source electrode (not shown) of at least two thin film transistor (TFT)s 200 also connects with the same test as a result,
After mouth 300B is connected, the utilization rate of test interface 300 can be further improved, further increase detectable thin in single test
The number of film transistor 200, further increases testing efficiency.Specifically, the drain electrode of multiple thin film transistor (TFT)s can be respectively and surplus
Remaining test interface is connected, and (as illustrated in FIG. 4, the grid of 2 thin film transistor (TFT)s is connected with test interface 300A, 2 films
The source electrode of transistor is connected with test interface 300B, the drain electrode of 2 thin film transistor (TFT)s respectively with test interface 300C and 300D
It is connected), therefore, in testing element group according to an embodiment of the present invention, not idle test interface, in subsequent electrical testing
In also not idle test fingers (Pin).Therefore, testing element group according to an embodiment of the present invention can make full use of test
The number of stitch (Pin), the thin film transistor (TFT) that single test can be detected is more, and testing efficiency is higher.Specifically, subsequent electricity
In test, identical gate voltage can be applied to multiple thin film transistor (TFT)s 200, the source electrode of multiple thin film transistor (TFT)s can also input
Identical test signal, the drain electrode of each thin film transistor (TFT) 200 is connected with a test interface 300, thus multiple film crystals
The test signal of drain electrode input or the output of pipe is not identical, and then can detect to the characteristic value of each thin film transistor (TFT).
According to an embodiment of the invention, the multiple grids (i.e. multiple thin film transistor (TFT)s) being connected with the same test interface
Specific number is not particularly limited, and those skilled in the art, which can according to need, to be designed, for example, can be 2,4,6
It is a, 8,10,12 etc..According to an embodiment of the invention, the multiple source electrodes being connected with the same test interface are (i.e. multiple thin
Film transistor) specific number be not particularly limited, those skilled in the art, which can according to need, to be designed, such as can be
2,4,6,8,10,12 etc..
According to an embodiment of the invention, test interface 300 may include grid interface G, source electrode interface S and drain junction
D is connected to multiple source electrodes of multiple thin film transistor (TFT)s of the same grid interface G, can be connected with the same source electrode interface S.
It is convenient for cabling (company when " cabling " connects the grid, source electrode and drain electrode of multiple thin film transistor (TFT)s with test interface as a result,
Wiring design and arrangement), and mentioned-above multiple thin film transistor (TFT)s are detected convenient for test equipment single, further
Improve testing efficiency.It should be noted that when carrying out electrical performance testing to thin film transistor (TFT), each thin film transistor (TFT)
Grid, source electrode and drain electrode require to be connected to test interface corresponding with test fingers, therefore, are connected to the same grid and connect
Multiple source electrodes of multiple thin film transistor (TFT)s of mouthful G, can be in the electrical testing of single after being connected with the same source electrode interface S
Mentioned-above multiple thin film transistor (TFT)s are tested together, it is easy to operate, and be conducive to cabling.
According to an embodiment of the invention, the number for the test interface for including in testing element group is not particularly limited, specifically
Test interface number can be with the number phase of the test fingers of the electrical testing equipment detected to the testing element group
Match, for example, the testing element group may include 4 test interfaces when having 4 test fingers in test equipment；Test equipment
In have 12 test fingers when, which may include 12 test interfaces.
According to an embodiment of the invention, the grid of multiple thin film transistor (TFT)s in testing element group can be connected to one
The source electrode of grid interface, multiple thin film transistor (TFT)s in testing element group can be connected to a source electrode interface.Thus, it is possible to
The utilization rate for largely improving test interface improves the number of the thin film transistor (TFT) of single test, further increases test
Efficiency, and improve test accuracy.
According to a particular embodiment of the invention, with reference to Fig. 5, there are 4 test interfaces 300, i.e., in testing element group 1000
Grid interface G, source electrode interface S, drain junction D1 and drain junction D2, the grid of 2 thin film transistor (TFT)s 200A and 200B are equal
It is connected to grid interface G by gate connection line 400,2 thin film transistor (TFT) 200A pass through source electrode with the source electrode of 200B and connect
Line 500 is connected to source electrode interface S, and the drain electrode of thin film transistor (TFT) 200A is connected to drain junction D1 by drain bond wires 600A,
The drain electrode of thin film transistor (TFT) 200B is connected to drain junction D2 by drain bond wires 600B, as a result, comparison diagram 2 and Fig. 5, such as
Preceding described, in existing testing element group, 4 test interfaces can only correspond to one thin film transistor (TFT) of test, and according to the present invention
In the testing element group of specific embodiment, 4 test interfaces can correspond to 2 thin film transistor (TFT)s of test, as a result, according to the present invention
The testing element group of embodiment improves the utilization rate of test interface, improves the number of the thin film transistor (TFT) of single test, mentions
High testing efficiency.
According to an embodiment of the invention, multiple thin film transistor (TFT)s 200 can arrange (first party along first direction with reference to Fig. 6
To the direction AA ' shown in reference Fig. 6), multiple test interfaces 300 can be arranged on the two sides of multiple thin film transistor (TFT)s 200
And two rows are arranged in along first direction, extend gate connection line 400 from grid interface G, gate connection line 400 is arranged two
Between row test interface 300 and extend in a first direction；Extend source connection lines 500, source connection lines from source electrode interface S
500 are arranged between two row test interfaces 300 and extend in a first direction, and the drain electrode of multiple thin film transistor (TFT)s 200 can pass through
Drain bond wires 600 are connected with multiple drain junction D respectively (refers to the leakage of 10 thin film transistor (TFT)s 200 shown in Fig. 6
Pole passes through drain bond wires 600 respectively and is connected with drain junction D1, D2, D3, D4, D5, D6, D7, D8, D9 and D10).As a result,
Gate connection line 400 is connected to the same grid interface G convenient for the grid of multiple thin film transistor (TFT)s 200, and source connection lines 500 are just
Be connected to the same source electrode interface S in the source electrode of multiple thin film transistor (TFT)s 200, the drain electrode of multiple thin film transistor (TFT)s respectively with it is multiple
Drain junction D is connected, and the cabling in the testing element group 1000 more succinctly and conveniently, and compares and saves space, further mentions
The high service performance of the testing element group 1000.According to an embodiment of the invention, the setting of grid interface G and source electrode interface D
Position is not particularly limited, for example, as illustrated in FIG. 6, grid interface G and source electrode interface D are arranged in multiple thin film transistor (TFT)s
Two sides, and one end of the testing element group is set, thus, it is possible to further facilitate cabling.
According to an embodiment of the invention, with reference to Fig. 6, multiple thin film transistor (TFT)s 200 can be arranged as two rows, from grid interface
Extend two gate connection lines 400 at G, the orthographic projection of thin film transistor (TFT) 200 on the substrate 100 and gate connection line 400 exist
There is overlapping region, source connection lines 500 are arranged between two gate connection lines 400 between orthographic projection on substrate 100.By
This, further saves space, and cabling is more succinct, further improves the service performance of the testing element group.It needs
Illustrate, at present when making array substrate, the narrower the non-display area on viewing area periphery the better, therefore, is located at viewing area
Space shared by the testing element group of surrounding is also the smaller the better, and therefore, inventor is had found by numerous studies, in testing element group
Thin film transistor (TFT), test interface and connecting line mode as described above when designing and arranging, can preferably save
Space further improves the service performance of the testing element group.
According to a particular embodiment of the invention, with reference to Fig. 7, when carrying out electrical performance testing using electrical devices, electricity
Test equipment has 12 test fingers 10, and 12 in the arrangement mode of 12 test fingers 10 and the testing element group
The arrangement mode of test interface 300 is identical, and corresponds, and Fig. 6 and Fig. 7 is referred to as a result, in the electrical performance testing of single
In, 12 test fingers 10 can detect 10 thin film transistor (TFT)s, greatly improve the film crystal of single test
(if existing test interface and connection type with reference to shown in Fig. 2, in single test, 12 are surveyed the number of pipe
Test point foot can only detect 3 thin film transistor (TFT)s, and it is idle for having 3 test interfaces), testing efficiency is improved, and
After the thin film transistor (TFT) number increase of single test, average to the test result for the multiple thin film transistor (TFT)s tested every time,
The average value can more accurately reactive film transistor characteristic value, that is, the accuracy of test can be improved.
In summary, electric property survey is carried out to array substrate using testing element group 1000 according to an embodiment of the present invention
When examination, the utilization rate of test interface can be improved, multiple thin film transistor (TFT)s can be detected every time, and then detect certain amount
The time of thin film transistor (TFT) can greatly reduce, and improve testing efficiency, and the accuracy of test can be improved.
In another aspect of this invention, the invention proposes a kind of array substrates.According to an embodiment of the invention, with reference to figure
8, which includes: substrate 2000 and mentioned-above testing element group 1000, is limited on substrate 2000 aobvious
Show area 2100 and non-display area 2200, testing element group 1000 is arranged in non-display area 2200.The array substrate as a result,
2300 have the advantages that whole feature possessed by mentioned-above testing element group 1000 and, details are not described herein.Total comes
It says, it, every time can be to multiple films when carrying out electrical performance testing to the array substrate 2300 using the testing element group 1000
Transistor is detected, and testing efficiency is improved, and the accuracy of test can be improved.
According to an embodiment of the invention, array substrate may include multiple testing element groups 1000, and multiple testing elements
The distribution of group 1000 and arrangement mode are not particularly limited, for example, multiple testing element groups can be distributed in display with reference to Fig. 8
The surrounding in area 2100, multiple thin film transistor (TFT)s and multiple test interface (not shown)s in testing element group 1000 can be with
The direction BB ' shown in Fig. 8 arranges, and can also arrange along the direction CC ' shown in Fig. 8.
In still another aspect of the invention, the invention proposes a kind of display devices.According to an embodiment of the invention, the display
Device includes mentioned-above array substrate.The display device has possessed by mentioned-above array substrate all as a result,
Feature and advantage, details are not described herein.
In still another aspect of the invention, electrical property is carried out using mentioned-above testing element group the invention proposes a kind of
The method that can be tested.The testing element group in this method has all special possessed by mentioned-above testing element group as a result,
Sign and advantage, details are not described herein.As previously mentioned, being surveyed by the testing element group in the non-display area to array substrate
Examination, that is, can determine whether the performance of the thin film transistor (TFT) in viewing area.According to an embodiment of the invention, this method comprises: being based on one
Test interface applies gate voltage to the grid of multiple thin film transistor (TFT)s, to detect to multiple thin film transistor (TFT)s.Such as preceding institute
It states, the grid of multiple thin film transistor (TFT)s can connect to a test interface, as a result, by being connected to the surveys of multiple grids to this
Mouth of trying is detected, can the multiple thin film transistor (TFT)s of single measurement, and then improve testing efficiency, and it is quasi- to improve test
True property.
According to an embodiment of the invention, this method further comprises: a test interface is based on, to grid and the same survey
The source electrode input test signal of the connected multiple thin film transistor (TFT)s of mouth of trying.As previously mentioned, grid and the same test interface phase
The source electrodes of multiple thin film transistor (TFT)s also can connect to the same test interface, as a result, by being connected to multiple sources to this
The test interface of pole is detected, can the multiple thin film transistor (TFT)s of single measurement, so as to further improve testing efficiency.
As previously mentioned, in electrical testing identical gate voltage, the source of multiple thin film transistor (TFT)s can be applied to multiple thin film transistor (TFT)s
Pole can also input identical test signal, and the drain electrode of each thin film transistor (TFT) can be connected with a test interface, thus more
The test signal of drain electrode input or the output of a thin film transistor (TFT) is not identical, and then can be to the characteristic value of each thin film transistor (TFT)
It is detected.
According to a particular embodiment of the invention, with reference to Fig. 6 and Fig. 7, in the testing needle using electrical testing equipment (EPM)
Foot 10 to multiple test interfaces 300 carry out electrical testing when, can first to source electrode interface S and multiple drain junction D1-D10 it
Between apply certain voltage so that forming the electrical circuit that can be connected between the source electrode and drain electrode of multiple thin film transistor (TFT)s then can
To apply scanning voltage to grid interface G, keep voltage slowly varying, be gradually turned between source electrode and drain electrode, during detection is somebody's turn to do
Drain current-Gate Voltage curve, and then the characteristic value of thin film transistor (TFT) is judged.And it is possible to measuring simultaneously
The characteristic values of 10 thin film transistor (TFT)s average, and then can more accurately measure the property of thin film transistor (TFT).
In the description of the present invention, the orientation or positional relationship of the instructions such as term " on ", "lower" "horizontal", "vertical" is base
In orientation or positional relationship shown in the drawings, it is merely for convenience of the description present invention rather than requires the present invention must be with specific
Orientation construction and operation, therefore be not considered as limiting the invention.
In the description of this specification, the description of reference term " one embodiment ", " another embodiment " etc. means to tie
The embodiment particular features, structures, materials, or characteristics described are closed to be included at least one embodiment of the present invention.At this
In specification, the schematic representation of the above terms does not necessarily have to refer to the same embodiment or example.Moreover, the tool of description
Body characteristics, structure, material or feature may be combined in any suitable manner in any one or more of the embodiments or examples.This
Outside, without conflicting with each other, those skilled in the art by different embodiments described in this specification or can show
The feature of example and different embodiments or examples is combined.In addition, it is necessary to illustrate, in this specification, term
" first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicate meaning
The quantity of the technical characteristic shown.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, modifies, replacement and variant.
Claims (10)
1. a kind of testing element group characterized by comprising
The multiple thin film transistor (TFT)s and multiple test interfaces for the electric connection being disposed on the substrate, wherein described at least two
The grid of thin film transistor (TFT) is connected with the same test interface.
2. testing element group according to claim 1, which is characterized in that the source electrode of at least two thin film transistor (TFT)s with
The same test interface is connected.
3. testing element group according to claim 1, which is characterized in that the test interface includes grid interface, source electrode
Interface and drain junction are connected to multiple source electrodes of multiple thin film transistor (TFT)s of the same grid interface,
It is connected with the same source electrode interface.
4. testing element group according to claim 3, which is characterized in that multiple films in the testing element group
The grid of transistor is connected to the grid interface,
The source electrode of multiple thin film transistor (TFT)s in the testing element group is connected to the source electrode interface.
5. testing element group according to claim 4, which is characterized in that multiple thin film transistor (TFT)s are arranged along first direction
Column, multiple test interfaces are arranged on the two sides of multiple thin film transistor (TFT)s and are arranged in two rows along the first direction,
Extend gate connection line, between the test interface described in the two rows and edge of gate connection line setting from the grid interface
The first direction extends；
Extend source connection lines from the source electrode interface, the source connection lines setting is between the test interface described in two rows
And extend along the first direction.
6. testing element group according to claim 5, which is characterized in that the multiple thin film transistor (TFT) is arranged as two rows,
Extend two gate connection lines from the grid interface, the orthographic projection of the thin film transistor (TFT) on the substrate with
There is overlapping region between the orthographic projection of the gate connection line on the substrate；
The source connection lines are arranged between two gate connection lines.
7. a kind of array substrate characterized by comprising
Substrate limits viewing area and non-display area on the substrate；And
Testing element group described in any one of claims 1-6, the testing element group are arranged in the non-display area.
8. a kind of display device, which is characterized in that the display device includes array substrate as claimed in claim 7.
9. a kind of method for carrying out electrical performance testing using testing element group described in any one of claims 1-6, feature
It is, comprising:
Based on a test interface, gate voltage is applied to the grid of multiple thin film transistor (TFT)s, to multiple described thin
Film transistor is detected.
10. according to the method described in claim 9, it is characterized in that, the method further includes:
Based on a test interface, multiple film crystals for being connected to the grid with the same test interface
The source electrode input test signal of pipe.
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| CN110335560A (en) * | 2019-07-23 | 2019-10-15 | 云谷（固安）科技有限公司 | The electric test method of array substrate, display panel and array substrate |
| CN111292661A (en) * | 2020-03-30 | 2020-06-16 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| WO2020220531A1 (en) * | 2019-04-30 | 2020-11-05 | 深圳市华星光电半导体显示技术有限公司 | Array substrate row driving circuit and display panel |
| CN112201186A (en) * | 2020-10-10 | 2021-01-08 | 深圳市华星光电半导体显示技术有限公司 | Test component group |
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