CN107068696A - A kind of preparation method of array base palte and array base palte - Google Patents
A kind of preparation method of array base palte and array base palte Download PDFInfo
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- CN107068696A CN107068696A CN201710420077.8A CN201710420077A CN107068696A CN 107068696 A CN107068696 A CN 107068696A CN 201710420077 A CN201710420077 A CN 201710420077A CN 107068696 A CN107068696 A CN 107068696A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 238000012360 testing method Methods 0.000 claims abstract description 400
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 10
- 230000005669 field effect Effects 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
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- 238000000926 separation method Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 3
- 239000010408 film Substances 0.000 claims description 2
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- 239000002699 waste material Substances 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 description 9
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- 238000003698 laser cutting Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
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- 238000005259 measurement Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The embodiment of the invention discloses the preparation method of a kind of array base palte and array base palte.The array base palte includes：Viewing area and the non-display area positioned at viewing area periphery, the first test cell, the second test cell and testing weld pad are provided with non-display area, wherein, the source electrode of first test cell and the second test cell is connected to same testing weld pad, grid is connected to same testing weld pad, and drain electrode is connected to different testing weld pads；First test cell is used to test the electrical parameter performance of TFT；Second test cell is used to test the gate driving circuit of non-display area.During the embodiment of the present invention is solved by the way of the existing test structure hot-wire array substrate, due to needing the special monitor area for being provided for testing GOA characteristics, and the problem of cause to waste substrate space, and cause the problem of product yield is relatively low due to GOA characteristics can not be monitored in subsequent technique.
Description
Technical field
The application relates to, but are not limited to display technology field, the preparation method of espespecially a kind of array base palte and array base palte.
Background technology
As display technology develops and updates, in the market occurs in that polytype display.Array base palte is
The primary structure of display, demand carries out dependence test to it to ensure the product of display in the manufacturing process of array base palte
Yield.
The development trend of display is that product is more and more frivolous, and frame is more and more narrow, and peripheral wiring region can be more next therewith
It is narrower, with gate driving circuit in display product (Gate Driver on Array, referred to as：GOA) bad occurred frequently,
The test of current array substrate mainly includes：TFT (Thin Film Transistor, referred to as：
TFT (Electrical Parameter Monitor are referred to as electrical parameter performance)：EPM) test and GOA tests.It is existing
Test structure in technology includes：Placed in the non-display area of the independent display unit (Single Cell) of substrate for surveying
(Test Element Group are referred to as examination TFT EPM test suite：TFG), i.e. EPM TEG, are set special in a substrate
Monitor area (Dummy areas) for placing GOA TEG, i.e., test EPM characteristics by independent test suite and GOA be special respectively
Property.However, there is problems with using the test suite for being used to test TFT EPM characteristics and GOA characteristics in the prior art：One side
Face, GOA TEG need to be arranged on the Dummy areas of whole substrate, can take space more on substrate；On the other hand, follow-up work
Dummy areas are cut out when substrate being cut into independent display unit formation modular structure in skill, it is impossible to monitored in subsequent technique
GOA characteristics and cause the problem of product yield is relatively low, so as to cause damage.
In summary, in by the way of the existing test structure hot-wire array substrate, due to needing special to be provided for surveying
The problem of trying the monitor area of GOA characteristics, and cause to waste substrate space；Further, since GOA can not be monitored in subsequent technique
Characteristic and cause the problem of product yield is relatively low.
The content of the invention
In order to solve the above-mentioned technical problem, the embodiments of the invention provide the making side of a kind of array base palte and array base palte
Method, in solving by the way of the existing test structure hot-wire array substrate, due to needing special to be provided for testing GOA characteristics
Monitor area, and the problem of cause to waste substrate space, and caused due to GOA characteristics can not be monitored in subsequent technique
The problem of product yield is relatively low.
The embodiment of the present invention provides a kind of array base palte, including：
The first test list is provided with viewing area and the non-display area positioned at the viewing area periphery, the non-display area
Member, the second test cell and testing weld pad, wherein, the source electrode of first test cell and second test cell is connected to
Same testing weld pad, grid is connected to same testing weld pad, and drain electrode is connected to different testing weld pads；
First test cell is used to test the electrical parameter performance of TFT；
Second test cell is used to test the gate driving circuit of the non-display area.
Alternatively, in array base palte as described above, first test cell is used for TFT
Electrical parameter performance is tested, including：
Add the scanning voltage of preset range by the grid to first test cell, electricity is fixed to drain electrode and source electrode
Pressure, tests the curent change of the drain electrode and the source electrode.
Alternatively, in array base palte as described above, first test cell is TFT, and described
First test cell is identical with the structure and electrical parameter performance of the TFT of the viewing area.
Alternatively, in array base palte as described above, source electrode, grid and the drain electrode of each test cell are connected to not
Same testing weld pad.
Alternatively, in array base palte as described above, it is single that second test cell includes following one or more tests
Member：First test subelement, the second test subelement and the 3rd test subelement；
Wherein, the thin film field-effect charged when the first test subelement is work by forward scan to high potential point
Transistor；
The thin film field-effect crystal that the second test subelement is charged when being work by reverse scan to high potential point
Pipe；
The TFT that the 3rd test subelement charges when being work to output.
Alternatively, in array base palte as described above, the first testing weld pad connect respectively first test cell and
The source electrode of the first test subelement, the second test subelement and the 3rd test subelement, the second testing weld pad
First test cell and the first test subelement, the second test subelement and the 3rd survey are connected respectively
The grid of swab unit；
3rd testing weld pad includes the first sub- pad and the second sub- pad of separation, and the 4th testing weld pad includes the of separation
Three sub- pads and the 4th sub- pad, the first sub- pad, the second sub- pad, the 3rd sub- pad and the 4th son
Pad connect correspondingly first test cell and it is described first test subelement, it is described second test subelement and
The drain electrode of the 3rd test subelement.
Alternatively, in array base palte as described above, the first test subelement, the second test subelement and institute
The channel width-over-length ratio for stating the 3rd test subelement is different.
The embodiment of the present invention also provides a kind of preparation method of array base palte, including：
Gate metal layer is formed in the viewing area of substrate and on the non-display area on the viewing area periphery；
The part gate metal layer is removed, the gate patterns of TFT and institute in the viewing area is formed
State the gate patterns of test cell in non-display area；
Insulating barrier is formed on the substrate and the gate patterns, partial insulative layer is removed with exposed portion grid figure
Shape；
Amorphous silicon layer is formed on the insulating barrier and the gate patterns, the part amorphous silicon layer is removed, institute is formed
State the active layer pattern of TFT and the test cell；
Metal level is formed on the insulating barrier and the active layer pattern, and removes partial metal layers and forms the film
Field-effect transistor and the source electrode figure of the test cell and drain patterns；
Wherein, the test cell includes the first test cell and the second test cell, first test cell and institute
The source electrode for stating the second test cell is connected to same testing weld pad, and grid is connected to same testing weld pad, and drain electrode is connected to
Different testing weld pads.
Alternatively, in the preparation method of array base palte as described above, first test cell is used to imitate thin film field
The electrical parameter performance of transistor is answered to be tested；First test cell and the TFT of the viewing area
Structure it is identical with electrical parameter performance；
Second test cell is used to test the gate driving circuit of the non-display area.
Alternatively, in the preparation method of array base palte as described above, source electrode, grid and the leakage of each test cell
Pole is connected to different testing weld pads.
Set in the preparation method of array base palte and array base palte provided in an embodiment of the present invention, the non-display area of array base palte
It is equipped with the first test cell, the second test cell and testing weld pad, and the source electrode of the first test cell and the second test cell
Same testing weld pad is connected to, grid is connected to same testing weld pad, and drain electrode is connected to different testing weld pads, wherein,
First test cell (EPM TEG) is used to test TFT electrical parameter performance, and the second test cell (GOA TEG) is used
Tested in the GOA to non-display area.Technical scheme provided in an embodiment of the present invention, by EPM TEG's of the prior art
Structure is re-designed as：Pass through EPM TEG and GOA TEG common-sources and the testing weld pad of grid, the different tests of drain electrode connection
Pad, so as to realize the integrated GOA TEG in EPM TEG, the structure of the array base palte is reduced needed for test suite
Space, without GOA TEG are placed in the monitor area of whole substrate, can be placed in non-display area, that is, save in base
The space of monitor area is set in plate；In addition, can be not only monitored in subsequent technique to the TFT characteristics of viewing area, also
The GOA characteristics of non-display area can be monitored and be intercepted with bad, be conducive to improving product yield.
Brief description of the drawings
Accompanying drawing is used for providing further understanding technical solution of the present invention, and constitutes a part for specification, with this
The embodiment of application is used to explain technical scheme together, does not constitute the limitation to technical solution of the present invention.
Fig. 1 is a kind of schematic diagram of EPM TEG set locations in array base palte in the prior art；
Fig. 2 is a kind of EPM TEG structural representation in the prior art；
Fig. 3 is a kind of GOA TEG structural representation in the prior art；
Fig. 4 is the structural representation of another GOA TEG in the prior art；
Fig. 5 is the structural representation of another GOA TEG in the prior art；
Fig. 6 is a kind of structural representation of array base palte provided in an embodiment of the present invention；
Fig. 7 is a kind of structural representation of test cell of array base palte provided in an embodiment of the present invention；
Fig. 8 is the structural representation of another test cell of array base palte provided in an embodiment of the present invention；
Fig. 9 is the flow chart of the preparation method of array base palte provided in an embodiment of the present invention；
Figure 10 is a schematic cross-section in the manufacturing process of array base palte shown in Fig. 9；
Figure 11 is another schematic cross-section in the manufacturing process of array base palte shown in Fig. 9；
Figure 12 is another schematic cross-section in the manufacturing process of array base palte shown in Fig. 9.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with accompanying drawing to the present invention
Embodiment be described in detail.It should be noted that in the case where not conflicting, in the embodiment and embodiment in the application
Feature can mutually be combined.
The test of array substrate includes：TFT EPM are tested and GOA tests.Fig. 1 is a kind of EPM TEG in the prior art
The schematic diagram of set location in array base palte, Fig. 2 is a kind of EPM TEG structural representation in the prior art, and Fig. 3 is existing
A kind of GOA TEG structural representation in technology, Fig. 4 is the structural representation of another GOA TEG in the prior art, and Fig. 5 is
Another GOA TEG structural representation in the prior art.
TFT EPM TEG placement location is can be seen that from Fig. 1 and Fig. 2 in array base palte (i.e. Single Cell)
, can be by testing the characteristic of TFT in EPM TEG monitoring displays area in the non-display area of non-display area.Can from Fig. 3 to Fig. 5
To find out, the placement location of the GOA TEG for testing GOA characteristics is monitor area, and test is needed during due to measurement GOA characteristics
TFG it is more, such as including the GOA M3 in the GOA M2 and Fig. 5 in GOA M1, Fig. 4 in Fig. 3, due to GOA TEG need
Take more space and can not be positioned in the non-display area of array base palte, therefore, prior art is set on whole substrate
Dedicated for placing GOA TEG monitor area (Dummy areas), so, space more on substrate can be taken, waste substrate empty
Between；In addition, for the GOA TEG for being positioned over monitor area, subsequent technique needs whole substrate being cut into Single Cell
Form issuable following various situations after modular structure, cutting Single Cell：Monitor area does not keep sample, or destruction prison
Region samples overall structure is controlled, or sample Single Cell tear high-temperature heating and instrument sled angle during shielding open and easily GOA are caused
Destruction；The generation of above-mentioned situation all will be unable to be monitored GOA characteristics, therefore, monitor area is positioned in the prior art
GOA TEG can not monitor GOA characteristics in subsequent technique and cause the problem of product yield is relatively low.
As can be seen that EPM TEG and GOA TEG are respectively provided with four testing weld pads in from Fig. 1 to Fig. 5, wherein three tests
Pad connects the source electrode, grid and drain electrode of some test suite correspondingly, and also one testing weld pad is not used, and is
Idle state.Test suite of the prior art not only wastes substrate space, also wastes the space in test suite, does not have
Make full use of each testing weld pad in test suite.
The present invention provides following specific embodiment and can be combined with each other, for same or analogous concept or process
It may be repeated no more in some embodiments.
Fig. 6 is a kind of structural representation of array base palte provided in an embodiment of the present invention, and Fig. 7 provides for the embodiment of the present invention
Array base palte a kind of test cell structural representation.The array base palte that the present embodiment is provided, can include：
The first test cell is provided with viewing area 10 and the non-display area 20 positioned at the periphery of viewing area 10, non-display area 20
210th, the second test cell 220 and testing weld pad 230, wherein, the source electrode of the first test cell 210 and the second test cell 220
Source electrode be connected to same testing weld pad 231, the grid of the grid of the first test cell 210 and the second test cell 220 connects
Same testing weld pad 232 is connected to, the drain electrode of the first test cell 210 and the drain electrode of the second test cell 220 are connected to difference
Testing weld pad, the drain electrode of such as the first test cell 210 is connected to testing weld pad 233, and the drain electrode of the second test cell 220 connects
It is connected to testing weld pad 234.
Array base palte of the prior art, it is same to include being used for effective luminous zone that display screen carries out normal display function
(Active Area, referred to as：AA), i.e. viewing area 10, the periphery of the viewing area 10 can be provided with non-display area 20, and this is non-aobvious
Show and test suite is usually provided with area 20, such as, including the EPM TEG for testing TFT characteristics, the non-display area 20 is also set
It is equipped with GOA.
In array base palte provided in an embodiment of the present invention, the first test cell 210 and second is provided with non-display area 20
Test cell 220, wherein, the first test cell 210 is used to test TFT electrical parameter performance, the second test cell
220 are used to test the GOA of non-display area 20.Thin Film Transistor-LCD (Thin Film Transistor-
Liquid Crystal Display, referred to as：TFT-LCD) production industry due to design and processes some shortcoming, fluctuation or
Person's environmental condition difference etc. causes technological fluctuation, may result in TFT characteristics and there is exception, it is therefore desirable to TFT characteristics are carried out real
When monitoring, evade bad, therefore, the first test cell 210 placed in non-display 20；Further, since field of display
Middle product G OA characteristics it is bad occurred frequently the problem of, such as interlacing is shown, multi outputs, high current etc. is special to GOA in display
The monitoring of property is particularly important.
Compared with test structure of the prior art, the test suite in non-display area 20 not only includes of the prior art
EPM TEG (i.e. the first test cell 210), in addition to for testing the GOA TEG (i.e. the second test cell 220) of GOA characteristics,
And above-mentioned two groups of test cells (i.e. the first test cell 210 and the second test cell 220) are arranged in same test suite；
In the specific implementation, the embodiment of the present invention is to EPM TEG design method：GOA TEG are added inside EPM TEG, i.e.,
The testing weld pad of first test cell 210 and the common grid of the second test cell 220 and source electrode, the first test cell 210 and
The different testing weld pad of two test cells 220 drain electrode connection, so, can be integrated in same survey by EPM TEG and GOA TEG
Try in structure.Design in the embodiment of the present invention, can monitor GOA characteristics while TFT EPM characteristics are monitored, and
The special monitor area for placing GOA TEG need not be set, can greatly reduce GOA TEG and take the space of substrate and ask
Topic, it is to avoid the waste of substrate space.
It should be noted that in the array base palte of the embodiment of the present invention, each test cell (i.e. the first test cell 210
Or second test cell 220) source electrode, drain and gate be connected to different testing weld pads, the tests letter different for receiving
Number, so as to test TFT characteristics or GOA characteristics.In addition, the structure of the first test cell 210 or the second test cell 220 is all
TFT, also, the first test cell 210 is identical with the structure and electrical parameter performance of the TFT in viewing area 10, in viewing area 10
TFT be TFT for control display screen pixel switch, can by the test to the first test cell 210 in non-display area 20
To embody the characteristic of TFT in viewing area 10.
The first test cell, the second test list are provided with array base palte provided in an embodiment of the present invention, its non-display area
Member and testing weld pad, and the source electrode of the first test cell and the second test cell is connected to same testing weld pad, and grid connects
It is connected to same testing weld pad, drain electrode is connected to different testing weld pads, wherein, the first test cell (EPM TEG) is used for pair
TFT electrical parameter performance is tested, and the second test cell (GOA TEG) is used to test the GOA of non-display area.This
The array base palte that inventive embodiments are provided, EPM TEG of the prior art structure is re-designed as：By EPM TEG and
The testing weld pad of GOA TEG common-sources and grid, the different testing weld pads of drain electrode connection, so as to realize in EPM TEG
Integrated GOA TEG, the structure of the array base palte reduces the space needed for test suite, without GOA TEG are placed on into whole
It in the monitor area of substrate, can be placed in non-display area, that is, save the space that monitor area is set in a substrate；In addition,
The TFT characteristics of viewing area can be not only monitored, the GOA characteristics of non-display area can also be supervised in subsequent technique
Control and bad interception, are conducive to improving product yield.
Further, in the prior art when carrying out failure analysis, because monitor area is already cut off testing, need
Tear the GOA progress laser cuttings inside screen array substrate open to isolate, cut-out can be caused not thorough or destruction GOA characteristics, and
Parsing is caused to fail.Array base palte provided in an embodiment of the present invention can monitor in time TFT characteristics and GOA characteristics feedback it is bad
Reason, largely improves product yield.In addition, array base palte provided in an embodiment of the present invention is in manufacturing process,
Extra photolithography plate (Mask) and testing weld pad quantity need not be increased, it is only necessary to which the photolithography plate of array substrate non-display area enters
Row modification can be achieved, the complexity without increasing cost and technique.
In embodiments of the present invention, can be to the mode that the first test cell 210 is tested：
The testing needle of test equipment is pricked to the survey in the testing weld pad 231, grid of the source electrode of the first test cell 210 simultaneously
On the testing weld pad of test weld disk 232 and the testing weld pad 233 of drain electrode, and to adding scanning on the grid of the first test cell 210
Voltage, the scanning voltage is, for example, -20~+20V, it is drained on reorder threshold voltage, for example, 15V, the voltage on its source electrode
Can be 0V；Because in the characteristic of TFT pipes, grid adds positive voltage, source electrode and drain electrode are turned on, and TFT pipes are bright, and grid adds negative voltage,
Source electrode and drain electrode disconnect, and TFT pipes do not work, by adding a range of change voltage in grid, the first test cell 210 of monitoring
Size of current between drain electrode and source electrode, whether the change of monitoring current size meets default change curve, so as to confirm to show
Show the electrical parameter performance of TFT in area 10.The first test cell 210 and TFT in viewing area 10 are had been described above in above-described embodiment
Structure it is identical with electrical parameter performance, can be by the result monitoring display area 10 that is tested the first test cell 210
Middle TFT characteristic.
Further, Fig. 8 is the structural representation of another test cell of array base palte provided in an embodiment of the present invention.
On the architecture basics of the above embodiment of the present invention, in the array base palte that the present embodiment is provided, the second test cell 220 can be wrapped
Include following one or more test cells：First test subelement, the second test subelement and the 3rd test subelement.
Wherein, the TFT charged when the first test subelement is work by forward scan to high potential (PU) point；The test
The structure of subelement is identical for example with the structure of the GOA M1 shown in Fig. 3.
The TFT that second test subelement is charged when being work by reverse scan to high potential point；The test subelement
Structure is identical for example with the structure of the GOA M2 shown in Fig. 4.
The TFT that 3rd test subelement charges when being work to output (output)；The structure of the test subelement is for example
It is identical with the structure of the GOA M3 shown in Fig. 5.
Alternatively, in embodiments of the present invention, due to the first test subelement, the second test subelement and the 3rd test
Unit can separately design the structure for GOA M1, GOA M2 and GOA M3, and the channel width-over-length ratio of this three test subelements is led to
Often to be different.
In embodiments of the present invention, the second test subelement 220 can be a test subelement, or multiple surveys
GOA in the combination of swab unit, the first test subelement, the second test subelement and the 3rd test subelement and non-display area 20
Structure it is identical, by first test subelement, second test subelement and the 3rd test subelement test, can monitor
GOA characteristic in non-display area 20.Wherein, filled when the first test subelement is GOA normal works by forward scan to PU points
The TFT of electricity, the TFT that the second test subelement is charged when being GOA normal works by reverse scan to PU points, the 3rd test is single
TFT when member is GOA normal works to output charging；For example, if array base palte is arranged in smart mobile phone, forward direction is swept
It can be to be scanned from the top of mobile phone display screen to lowermost end to retouch, reverse scan can be from the lowermost end of mobile phone display screen to
Top is scanned.
Alternatively, in embodiments of the present invention, if the second test cell 220 includes the first test subelement, the second test
Subelement and the 3rd test subelement, concrete structure is as shown in figure 8, the first testing weld pad 231 connects the first test cell respectively
210 and first test subelement, second test subelement and the 3rd test subelement source electrode, the second 232 points of testing weld pad
The grid of the first test cell 210 and the first test subelement, the second test subelement and the 3rd test subelement is not connected；
3rd testing weld pad 233 includes the first sub- sub- pad 233b of pad 233a and second of separation, the 4th testing weld pad
234 include the 3rd sub- sub- pad 234b of pad 234a and the 4th of separation, the first sub- pad 233a, the second sub- pad 233b, the
The one-to-one test subelements of the first test cell of connection 210 and first of the three sub- sub- pad 234b of pad 234a and the 4th,
The drain electrode of second test subelement and the 3rd test subelement.
Array base palte provided in an embodiment of the present invention, is welded by the test of EPM TEG and GOA TEG common grids and source electrode
Disk, is redesigned, the testing weld pad that will be drained is divided into two by single, and cut zone is in gold to drain electrode testing weld pad
More than category layer carve and open, that is to say, that on the basis of test structure shown in Fig. 2, by original drain pad and idle pad
Two pads are divided into, due to the first test cell and the first test subelement, the second test subelement and the 3rd test
The source electrode of subelement can share a testing weld pad (i.e. the first testing weld pad 231), and grid can share a testing weld pad
(i.e. the second testing weld pad 232), two other testing weld pad is divided into after four independent sub- pads, can be single by four tests
The drain electrode one of member (i.e. the first test cell, and the first test subelement, the second test subelement and the 3rd test subelement)
One it is corresponding be connected on four sub- pads so that meet to this four test monitoring test.
As shown in figure 8, testing needle is pricked in the first testing weld pad 231, the second testing weld pad 232 and the first sub- pad 233a
When, for testing the first test cell 210, that is, test the TFT characteristics of viewing area 10；Testing needle prick the first testing weld pad 231,
Second testing weld pad 232 and during the second sub- pad 233b, tests subelement for testing first, that is, tests GOA M1 characteristic；
Testing needle is pricked in the first testing weld pad 231, the second testing weld pad 232 and the 3rd sub- pad 234a, is tested for testing second
Subelement, that is, test GOA M2 characteristic；Testing needle is pricked in the first testing weld pad 231, the second testing weld pad 232 and the 4th son weldering
During disk 234b, subelement is tested for testing the 3rd, that is, tests GOA M3 characteristic.As can be seen that the embodiment of the present invention is provided
Array base palte, not only save the space needed for control area, each test in test structure can also be made full use of to weld
Disk.
It should be noted that in the test cell of array base palte shown in Fig. 8 of the present invention, being included with the second test cell 220
Shown exemplified by first test subelement, the second test subelement and the 3rd test subelement, in this case GOA TEG knot
Structure is most complete.
The array base palte provided based on the various embodiments described above of the present invention, the embodiment of the present invention also provides a kind of array base palte
Preparation method, the preparation method of the array base palte is used to make the array base palte that any of the above-described embodiment of the invention is provided.
As shown in figure 9, the flow chart of the preparation method for array base palte provided in an embodiment of the present invention.The present embodiment is provided
Method can apply to make array base palte technique in, method provided in an embodiment of the present invention may include steps of：
S110, gate metal layer is formed in the viewing area of substrate and on the non-display area on viewing area periphery；
Test cell in TFT gate patterns and non-display area in S120, removal part of grid pole metal level, formation viewing area
Gate patterns.
In embodiments of the present invention, need to consider the device figure in viewing area 30 and non-display area 40 when making array base palte
Can be made in shape, viewing area 30 can make the EPM TEG for testing TFT characteristics and be used in TFT, non-display area 40
The GOA TEG of GOA characteristics are tested, accordingly, it would be desirable to gate patterns 310 are formed in the viewing area 30 of substrate 2, and in substrate 2
Gate patterns 410 are formed in non-display area 40.As shown in Figure 10, be array base palte shown in Fig. 9 manufacturing process in one cut
Face schematic diagram.Illumination can be carried out using masking process to gate metal layer by removing the mode of part of grid pole metal level, then be adopted
Part of grid pole metal level is got rid of with etching technics, gate patterns are formed.
S130, forms insulating barrier on substrate and gate patterns, removes partial insulative layer with exposed portion gate patterns.
In embodiments of the present invention, the part of grid pole figure exposed is used in subsequent technique, the grid of connecting test unit
Pole and testing weld pad.
S140, forms amorphous silicon layer on insulating barrier and gate patterns, removes portion of amorphous silicon layer, forms TFT and test
The active layer pattern of unit.
As shown in figure 11, be array base palte shown in Fig. 9 manufacturing process in another schematic cross-section.Shown in Figure 11
Insulating barrier 200 and active layer pattern, it (is TFT's that the active layer pattern, which includes being located at active layer pattern 320 in viewing area 30,
Active layer pattern) and active layer pattern 420 active layer pattern of test cell (be) in non-display area 40.
S150, forms metal level, and remove partial metal layers formation TFT and test list on insulating barrier and active layer pattern
The source electrode figure of member and drain patterns.
As shown in figure 12, be array base palte shown in Fig. 9 manufacturing process in another schematic cross-section.Shown in Figure 12
In viewing area 30 in TFT source electrode figure 331 and drain patterns 332, and non-display area 40 test cell source electrode figure
431 and drain patterns 432.
In the embodiment of the present invention, the structure of the test cell in non-display area 40 is referred to appoint shown in above-mentioned Fig. 6 to Fig. 8
Test cell in one embodiment, the test cell include the first test cell and the second test cell, the first test cell and
The source electrode of second test cell is connected to same testing weld pad, and grid is connected to same testing weld pad, and drain electrode is connected to not
Same testing weld pad.
Alternatively, in embodiments of the present invention, the first test cell is used to test TFT electrical parameter performance；
First test cell is TFT, and the structure and electrical parameter performance with the TFT of viewing area are identical；In addition, the second test is single
Member is used to test the GOA of non-display area.
Alternatively, in embodiments of the present invention, the source electrode of each test cell, grid and drain electrode are connected to different tests
Pad, the testing weld pad of source electrode, grid and drain electrode for testing needle to be pricked to some test cell in test simultaneously, from
And making alive is tested.
The preparation method for the array base palte that inventive embodiments are provided, has the in the non-display area for the array base palte produced
One test cell, the second test cell and testing weld pad, and the source electrode of the first test cell and the second test cell is connected to
Same testing weld pad, grid is connected to same testing weld pad, and drain electrode is connected to different testing weld pads, wherein, first surveys
Examination unit (EPM TEG) is used to test TFT electrical parameter performance, and the second test cell (GOA TEG) is used for non-
The GOA of viewing area is tested.Array base palte provided in an embodiment of the present invention, by EPM TEG of the prior art structure weight
Newly it is designed as：By EPM TEG and GOA TEG common-sources and the testing weld pad of grid, drain electrode connects different testing weld pads, from
And the integrated GOA TEG in EPM TEG can be realized, the structure of the array base palte reduces the space needed for test suite, nothing
GOA TEG need to be placed in the monitor area of whole substrate, can be placed in non-display area, that is, saved and set in a substrate
The space of monitor area；In addition, the TFT characteristics of viewing area can be not only monitored in subsequent technique, can also be to non-
The GOA characteristics of viewing area are monitored to be intercepted with bad, is conducive to improving product yield.
Although disclosed herein embodiment as above, described content be only readily appreciate the present invention and use
Embodiment, is not limited to the present invention.Technical staff in any art of the present invention, is taken off not departing from the present invention
On the premise of the spirit and scope of dew, any modification and change, but the present invention can be carried out in the form and details of implementation
Scope of patent protection, still should be subject to the scope of the claims as defined in the appended claims.
Claims (10)
1. a kind of array base palte, it is characterised in that including：
The first test cell, are provided with viewing area and the non-display area positioned at the viewing area periphery, the non-display area
Two test cells and testing weld pad, wherein, the source electrode of first test cell and second test cell is connected to same
Individual testing weld pad, grid is connected to same testing weld pad, and drain electrode is connected to different testing weld pads；
First test cell is used to test the electrical parameter performance of TFT；
Second test cell is used to test the gate driving circuit of the non-display area.
2. array base palte according to claim 1, it is characterised in that first test cell is used for thin film field-effect
The electrical parameter performance of transistor is tested, including：
Add the scanning voltage of preset range by the grid to first test cell, voltage be fixed to drain electrode and source electrode,
The test drain electrode and the curent change of the source electrode.
3. array base palte according to claim 1, it is characterised in that first test cell is thin film field-effect crystal
Pipe, and first test cell is identical with the structure and electrical parameter performance of the TFT of the viewing area.
4. array base palte according to claim 1, it is characterised in that source electrode, grid and the leakage of each test cell
Pole is connected to different testing weld pads.
5. according to array base palte according to any one of claims 1 to 4, it is characterised in that second test cell includes
One or more test cells below：First test subelement, the second test subelement and the 3rd test subelement；
Wherein, the thin film field-effect crystal charged when the first test subelement is work by forward scan to high potential point
Pipe；
The TFT that the second test subelement is charged when being work by reverse scan to high potential point；
The TFT that the 3rd test subelement charges when being work to output.
6. array base palte according to claim 5, it is characterised in that the first testing weld pad connects first test respectively
The source electrode of unit and the first test subelement, the second test subelement and the 3rd test subelement, second
Testing weld pad connects first test cell and the first test subelement, the second test subelement and institute respectively
State the grid of the 3rd test subelement；
3rd testing weld pad includes the first sub- pad and the second sub- pad of separation, and the 4th testing weld pad includes the 3rd son of separation
Pad and the 4th sub- pad, the first sub- pad, the second sub- pad, the 3rd sub- pad and the 4th sub- pad
First test cell and the first test subelement, the second test subelement and described are connected correspondingly
The drain electrode of 3rd test subelement.
7. the array base palte according to claim 5 or 6, it is characterised in that the first test subelement, described second are surveyed
Swab unit is different with the channel width-over-length ratio of the described 3rd test subelement.
8. a kind of preparation method of array base palte, it is characterised in that including：
Gate metal layer is formed in the viewing area of substrate and on the non-display area on the viewing area periphery；
The part gate metal layer is removed, the gate patterns of TFT are formed in the viewing area and described non-
The gate patterns of test cell in viewing area；
Insulating barrier is formed on the substrate and the gate patterns, partial insulative layer is removed with exposed portion gate patterns；
Amorphous silicon layer is formed on the insulating barrier and the gate patterns, the part amorphous silicon layer is removed, is formed described thin
The active layer pattern of film field-effect transistor and the test cell；
Metal level is formed on the insulating barrier and the active layer pattern, and removes partial metal layers and forms the thin film field effect
Answer transistor and the source electrode figure of the test cell and drain patterns；
Wherein, the test cell includes the first test cell and the second test cell, first test cell and described the
The source electrode of two test cells is connected to same testing weld pad, and grid is connected to same testing weld pad, and drain electrode is connected to difference
Testing weld pad.
9. the preparation method of array base palte according to claim 8, it is characterised in that first test cell is used for pair
The electrical parameter performance of TFT is tested；First test cell and the thin film field of the viewing area are imitated
Answer the structure of transistor identical with electrical parameter performance；
Second test cell is used to test the gate driving circuit of the non-display area.
10. the preparation method of array base palte according to claim 8, it is characterised in that the source of each test cell
Pole, grid and drain electrode are connected to different testing weld pads.
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| CN109166507A (en) * | 2018-11-01 | 2019-01-08 | 京东方科技集团股份有限公司 | Testing element group, electrical performance test method, array substrate, display device |
| CN109903712A (en) * | 2019-04-30 | 2019-06-18 | 深圳市华星光电半导体显示技术有限公司 | Array substrate horizontal drive circuit and display panel |
| CN109961729A (en) * | 2019-04-30 | 2019-07-02 | 深圳市华星光电半导体显示技术有限公司 | Display panel and its test method |
| US11480606B2 (en) * | 2016-06-14 | 2022-10-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | In-line device electrical property estimating method and test structure of the same |
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| US11480606B2 (en) * | 2016-06-14 | 2022-10-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | In-line device electrical property estimating method and test structure of the same |
| CN109166507A (en) * | 2018-11-01 | 2019-01-08 | 京东方科技集团股份有限公司 | Testing element group, electrical performance test method, array substrate, display device |
| CN109903712A (en) * | 2019-04-30 | 2019-06-18 | 深圳市华星光电半导体显示技术有限公司 | Array substrate horizontal drive circuit and display panel |
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| CN107068696B (en) | 2020-05-22 |
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