CN109165183A - Peripheral assembly quickly interconnects atomic operation hardware implementation method, apparatus and system - Google Patents
Peripheral assembly quickly interconnects atomic operation hardware implementation method, apparatus and system Download PDFInfo
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- CN109165183A CN109165183A CN201811073490.2A CN201811073490A CN109165183A CN 109165183 A CN109165183 A CN 109165183A CN 201811073490 A CN201811073490 A CN 201811073490A CN 109165183 A CN109165183 A CN 109165183A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F9/526—Mutual exclusion algorithms
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
A kind of peripheral assembly quickly interconnects PCIe atomic operation hardware implementation method, apparatus and system.This method comprises: atom decoder module is identified by the PCIe data stream that PCIe interface is received and is sent in level expansion interface AXI bus interface according to PCIe bus protocol, to obtain the request of the first atomic operation；First atomic operation obtained request is encoded to by atom decoder module according to AXI bus protocol to be met the second atomic operation of AXI bus protocol and requests and send it to atomic processor module；And atomic processor module executes corresponding atomic operation according to the type that the second atomic operation for receiving is requested, wherein atom decoder module and atomic processor module are hardware module.This method realizes external PCIe atomic operation by hardware module on internal bus, and processing speed is fast, high-efficient, and realizes that convenience, portability are strong.
Description
Technical field
The present disclosure relates generally to data communications, and quickly interconnect PCIe atom more particularly, to a kind of peripheral assembly
Operate hardware implementation method, apparatus and system.
Background technique
Computer system is by including that the interconnection of the various components of processor, memory, peripheral equipment etc. is realized.For
Realize the communication between these different components, may occur in which multiple links with by one or more apparatus interconnections together.
Atomic operation (atomic operation) borrows the concept of physics minimum particle, and referring to will not be by thread scheduling
The operation that mechanism interrupts.Atomic operation is once just running to always end, centre will not be switched to another thread.
PCIe (Peripheral Component Interconnect express, peripheral assembly quickly interconnect) bus
It is a kind of high speed serialization computer expansion bus standard.FetchAdd can be used in PCIe device, and (fetch and add is extracted
And be added), Swap (exchange) and CAS (compare and swap, relatively and exchange) bus transaction carry out atomic operation.
Currently, needing not support original for internal bus when realizing external PCIe atomic operation on internal bus
The situation of sub-operation transmitting mainly realizes PCIe atomic operation by software, therefore access time delay is high, occupies CPU
(Central Processing Unit, central processing unit) process is easy to cause data jamming and then influences the operation of system
Efficiency.
Information above is presented as background technique to be only used for helping to understand the disclosure.Whether it is applicable in as any of the above content
In the prior art as the disclosure, it is not determined and is not stated yet.
Summary of the invention
In accordance with an embodiment of the present disclosure, a kind of peripheral assembly is provided and quickly interconnects PCIe atomic operation hardware implementation method,
It receives this method comprises: atom decoder module is identified by PCIe interface according to PCIe bus protocol and is sent to AXI
PCIe data stream in (Advanced eXtensible Interface, level expansion interface) bus interface, to obtain first
Atomic operation request；First atomic operation obtained request is encoded to symbol according to AXI bus protocol by atom decoder module
The second atomic operation for closing AXI bus protocol requests and sends it to atomic processor module；And atomic processor module
Corresponding atomic operation is executed according to the type of the second atomic operation request received, wherein atom decoder module and original
Sub-processor module is hardware module.
For example, the peripheral assembly provided in accordance with an embodiment of the present disclosure quickly interconnects PCIe atomic operation hardware implementation method
In, in the second atomic operation request for not receiving the transmission of atom decoder module, atomic processor module is in idle shape
State.
For example, the peripheral assembly provided in accordance with an embodiment of the present disclosure quickly interconnects PCIe atomic operation hardware implementation method
In, it includes: atomic processor that the type that atomic processor module is requested according to the second atomic operation, which executes corresponding atomic operation,
Module judges whether atomic operation runs succeeded, and is sent out according to AXI bus protocol to atom decoder module if running succeeded
It send and completes information to terminate corresponding atomic operation；If execution is unsuccessful, atomic processor module repeats atomic operation
Until running succeeded or until number of operations reaches the error handle upper limit or time-out, and reach on error handle in number of operations
It is reported an error according to AXI bus protocol to atom decoder module when limit or time-out and is sent completely information to terminate corresponding atom behaviour
Make.
For example, the peripheral assembly provided in accordance with an embodiment of the present disclosure quickly interconnects PCIe atomic operation hardware implementation method
In, the type of the second atomic operation request includes one of FetchAdd type, Swap type and CAS type or a variety of.
For example, the peripheral assembly provided in accordance with an embodiment of the present disclosure quickly interconnects PCIe atomic operation hardware implementation method
In, the type that sub-processor module is requested according to the second atomic operation received executes corresponding atomic operation and specifically includes:
If the type of the second atomic operation request is FetchAdd type, read at the destination address in the request of the second atomic operation
The value that the value of reading is added with the additive value in the request of the second atomic operation is written destination address, and returned by the value of storage
Return the value stored at the destination address before being not carried out corresponding atomic operation；If the type of the second atomic operation request is
Swap type then reads the value stored at the destination address in the request of the second atomic operation, will be in the request of the second atomic operation
Destination address is written in cross-over value, and returns to the value stored at the destination address before being not carried out corresponding atomic operation；Alternatively, such as
The type of the second atomic operation of fruit request is CAS type, then reads storage at the destination address in the request of the second atomic operation
Fiducial value in the value of reading and the request of the second atomic operation is compared by value, if the value read and the second atomic operation
Fiducial value in request is equal then by the cross-over value write-in destination address in the request of the second atomic operation, and returns and be not carried out accordingly
Atomic operation before destination address at store value.
According to another embodiment of the present disclosure, a kind of peripheral assembly is provided and quickly interconnects PCIe atomic operation hardware realization dress
It sets, which includes: atom decoder module, is configured as: being identified by PCIe interface according to PCIe bus protocol and receive
And it is sent to the PCIe data stream in level expansion interface AXI bus interface, it is requested with obtaining the first atomic operation, and according to
First atomic operation obtained request is encoded to the second atomic operation request for meeting AXI bus protocol by AXI bus protocol
And send it to atomic processor module；And atomic processor module, it is configured as according to the second atom received
The types of operation requests executes corresponding atomic operation, wherein atom decoder module and atomic processor module are hardware
Module.
For example, the peripheral assembly provided in accordance with an embodiment of the present disclosure quickly interconnects PCIe atomic operation hardware realization apparatus
In, in the second atomic operation request for not receiving the transmission of atom decoder module, atomic processor module is in idle shape
State.
For example, the peripheral assembly provided in accordance with an embodiment of the present disclosure quickly interconnects PCIe atomic operation hardware realization apparatus
In, atomic processor module is also configured to judge whether atomic operation runs succeeded, total according to AXI if running succeeded
Wire protocol is sent completely information to atom decoder module to terminate corresponding atomic operation；If execution is unsuccessful, repeat
Atomic operation is executed until running succeeded or until number of operations reaches the error handle upper limit or time-out, and is reached in number of operations
It is reported an error according to AXI bus protocol to atom decoder module when to the error handle upper limit or time-out and is sent completely information to terminate
Corresponding atomic operation.
For example, the peripheral assembly provided in accordance with an embodiment of the present disclosure quickly interconnects PCIe atomic operation hardware realization apparatus
In, the type of the second atomic operation request includes the one or more of FetchAdd type, Swap type and CAS type.
For example, the peripheral assembly provided in accordance with an embodiment of the present disclosure quickly interconnects PCIe atomic operation hardware realization apparatus
In, atomic processor module is specifically configured to: if the type of the second atomic operation request is FetchAdd type, being read
The value stored at destination address in the request of second atomic operation, by the additive value in the value of reading and the request of the second atomic operation
It is added obtained value write-in destination address, and returns to the value stored at the destination address before being not carried out corresponding atomic operation；
If the type of the second atomic operation request is Swap type, reads and stored at the destination address in the request of the second atomic operation
Value, by the second atomic operation request in cross-over value be written destination address, and return be not carried out before corresponding atomic operation
Destination address at store value；Alternatively, reading the second atom if the type of the second atomic operation request is CAS type
The value stored at destination address in operation requests compares the fiducial value in the value of reading and the request of the second atomic operation
Compared with by the cross-over value in the request of the second atomic operation if the value read is equal with the fiducial value in the request of the second atomic operation
Destination address is written, and returns to the value stored at the destination address before being not carried out corresponding atomic operation.
According to another embodiment of the present disclosure, a kind of peripheral assembly is provided and quickly interconnects PCIe atomic operation hardware realization system
System, which includes: PCIe interface, is configured as receiving the PCIe data stream including the request of the first atomic operation and will receive
To PCIe data stream be sent to level expansion interface AXI bus interface；AXI bus interface is configured as reception PCIe and connects
The PCIe data stream that mouth is sent；Atom decoder module, is configured as: identifying AXI bus interface according to PCIe bus protocol
In PCIe data stream to obtain the request of the first atomic operation, and according to AXI bus protocol the first atom obtained is grasped
Make request and be encoded to meet the second atomic operation of AXI bus protocol and request and send it to atomic processor module；And
Atomic processor module is configured as executing corresponding atom behaviour according to the type of the second atomic operation request received
Make, wherein atom decoder module and atomic processor module are hardware module.
The PCIe atomic operation hardware implementation method of disclosure offer, apparatus and system pass through two hardware module (atoms
Decoder module and atomic processor module) external PCIe atomic operation is realized on internal bus.With in the prior art
The case where being compared by the method for software realization, being not take up cpu process and blocked there is no data, therefore shown according to the disclosure
PCIe atomic operation hardware implementation method, the processing speed of apparatus and system of example property embodiment are fast, high-efficient, and the side of realization
Just, portable strong.
Detailed description of the invention
In order to illustrate more clearly of the technical solution of the embodiment of the present disclosure, the attached drawing to embodiment is simply situated between below
It continues, it will be apparent that, the accompanying drawings in the following description merely relates to some embodiments of the present disclosure, rather than the limitation to the disclosure.
Fig. 1 is the structural schematic diagram according to the PCIe atomic operation hardware realization apparatus of the exemplary embodiment of the disclosure.
Fig. 2 is according to atomic processor mould in the PCIe atomic operation hardware realization apparatus of the exemplary embodiment of the disclosure
The status diagram of block.
Fig. 3 is the flow chart according to the PCIe atomic operation hardware implementation method of the exemplary embodiment of the disclosure.
Fig. 4 is according to the atomic processor in the PCIe atomic operation hardware implementation method of the exemplary embodiment of the disclosure
The process flow diagram of module.
Fig. 5 is the structural schematic diagram according to the PCIe atomic operation system for implementing hardware of the exemplary embodiment of the disclosure.
Specific embodiment
To keep the purposes, technical schemes and advantages of the embodiment of the present disclosure clearer, below in conjunction with the embodiment of the present disclosure
Attached drawing, the technical solution of the embodiment of the present disclosure is clearly and completely described.Obviously, described embodiment is this public affairs
The a part of the embodiment opened, instead of all the embodiments.Based on described embodiment of the disclosure, ordinary skill
Personnel's every other embodiment obtained under the premise of being not necessarily to creative work, belongs to the range of disclosure protection.
Unless otherwise defined, the technical term or scientific term that the disclosure uses should be tool in fields of the present invention
The ordinary meaning for thering is the personage of general technical ability to be understood." first ", " second " used in the disclosure and similar word are simultaneously
Any sequence, quantity or importance are not indicated, and are used only to distinguish different component parts.Equally, "one", " one " or
The similar word such as person's "the" does not indicate that quantity limits yet, but indicates that there are at least one." comprising " or "comprising" etc. are similar
Word mean to occur element or object before the word cover the element for appearing in the word presented hereinafter or object and its
It is equivalent, and it is not excluded for other elements or object.The similar word such as " connection " or " connected " be not limited to physics or
The connection of person's machinery, but may include electrical connection, it is either direct or indirect."upper", "lower", " left side ",
" right side " etc. is only used for indicating relative positional relationship, after the absolute position for being described object changes, then the relative positional relationship
May correspondingly it change.
The disclosed invention people has found that current PCIe atomic operation is mainly realized by software, because of the visit under study for action
It asks that time delay is high, occupies cpu process, is easy to cause data jamming and then influences the operational efficiency of system.
According to an at least exemplary embodiment for the disclosure, PCIe atomic operation hardware realization apparatus is provided, the device packet
Include: atom decoder module is configured as: being identified by PCIe interface according to PCIe bus protocol and is received and be sent to advanced
PCIe data stream in expansion interface AXI bus interface, to obtain the request of the first atomic operation, and according to AXI bus protocol
First atomic operation obtained request is encoded to and meets the second atomic operation of AXI bus protocol and requests and send it to
Atomic processor module；And atomic processor module, it is configured as the class according to the second atomic operation request received
Type executes corresponding atomic operation, wherein the atom decoder module and atomic processor module are hardware module.
According to an at least exemplary embodiment for the disclosure, PCIe atomic operation hardware implementation method, this method packet are provided
Include: atom decoder module is identified by PCIe interface according to PCIe bus protocol and receives and be sent to level expansion interface AXI
PCIe data stream in bus interface, to obtain the request of the first atomic operation；Atom decoder module will according to AXI bus protocol
First atomic operation obtained request, which is encoded to, to be met the second atomic operation of AXI bus protocol and requests and send it to original
Sub-processor module；And atomic processor module executes corresponding original according to the type that the second atomic operation received is requested
Sub-operation, wherein atom decoder module and atomic processor module are hardware module.
According to an at least exemplary embodiment for the disclosure, PCIe atomic operation system for implementing hardware is provided, the system packet
Include: PCIe interface is configured as receiving the PCIe number that includes the PCIe data stream of the first atomic operation request and will receive
Level expansion interface AXI bus interface is sent to according to stream；AXI bus interface is configured as receiving what PCIe interface was sent
PCIe data stream；Atom decoder module, is configured as: identifying the PCIe in AXI bus interface according to PCIe bus protocol
First atomic operation obtained is requested to compile by data flow to obtain the request of the first atomic operation, and according to AXI bus protocol
Code requests to meet the second atomic operation of AXI bus protocol and sends it to atomic processor module；And atom processing
Device module is configured as executing corresponding atomic operation according to the type of the second atomic operation request received, wherein former
Sub-decoder module and atomic processor module are hardware module.
Below by several specific embodiments to the PCIe atomic operation hardware implementation method of the disclosure, apparatus and system
It is illustrated.In order to keep the following explanation of the embodiment of the present invention to understand and concise, known function and known elements can be omitted
It is described in detail.When the either component of the embodiment of the present invention occurs in more than one attached drawing, the component is in each attached drawing
It is denoted by the same reference numerals.
A kind of PCIe atomic operation hardware realization apparatus is provided according to an exemplary embodiment of the present disclosure.Fig. 1 is according to this
The structural schematic diagram of the PCIe atomic operation hardware realization apparatus of disclosed exemplary embodiment.
As shown in Figure 1, PCIe atomic operation hardware realization apparatus 11 according to the exemplary embodiment of the disclosure includes original
Sub-decoder module 111 and atomic processor module 112.Wherein, atom decoder module 111 and atomic processor module 112
It is hardware module.
In the present embodiment, atom decoder module 111 is configured as: being identified by PCIe interface according to PCIe bus protocol
The PCIe data stream for receiving and being sent in level expansion interface AXI bus interface, to obtain the request of the first atomic operation.This public affairs
In the embodiment opened, atomic operation associated with the first atomic operation request in PCIe data stream is properly termed as PCIe atom
Operation.In embodiment of the disclosure, the first atomic operation request in PCIe data stream meets the atom behaviour of PCIe bus protocol
It standardizes.
In the present embodiment, atom decoder module 111 is also configured to obtained first according to AXI bus protocol
Atomic operation request, which is encoded to, to be met the second atomic operation of AXI bus protocol and requests and send it to atomic processor module
112.Here, the request of the second atomic operation meets the atomic operation specification of AXI bus protocol.Pass through above-mentioned identification and coding behaviour
Make, realizes the conversion of the atomic operation specification of PCIe bus protocol and the atomic operation specification of AXI bus protocol, so that it is guaranteed that
Exterior PC Ie atomic operation can be realized in internal AXI bus.These identification and encoding operation traditional software mode into
It is no or increasingly complex during row atomic operation.
For example, atom decoder module 111 can also request the atomic operation of acquisition in an example of the present embodiment
It is cached, to facilitate atomic processor module 112 to be handled.
In the present embodiment, atomic processor module 112 is configured as being executed according to the type that atomic operation is requested corresponding
Atomic operation.
Fig. 2 is according to atomic processor mould in the PCIe atomic operation hardware implementation method of the exemplary embodiment of the disclosure
The status diagram of block 112.
With reference to Fig. 2, for example, atomic processor module 112 is not receiving atom solution in an example of the present embodiment
When the second atomic operation request that code device module 111 is sent, in idle (IDLE) state；Receiving atom decoder mould
When the second atomic operation request that block 111 is sent, corresponding atomic operation is executed according to the type of the second atomic operation request.By
In sky when atomic processor module 112 is in the second atomic operation request for not receiving the transmission of atom decoder module 111
Not busy state, therefore power consumption can be saved according to the device of the present embodiment.
With reference to Fig. 2, for example, atomic processor module 112 is specifically configured in another example of the present embodiment:
When receiving the second atomic operation request of the transmission of atom decoder module 111, the type of the second atomic operation request, example are judged
Such as, in the present embodiment, the type of the second atomic operation request includes FetchAdd (fetch and add) type, Swap type
With CAS (compare and swap) type；Then, corresponding atom is executed according to the type of the second atomic operation request to grasp
Make.
It specifically, include FetchAdd type, Swap type and CAS in the type of the second atomic operation request with reference to Fig. 2
One of type or it is a variety of in the case where, atomic processor module 112 is specifically configured to: if the second atomic operation request
Type be FetchAdd type, then read the second atomic operation request in destination address at store value, by the value of reading
Destination address is written in the value being added with the additive value in the request of the second atomic operation, and returns and be not carried out corresponding atom behaviour
The value stored at destination address before work；If the type of the second atomic operation request is Swap type, it is former to read second
Destination address is written in cross-over value in the request of second atomic operation by the value stored at the destination address in sub-operation request, and
Return to the value stored at the destination address before being not carried out corresponding atomic operation；Or the if class that the second atomic operation is requested
Type is CAS type, then the value stored at the destination address in the request of the second atomic operation is read, by the value of reading and the second atom
Fiducial value in operation requests is compared, by the if the fiducial value during value and the second atomic operation read is requested is equal
Destination address is written in cross-over value in the request of two atomic operations, and returns to the destination address being not carried out before corresponding atomic operation
Locate the value of storage.Operating process about atomic processor module 112 can refer to Fig. 4 and corresponding embodiment.
For example, atomic processor module 112 can be additionally configured to: judge atom in another example of the present embodiment
Whether operation runs succeeded, and is sent completely according to AXI bus protocol to atom decoder module 111 if running succeeded
(completion) information is to terminate corresponding atomic operation；If execution is unsuccessful, atomic processor module 112 is repeated
Atomic operation reaches wrong in number of operations until running succeeded or until number of operations reaches the error handle upper limit or time-out
It is reported an error according to AXI bus protocol to atom decoder module 111 when accidentally handling the upper limit or time-out and is sent completely information to terminate
Corresponding atomic operation.For example, atomic processor module 112, which judges whether atomic operation runs succeeded, will be written mesh including judgement
Whether the value of mark address is written success.
In the present embodiment, by atom decoder module 111 and atomic processor module 112, realized on internal bus
External PCIe atomic operation.In addition, the atom decoder module 111 and atomic processor module 112 in the present embodiment are equal
For hardware module, thus it is fast, high-efficient according to the processing speed of the realization device of disclosure exemplary embodiment, and the side of realization
Just, portable strong.
Next, providing a kind of PCIe atomic operation hardware implementation method according to an exemplary embodiment of the present disclosure.Fig. 3 is
The flow chart of PCIe atomic operation hardware implementation method according to the exemplary embodiment of the disclosure.Method provided in this embodiment
By two hardware modules: atom decoder module and atomic processor module execute.
As shown in figure 3, in step s 11, atom decoder module is identified by PCIe interface according to PCIe bus protocol
The PCIe data stream for receiving and being sent in level expansion interface AXI bus interface, to obtain the request of the first atomic operation.This public affairs
In the embodiment opened, atomic operation associated with the first atomic operation request in PCIe data stream is properly termed as PCIe atom
Operation.In embodiment of the disclosure, the first atomic operation request in PCIe data stream meets the atom behaviour of PCIe bus protocol
It standardizes.
With continued reference to Fig. 3, in step s 12, atom decoder module is former by obtained first according to AXI bus protocol
Sub-operation request, which is encoded to, to be met the second atomic operation of AXI bus protocol and requests and send it to atomic processor module.
Here, the request of the second atomic operation meets the atomic operation specification of AXI bus protocol.It is real by above-mentioned identification and encoding operation
The conversion for having showed the atomic operation specification of PCIe bus protocol and the atomic operation specification of AXI bus protocol, so that it is guaranteed that external
PCIe atomic operation can be realized in internal AXI bus.
For example, in an example of the present embodiment, step S12 further include: atom decoder module coding is obtained the
The request of two atomic operations is cached, to facilitate atomic processor module to be handled.
With continued reference to Fig. 3, in step s 13, atomic processor module is requested according to the second atomic operation received
Type executes corresponding atomic operation.
For example, step S13 is specifically included in an example of the present embodiment: not receiving atom decoder module hair
When the second atomic operation request sent, atomic processor module is in idle (IDLE) state；Receiving atom decoder mould
When the second atomic operation request that block is sent, corresponding atomic operation is executed according to the type of the second atomic operation request.Due to
Atomic processor module is in idle condition in the second atomic operation request for not receiving the transmission of atom decoder module, because
This can save power consumption according to the method for the present embodiment.
Fig. 4 is according to the atomic processor in the PCIe atomic operation hardware implementation method of the exemplary embodiment of the disclosure
The process flow diagram of module.
With reference to Fig. 4, in an example of the present embodiment, in the second atomic operation for receiving the transmission of atom decoder module
When request, corresponding atomic operation is executed according to the type of atomic operation request and is specifically included: receiving atom decoder mould
When the second atomic operation request that block is sent, the type of the second atomic operation request is judged, for example, second is former in the present embodiment
The type of sub-operation request includes one of FetchAdd type, Swap type and CAS type or a variety of；Then, according to
The type of two atomic operations request executes corresponding atomic operation.
With continued reference to Fig. 4, for example, receiving the transmission of atom decoder module in another example of the present embodiment
When second atomic operation is requested, corresponding atomic operation is executed according to the type of atomic operation request and is specifically included: if second
The type of atomic operation request is FetchAdd type, then reads the value of the destination address storage in the request of the second atomic operation,
Destination address is written into the value that the value of reading is added with the additive value in the request of the second atomic operation, and returns and is not carried out phase
The value of destination address storage before the atomic operation answered；If the type of the second atomic operation request is Swap type, read
The value for taking the destination address storage in the request of the second atomic operation, by the cross-over value write-in target in the request of the second atomic operation
Location, and return to the value of the destination address storage before being not carried out corresponding atomic operation；Or if the second atomic operation is requested
Type be CAS type, then read the value of the destination address storage in the request of the second atomic operation, the value of reading and second is former
Fiducial value in sub-operation request is compared, will if the value read is equal with the fiducial value in the request of the second atomic operation
Destination address is written in cross-over value in the request of second atomic operation, and with returning to the target being not carried out before corresponding atomic operation
The value of location storage.
For example, in another example of the present embodiment, in the second atomic operation for receiving the transmission of atom decoder module
When request, corresponding atomic operation is executed according to the type of atomic operation request further include: judge whether atomic operation executes into
Function is sent completely (completion) information to atom decoder module according to AXI bus protocol if running succeeded to tie
The corresponding atomic operation of beam；If execution is unsuccessful, atomic processor module repeat atomic operation until running succeeded or
Until number of operations reaches the error handle upper limit or time-out, and when number of operations reaches the error handle upper limit or time-out according to
AXI bus protocol reports an error to atom decoder module and is sent completely information to terminate corresponding atomic operation.For example, at atom
Reason device module judges whether atomic operation runs succeeded including judging whether the value that destination address is written is written success.Here,
The completion information or error information that atomic processor module is sent to atom coder module, which are used as, requests the second atomic operation
Response message.
Since method provided in this embodiment is mainly by two hardware modules: atom decoder module and atomic processor mould
Block executes, therefore according to the processing speed of the implementation method of disclosure exemplary embodiment fast, high-efficient, and the side of realization
Just, portable strong.
Next, providing a kind of PCIe atomic operation system for implementing hardware according to an exemplary embodiment of the present disclosure.Fig. 5 is
The structural schematic diagram of PCIe atomic operation system for implementing hardware according to the exemplary embodiment of the disclosure.
As shown in figure 5, PCIe atomic operation system for implementing hardware according to the exemplary embodiment of the disclosure includes PCIe
Interface 12, AXI bus interface 13 and the PCIe atomic operation hardware realization apparatus 11 as described in embodiment one.
In the present embodiment, PCIe interface 12 is configured as receiving the PCIe data stream including the request of the first atomic operation.Show
Example property, what PCIe interface 12 can receive the external equipment transmission for being coupled to PCIe bus includes the request of the first atomic operation
PCIe data stream.In embodiment of the disclosure, the atomic operation that PCIe interface 11 receives requests associated atomic operation can
With referred to as PCIe atomic operation.In embodiment of the disclosure, it is total that the first atomic operation request in PCIe data stream meets PCIe
Wire protocol.
In the present embodiment, AXI bus interface 12 is used as internal bus interface, is configured as receiving the transmission of PCIe interface 11
PCIe data stream.
In the present embodiment, PCIe atomic operation hardware realization apparatus 11 includes that atom decoder module 111 and atom are handled
Device module 112.
In the present embodiment, atom decoder module 111 is configured as: identifying AXI bus interface according to PCIe bus protocol
PCIe data stream in 12 is to obtain the request of the first atomic operation, and according to AXI bus protocol by the first atom obtained
Operation requests, which are encoded to, to be met the second atomic operation of AXI bus protocol and requests and send it to atomic processor module 112.
In the present embodiment, atomic processor module 112 is configured as the class according to the second atomic operation request received
Type executes corresponding atomic operation.
The PCIe as described in PCIe atomic operation hardware realization apparatus 11 and above-described embodiment in this present embodiment is former
The structure of sub-operation hardware realization apparatus is identical with principle, accordingly, with respect to atom decoder module 111 and atomic processor module
112 other examples, which is not described herein again.
By this system, external PCIe atomic operation is realized on internal bus.Also, system provided in this embodiment
It unites and is realized by hardware module, therefore is fast, high-efficient according to the processing speed of the realization system of disclosure exemplary embodiment, and
It realizes convenient, portable strong.
Described above is only the specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto,
Anyone skilled in the art can carry out various change or replacement in the technical scope that the disclosure discloses, this
A little change or replacement should all be covered within the protection scope of the disclosure.Therefore, the protection scope of the disclosure should be with claim
Protection scope subject to.
Claims (11)
1. a kind of peripheral assembly quickly interconnects PCIe atomic operation hardware implementation method, comprising:
Atom decoder module is identified by PCIe interface according to PCIe bus protocol and receives and be sent to level expansion interface AXI
PCIe data stream in bus interface, to obtain the request of the first atomic operation；
First atomic operation obtained request is encoded to by atom decoder module according to AXI bus protocol meets AXI bus
Second atomic operation of agreement requests and sends it to atomic processor module；And
Atomic processor module executes corresponding atomic operation according to the type of the second atomic operation request received,
Wherein, the atom decoder module and atomic processor module are hardware module.
2. PCIe atomic operation hardware implementation method as described in claim 1, wherein do not receiving atom decoder module
When the second atomic operation request sent, the atomic processor module is in idle condition.
3. PCIe atomic operation hardware implementation method as described in claim 1, wherein atomic processor module is according to the second original
The type of sub-operation request executes corresponding atomic operation
Atomic processor module judges whether atomic operation runs succeeded, according to AXI bus protocol to original if running succeeded
Sub-decoder module is sent completely information to terminate corresponding atomic operation；If execution is unsuccessful, atomic processor module weight
Atomic operation is executed until running succeeded again or until number of operations reaches the error handle upper limit or time-out, and in number of operations
It is reported an error according to AXI bus protocol to atom decoder module when reaching the error handle upper limit or time-out and is sent completely information to tie
The corresponding atomic operation of beam.
4. PCIe atomic operation hardware implementation method as described in claim 1, wherein the class of the second atomic operation request
Type includes extracting and being added FetchAdd type, exchange Swap type and relatively and one of exchange CAS type or a variety of.
5. PCIe atomic operation hardware implementation method as claimed in claim 4, wherein atomic processor module is according to receiving
The type of the second atomic operation request execute corresponding atomic operation and specifically include:
If the type of the second atomic operation request is FetchAdd type, the mesh in the request of the second atomic operation is read
The value stored at address is marked, the value write-in target that the value of reading is added with the additive value in the request of the second atomic operation
Location, and return to the value stored at the destination address before being not carried out corresponding atomic operation；
If the type of the second atomic operation request is Swap type, with reading the target in the request of the second atomic operation
Cross-over value in the request of second atomic operation is written destination address, and returns and be not carried out corresponding atom by the value stored at location
The value stored at destination address before operation；Or
If the type of the second atomic operation request is CAS type, with reading the target in the request of the second atomic operation
Fiducial value in the value of reading and the request of the second atomic operation is compared by the value stored at location, if the value read and the
Fiducial value in the request of two atomic operations is equal then by the cross-over value write-in destination address in the request of the second atomic operation, and returns
The value stored at destination address before being not carried out corresponding atomic operation.
6. a kind of peripheral assembly quickly interconnects PCIe atomic operation hardware realization apparatus, which includes:
Atom decoder module, is configured as:
PCIe interface is identified by according to PCIe bus protocol to receive and be sent in level expansion interface AXI bus interface
PCIe data stream, to obtain the request of the first atomic operation, and
First atomic operation obtained request is encoded to the second atom for meeting AXI bus protocol according to AXI bus protocol
Operation requests simultaneously send it to atomic processor module；And
Atomic processor module is configured as executing corresponding atom according to the type of the second atomic operation request received
Operation,
Wherein, the atom decoder module and atomic processor module are hardware module.
7. PCIe atomic operation hardware realization apparatus as claimed in claim 6 is sent not receiving atom decoder module
The second atomic operation request when, the atomic processor module is in idle condition.
8. PCIe atomic operation hardware realization apparatus as claimed in claim 6, wherein the atomic processor module is also matched
It is set to:
Judge whether atomic operation runs succeeded, is sent out according to AXI bus protocol to atom decoder module if running succeeded
It send and completes information to terminate corresponding atomic operation；If execution is unsuccessful, atomic operation is repeated until running succeeded
Or until number of operations reaches the error handle upper limit or time-out, and the root when number of operations reaches the error handle upper limit or time-out
It reports an error according to AXI bus protocol to atom decoder module and is sent completely information to terminate corresponding atomic operation.
9. PCIe atomic operation hardware realization apparatus as claimed in claim 6, wherein the class of the second atomic operation request
Type includes extracting and being added FetchAdd type, exchange Swap type and relatively and one of exchange CAS type or a variety of.
10. PCIe atomic operation hardware implementation method as claimed in claim 9, wherein the atomic processor module is specific
It is configured as:
If the type of the second atomic operation request is FetchAdd type, the mesh in the request of the second atomic operation is read
The value stored at address is marked, the value write-in target that the value of reading is added with the additive value in the request of the second atomic operation
Location, and return to the value stored at the destination address before being not carried out corresponding atomic operation；
If the type of the second atomic operation request is Swap type, with reading the target in the request of the second atomic operation
Cross-over value in the request of second atomic operation is written destination address, and returns and be not carried out corresponding atom by the value stored at location
The value stored at destination address before operation；Or
If the type of the second atomic operation request is CAS type, with reading the target in the request of the second atomic operation
Fiducial value in the value of reading and the request of the second atomic operation is compared by the value stored at location, if the value read and the
Fiducial value in the request of two atomic operations is equal then by the cross-over value write-in destination address in the request of the second atomic operation, and returns
The value stored at destination address before being not carried out corresponding atomic operation.
11. a kind of peripheral assembly quickly interconnects PCIe atomic operation system for implementing hardware, which includes:
PCIe interface is configured as receiving the PCIe number that includes the PCIe data stream of the first atomic operation request and will receive
Level expansion interface AXI bus interface is sent to according to stream；
AXI bus interface is configured as receiving the PCIe data stream that PCIe interface is sent；
Atom decoder module, is configured as:
The PCIe data stream in AXI bus interface is identified according to PCIe bus protocol to obtain the request of the first atomic operation, and
First atomic operation obtained request is encoded to the second atom for meeting AXI bus protocol according to AXI bus protocol
Operation requests simultaneously send it to atomic processor module；And
Atomic processor module is configured as executing corresponding atom according to the type of the second atomic operation request received
Operation,
Wherein, the atom decoder module and atomic processor module are hardware module.
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