CN103218337A - SoC (System on Chip) and method for realizing communication between master modules and between slave modules based on wishbone bus - Google Patents

SoC (System on Chip) and method for realizing communication between master modules and between slave modules based on wishbone bus Download PDF

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CN103218337A
CN103218337A CN2013100794181A CN201310079418A CN103218337A CN 103218337 A CN103218337 A CN 103218337A CN 2013100794181 A CN2013100794181 A CN 2013100794181A CN 201310079418 A CN201310079418 A CN 201310079418A CN 103218337 A CN103218337 A CN 103218337A
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module
communication data
primary module
communication
primary
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CN103218337B (en
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袁东明
杨学斌
刘元安
胡鹤飞
冉静
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BEIJING ANTROSE TECHNOLOGY Co Ltd
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BEIJING ANTROSE TECHNOLOGY Co Ltd
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Abstract

The invention relates to an SoC (System on Chip) and method for realizing the communication between master modules and between slave modules based on a wishbone bus. The SoC is provided with a standard wishbone bus, the master modules, the slave modules, a special exchange master module and a special exchange slave module, wherein the structures of the master and slave modules are improved, the master and slave modules are connected to the wishbone bus, and the special exchange master module and the special exchange slave module are additionally arranged. According to the SoC and the method provided by the invention, the corresponding modules are additionally arranged, and existing modules are improved, so that the communication between the master modules and between the slave modules can be realized in a manner that only a small amount of investment is spent, the cost is low, and the operation is simple and easy; and thus, the resources of the wishbone bus can be utilized sufficiently, the communication flexibility of a wishbone-bus system is improved, and the communication between master modules and between slave modules is realized, so that the SoC is applicable to more extensive systems, the resource advantage of the bus is utilized sufficiently, and meanwhile, the normativity of the SoC is maintained.

Description

Realize master and SOC (system on a chip) and method master and slave and based on the wishbone bus from communicating by letter
Technical field
The present invention relates to a kind of SOC (system on a chip), particularly a kind of wishbone of use as interconnection, realization master and SOC (system on a chip) and method master and slave and, belong to the technical field of on-chip testing system and digital communication from communicating by letter based on the wishbone bus.
Background technology
The Wishbone bus is a kind of interconnected SOC (system on a chip) bus of SOC (system on a chip) internal module that is used for.At present, SOC (system on a chip) uses four kinds of more bus standards to be: the Avalon of the AMBA of ARM, the Wishbone of OpenCores, Altera and the OCP of OCP-IP.Wherein, the advantage that the wishbone bus is different from other on-chip bus is as follows: simple in structure, dirigibility is very strong, and interface is simply compact, is applicable to the system of lightweight standard; Support User Defined signal (as TGD_I/O), open fully and free, be the inscience property right.Based on above advantage, the wishbone bus is often used in the design of some lightweight SOC (system on a chip).
The network-on-chip test macro is to adopt SoPC(System on Programmable Chip usually) technology realize, have a SOC (system on a chip) of the multiple network performance being carried out test function.Along with the development of semiconductor technology and industry, the product of such test macro or device little by little by original board level system gradually transition be SOC (system on a chip).Building of the SOC (system on a chip) of high-performance, lightweight be unable to do without high performance on-chip bus, so the wishbone on-chip bus is widely used also in test macro.
Referring to Fig. 1, introduce one of characteristics of wishbone on-chip bus: the data transmission procedure of master-slave mode.The interface of its primary module can the reading and writing bus, and can only be read and write by bus from the interface of module, and this is its simple in structure with compact reason.But therefore, also cause between primary module and the primary module or from module and from can't communicating between the module, and this communication process is necessary in the test macro often.
The reason that causes above-mentioned defective is that it mainly comprises following parts owing to should have special structural characteristics based on the test macro of wishbone bus:
The control primary module: its function is to be responsible on the one hand instructing with the upper-layer functionality module or test result mutual, is responsible on the other hand assigning instruction and reclaiming test result to the test primary module.
The test primary module: be responsible for receiving the test instruction of control primary module, calling function is implemented different test processs from module; And behind calculating and the statistical test result, send test result data to the control primary module.
Function is from module: be responsible for accepting calling of test primary module, and cooperatively interact, thereby implement various concrete, complicated test functions.
With the network performance testing system is example: in test process, need the control primary module to assign the test instruction that has parameter to the test primary module, reclaim test result and be uploaded to host computer.Function is from also needing to carry out the exchange of packet and the processing of procotol between the module, cooperation just can be finished subnetwork performance test function mutually.Yet, the master-slave mode data-transmission mode that wishbone bus self is fixing, make main control module and main test module, function from module and from all not carrying out data transmission between the functional module, this has just limited the realization of many network test functions to a great extent.
Prior art solutions is: directly adding data transmission interface between the primary module and/or between the module, walk around bus transfer data, so not only make the control circuit of this SOC (system on a chip) become disorderly and unsystematic, destroy the standardization of this SOC (system on a chip), can't utilize the bus advantage of this SOC (system on a chip) again.And, often still can not satisfy user's demand.Therefore, how to solve this difficult problem, just become the problem of scientific and technical personnel's concern in the industry.
Summary of the invention
In view of this, the purpose of this invention is to provide and a kind of thereby the wishbone bus system is optimized the SOC (system on a chip) and the method based on the wishbone bus of communicating by letter between main and master and slave and the module of can realizing of transforming, the present invention has improved the communication dirigibility of wishbone bus system, realized main and master and slave with from communicate by letter, also safeguarded the standardization of this SOC (system on a chip) simultaneously and made full use of the resources advantage of bus.
In order to achieve the above object, the invention provides a kind of based on the wishbone bus realize primary module and primary module, from module and from the SOC (system on a chip) of module communication, be provided with standard wishbone bus; It is characterized in that: this SOC (system on a chip) is also set up following two modules except improving to original each primary module of connecting described wishbone bus with from module:
Private exchange is from module, be responsible for when primary module is communicated by letter with primary module, the communication data that comprises control information, valid data and end signal that temporary source primary module sends, and confirm the purpose primary module respectively and this communication data is stored in the purpose primary module in storage unit in the corresponding memory space according to the purpose primary module address in the control information and communication data word length; And when the communication data that has a plurality of purpose primary modules when storage unit need send, by the arbitration of interrupt location priority supreme good primary module produced and to interrupt application; When communication data read by the purpose primary module finish after, just empty this purpose primary module corresponding memory space, write for the subsequent communications data; Be provided with: control, storage, interruption application and interface is totally four unit;
The private exchange primary module, be responsible for the time from module and from module communication, reception sources is from the interruption application of module, and a plurality of interruption applications are arbitrated, response priority the highest from module: read control information earlier with the communication data of buffer memory source from module, so that read whole communication datas, and determine to transmit target from module's address by purpose by the communication data word length in the control information; After finishing the reading of communication data, write the communication data of buffer memory from module to purpose; Be provided with: control, buffer memory, interruption reception and interface is totally four unit;
Described primary module and be to increase respectively separately to send and the condition judgment module that receives data from the improvement of module is so that this primary module and can send communication data according to the protocol rule of setting separately respectively from module; And the communication data that receives resolved according to the protocol rule of setting, to obtain valid data wherein.
In order to achieve the above object, the invention provides a kind of employing SOC (system on a chip) of the present invention and realize method for communicating between primary module and the primary module, it is characterized in that: described method comprises following operation steps:
(1) apply for the bus right to use after, the source primary module earlier sends the communication data of query type to private exchange from module, reads Query Result again, judges whether private exchange purpose primary module corresponding stored space from module is sky; If be not empty, then carry out subsequent step (2); Otherwise, redirect execution in step (3);
(2) the source primary module resets to sky by sending replacement type communication data with this section storage space, waits for that perhaps private exchange wherein after the data forwarding, becomes sky from module automatically; Just finish this method operating process;
(3) the source primary module sends communication data to private exchange from module; Private exchange is resolved the control information that wherein at first receives by its control module after module received communication data, and after according to control information all communication datas being stored in purpose primary module corresponding memory space, the source primary module discharges the bus right to use;
When (4) communication data that monitors buffer memory when the storage unit of private exchange from module will send, purpose primary module address is sent to the interruption application unit, by interrupting application unit the purpose primary module is carried out priority arbitration, and send the interruption application to priority supreme good primary module;
(5) receive the purpose primary module application bus right to use that this interruption is applied for; After applying for successfully, earlier send the communication data of reading type in advance from module, and private exchange is informed from module in himself address, so that following one-period is read the data in himself corresponding stored space to private exchange; Perhaps send the query type communication data earlier, inquire about whether the communication data that need read is arranged in its storage space, transmission is read the type communication data in advance and is informed that private exchange is after module again, directly read the data of private exchange in the module corresponding stored space, and finish the reception of whole communication datas according to the communication data word length in the control information that at first receives;
(6) after the purpose primary module receives all communication datas, it is resolved and extracted valid data; Simultaneously, private exchange is cancelled interruption application signal automatically from module, empties the corresponding stored space; Finish the communication process of this primary module and primary module.
In order to achieve the above object, the present invention provides a kind of employing SOC (system on a chip) of the present invention to realize that it is characterized in that: described method comprises following operation steps from module and from method for communicating between the module again:
(1) after the source is ready to communication data from module according to protocol rule, sends the interruption application to the private exchange primary module;
(2) the interruption receiving element of private exchange primary module receive active interruption application from module, and make a strategic decision according to priority, receive the communication data of the highest source of priority earlier from module, its control module is according to the communication data word length in the control information that receives earlier, the reception of whole communication datas is finished in the control interface unit, and is written to buffer unit;
(3) the private exchange primary module keeps the bus right to use, or when applying for the bus right to use once more after release, its control module sends to purpose from module from module's address and communication data word length with the communication data the buffer unit according to purpose in the control information;
(4) after purpose receives whole communication datas from module, communication data is resolved, extract valid data wherein, just finished this from module and communication process from module according to protocol rule.
The present invention's advantage compared with prior art is: in the SOC (system on a chip) of similar test macro since standard wishbone bus can only carry out primary module with between the module communicating by letter and inconvenient to some extent.The solution of prior art is to add self-defining interface to carry out data transmission between each equipment of needs communication, yet, do to make system become numerous and diverse like this, destroy the standardization of system.SOC (system on a chip) of the present invention is by adding corresponding module, again a small amount of logical circuit and respective resources are expanded, promptly set up to existing module, thereby making that only cost is a small amount of drops into, simple to operate, easy, just can realize primary module and primary module, from module with from communicating by letter between the module.Can make full use of the wishbone bus resource like this, improve the system communication dirigibility greatly, make it be applicable to test macro more, safeguard the standardization of bus system simultaneously.
Description of drawings
Fig. 1 is that the structure of existing standard SOC (system on a chip) based on the wishbone bus is formed synoptic diagram.
Fig. 2 be the present invention is based on the wishbone bus realize primary module and primary module, from module and structure composition synoptic diagram from the SOC (system on a chip) of module communication.
Fig. 3 is the private exchange primary module of SOC (system on a chip) of the present invention and forms synoptic diagram from the structure of module.
Fig. 4 the present invention is based on the wishbone bus to realize the operation steps process flow diagram of once communicating by letter between primary module and the primary module.
Fig. 5 the present invention is based on the wishbone bus to realize from module and operation steps process flow diagram from once communicating by letter between the module.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Referring to Fig. 2, introduce the present invention is based on the wishbone bus realize primary module and primary module, from module and structure composition from the SOC (system on a chip) of module communication.Each primary module of the architecture advances that it comprises the wishbone bus, be connected with this wishbone bus and from module, and following two modules of setting up:
(1) private exchange is from module: be responsible for when primary module is communicated by letter with primary module, the communication data that comprises control information, valid data and end signal (control information wherein comprises source module address and purpose module's address, communication data byte length, communication type and the standby field of reservation) that temporary source primary module sends in proper order, and confirm the purpose primary module respectively and this communication data is stored in the purpose primary module in storage unit in the corresponding memory space according to the purpose primary module address in the control information and communication data word length; And when the communication data that has a plurality of purpose primary modules when storage unit need send, by the arbitration of interrupt location priority supreme good primary module produced and to interrupt application; When communication data read by the purpose primary module finish after, just empty this purpose primary module corresponding memory space, write for the subsequent communications data; Be provided with: control, storage, interruption application and interface is totally four unit.The structure of these four unit is formed and its function following (referring to shown in Figure 3):
Control module: when being used for source primary module transmission communication data, the control information that at first sends is resolved,, and be stored to corresponding storage space so that receive whole communication datas according to purpose primary module address and communication data word length; After the purpose primary module has read all communication datas, be end signal just with the content assignment in the first address institute corresponding stored unit of this storage space, be the free time to show this storage space, can be used in and write communication data next time.
Storage unit: be used for the communication data that buffer memory source primary module sends, and mark the storage space of independent stationary separately respectively for each purpose primary module; And monitor whether be cached with the communication data that does not send in each storage space in real time; If have, then the purpose primary module address with this communication data correspondence sends to the interruption application unit.The mode of this cell stores communication data has two kinds:
First kind is sectional type storage: be that each primary module distributes one section fixed storage space, the communication data that will send to different primary modules according to the purpose primary module address in the control signal deposits in separately in the corresponding space;
Second kind is the queue-type storage: all communication datas that need transmit are cached in first-in first-out FIFO storehouse in proper order according to read-write, but the purpose primary module address in the control information of the every group communication data of need record, be used for producing and interrupt application, all data are sent out and finish in the FIFO storehouse.
Interrupt application unit: be responsible for receiving the purpose primary module address that needs the transport communication data that storage unit sends, and arbitrate, produce interruption according to the priority of these primary modules and apply for signal, the same time only produces the highest primary module of priority interrupts applying for signal.
Interface unit: be responsible for the wishbone bus end to communication data chronologically rule read and write, simultaneously the communication data that receives is sent to control module, is stored in the purpose primary module corresponding memory space; Perhaps receive the communication data of control module, for being read by primary module.
(2) private exchange primary module, be responsible for the time from module and from module communication, reception sources is from the interruption application of module, and a plurality of interruption applications are arbitrated, response priority the highest from module: read control information earlier with the communication data of buffer memory source from module, so that read whole communication datas, and determine to transmit target from module's address by purpose by the communication data word length in the control information; After finishing the reading of communication data, write the communication data of buffer memory from module to purpose.This private exchange primary module read-write communication data has two kinds of patterns:
First kind is after occupying the bus right to use, reads earlier and the buffer memory communication data, and forces to keep the bus right to use, finishes in this bus holding time communication data is read from buffer unit, is transmitted to purpose again from module;
Second kind is after occupying the bus right to use, reads earlier and the buffer memory communication data, does not force to keep the bus right to use afterwards; When this or next time obtain the bus right to use, again communication data is read from buffer unit, and be transmitted to purpose from module.This module is provided with: control, buffer memory, interruption reception and interface is totally four unit.The structure of these four unit is formed and its function following (referring to shown in Figure 3):
Interrupt receiving element: be responsible for receiving of the interruption application of each source, and the execution priority arbitration, the application of the highest source of priority from module responded, so that control module reads the communication data of this source from module from module;
Control module: be responsible for the control information of at first reading being resolved,, and it be stored in buffer unit so that finish reading of residual flux letter data according to the communication data word length by interrupting source that receiving element sends when module's address reads communication data; After reading whole communication datas, the forwarding target according to purpose is determined from module's address sends to purpose from module with the communication data in the buffer unit by interface unit again;
Buffer unit: be responsible under the control of control module the communication data of source from module that buffer memory is read by interface unit;
Interface unit: be responsible for the wishbone bus end to communication data chronologically rule send or receive, simultaneously the communication data that receives is sent to control module, perhaps receive the communication data of control module, be transmitted to purpose again from module.
(3) in the SOC (system on a chip) of the present invention improved primary module and improved be to increase respectively separately to send and the condition judgment module that receives data from module so that this primary module and can send communication data according to the protocol rule of setting separately respectively from module; And the communication data that receives resolved according to the protocol rule of setting, to obtain valid data wherein.
Referring to Fig. 4, introduce SOC (system on a chip) of the present invention and realize communication means between primary module and the primary module, concrete operations step:
Step 1, apply for the bus right to use after, the source primary module earlier sends the communication data of query type to private exchange from module, reads Query Result again, judges whether private exchange purpose primary module corresponding stored space from module is sky; If be not empty, then carry out subsequent step 2; Otherwise, redirect execution in step 3.
Step 2, the source primary module resets to sky by sending replacement type communication data with this section storage space, or waits for that private exchange wherein after the data forwarding, becomes sky from module automatically; Just finish this method operating process.
Step 3, the source primary module sends communication data to private exchange from module; Private exchange is resolved the control information that wherein at first receives by its control module after module received communication data, and after according to control information all communication datas being stored in purpose primary module corresponding memory space, the source primary module discharges the bus right to use.
Step 4, when the communication data that monitors buffer memory when the storage unit of private exchange from module will send, purpose primary module address is sent to the interruption application unit, by interrupting application unit the purpose primary module is carried out priority arbitration, and send the interruption application to priority supreme good primary module.
Step 5 receives the purpose primary module application bus right to use that this interruption is applied for; After applying for successfully, earlier send the communication data of reading type in advance from module, and private exchange is informed from module in himself address, so that following one-period is read the data in himself corresponding stored space to private exchange; Perhaps send the query type communication data earlier, inquire about whether the communication data that need read is arranged in its storage space, transmission is read the type communication data in advance and is informed that private exchange is after module again, directly read the data of private exchange in the module corresponding stored space, and finish the reception of whole communication datas according to the communication data word length in the control information that at first receives.
Step 6 after the purpose primary module receives all communication datas, is resolved and extracted valid data it; Simultaneously, private exchange is cancelled interruption application signal automatically from module, empties the corresponding stored space; Finish the communication process of this primary module and primary module.
Referring to Fig. 5, introduce SOC (system on a chip) of the present invention and realize from module and from the concrete operations step of communication means between the module:
After step 1, source are ready to communication data from module according to protocol rule, send the interruption application to the private exchange primary module.
Step 2, the interruption receiving element of private exchange primary module receive active interruption application from module, and make a strategic decision according to priority, receive the communication data of the highest source of priority earlier from module, its control module is according to the communication data word length in the control information that receives earlier, the reception of whole communication datas is finished in the control interface unit, and is written to buffer unit.
Step 3, the private exchange primary module keeps the bus right to use, or when applying for the bus right to use once more after release, its control module sends to purpose from module from module's address and communication data word length with the communication data the buffer unit according to purpose in the control information.
Step 4 after purpose receives whole communication datas from module, is resolved communication data according to protocol rule, extract valid data wherein, has just finished this from module and communication process from module.
The present invention has carried out repeatedly implementing test, below the situation of brief description embodiment:
When emulation of the present invention is implemented, adopt SoPC(System on Programable Chip) reason of hardware embodiment is: the primary module of original system or from module for realize main and master and slave with need add transmissions, accepting state machine from communication function and control the transmitting-receiving of communication data, to satisfy the rule of communication protocol, SoPC can give full play to its programmable features, like a cork former primary module can be led and circuit structure master and slave and from communicating by letter with revising to upgrade to from module.And module as main interpolation: the master/slave module of private exchange, also can utilize its programmable dirigibility, be added in this chip system effectively, neatly, reduce design complexities.The operation steps of embodiment is as described below:
Step 1: former SoPC SOC (system on a chip) is led the primary module of communicating by letter with the master upgrade: add observation circuit and state machine respectively at its transmission, receiving element, when finding that this communication is to carry out entering when primary module is communicated by letter with primary module set condition, transmission in this set condition, receiving circuit can send data and resolve and receive data according to communication protocol regular weaves of the present invention, and only the content of transceive data is carried out the agreement processing, and need not to change the read-write interface of bus, also to former master and not influence of transceive data from pattern.
Step 2: to former SoPC SOC (system on a chip) carry out from from upgrading of communicating by letter from module: add observation circuit and state machine respectively at its transmission, receiving element, when finding that this communication is to carry out entering set condition with from module communication the time from module, transmission in this set condition, receiving circuit can send data and resolve and receive data according to communication protocol regular weaves of the present invention, and only the content of transceive data is carried out the agreement processing, and need not to change the read-write interface of bus, also to former master and from the not influence of pattern transceive data.
Step 3: the private exchange that structure is finished is from module, be mounted to bus from module interface.This private exchange can adopt two kinds of modes of storing data of the present invention from module, all can finish the storage of data, the function of removing and monitoring.
Step 4: the private exchange primary module that structure is finished is mounted on the primary module interface of bus.Preferably adopt the continued operation of reading+writing, use same bus to take the mode of phase,, ensure the complete transmitting-receiving of data to improve the bus work efficiency.
Step 5: finish primary module with from the upgrading of module, and add private exchange primary module and private exchange after module to bus, also need interrupt system is made amendment, set priority etc., after finishing the architecture advances of each side from the interconnected angle of entire system, just can realize primary module and primary module, from module and communication process from module.
Adopt above implementation step, just SOC (system on a chip) of the present invention is implemented in the original system, and realize correlation function by the inventive method.The test findings of embodiment is successful, has realized goal of the invention.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.

Claims (8)

  1. One kind based on the wishbone bus realize primary module and primary module, from module and from the SOC (system on a chip) of module communication, be provided with standard wishbone bus; It is characterized in that: this SOC (system on a chip) is also set up following two modules except improving to original each primary module of connecting described wishbone bus with from module:
    Private exchange is from module, be responsible for when primary module is communicated by letter with primary module, the communication data that comprises control information, valid data and end signal that temporary source primary module sends, and confirm the purpose primary module respectively and this communication data is stored in the purpose primary module in storage unit in the corresponding memory space according to the purpose primary module address in the control information and communication data word length; And when the communication data that has a plurality of purpose primary modules when storage unit need send, by the arbitration of interrupt location priority supreme good primary module produced and to interrupt application; When communication data read by the purpose primary module finish after, just empty this purpose primary module corresponding memory space, write for the subsequent communications data; Be provided with: control, storage, interruption application and interface is totally four unit;
    The private exchange primary module, be responsible for the time from module and from module communication, reception sources is from the interruption application of module, and a plurality of interruption applications are arbitrated, response priority the highest from module: read control information earlier with the communication data of buffer memory source from module, so that read whole communication datas, and determine to transmit target from module's address by purpose by the communication data word length in the control information; After finishing the reading of communication data, write the communication data of buffer memory from module to purpose; Be provided with: control, buffer memory, interruption reception and interface is totally four unit;
    Described primary module and be to increase respectively separately to send and the condition judgment module that receives data from the improvement of module is so that this primary module and can send communication data according to the protocol rule of setting separately respectively from module; And the communication data that receives resolved according to the protocol rule of setting, to obtain valid data wherein.
  2. 2. SOC (system on a chip) according to claim 1, it is characterized in that: described communication data is made up of control information, valid data and end signal that order sends, wherein, control information comprises source module address and purpose module's address, communication data byte length, communication type and the standby field of reservation.
  3. 3. SOC (system on a chip) according to claim 1 is characterized in that: four Elementary Functions of described private exchange from module are as follows:
    Control module when being used for source primary module transmission communication data, is resolved the control information that at first sends, so that receive whole communication datas according to purpose primary module address and communication data word length, and is stored to corresponding storage space; After the purpose primary module has read all communication datas, be end signal just with the content assignment in the first address institute corresponding stored unit of this storage space, be the free time to show this storage space, can be used in and write communication data next time;
    Storage unit is used for the communication data that buffer memory source primary module sends, and marks the storage space of independent stationary separately respectively for each purpose primary module; And monitor whether be cached with the communication data that does not send in each storage space in real time; If have, then the purpose primary module address with this communication data correspondence sends to the interruption application unit;
    Interrupt application unit, be responsible for receiving the purpose primary module address that needs the transport communication data that storage unit sends, and arbitrate, produce interruption according to the priority of these primary modules and apply for signal, the same time only produces the highest primary module of priority interrupts applying for signal;
    Interface unit, be responsible for the wishbone bus end to communication data chronologically rule read and write, simultaneously the communication data that receives is sent to control module, is stored in the purpose primary module corresponding memory space; Perhaps receive the communication data of control module, for being read by primary module.
  4. 4. SOC (system on a chip) according to claim 1 is characterized in that: four Elementary Functions in the described private exchange primary module are as follows:
    Interrupt receiving element, be responsible for receiving of the interruption application of each source, and the execution priority arbitration, the application of the highest source of priority from module responded, so that control module reads the communication data of this source from module from module;
    Control module is responsible for by interrupting source that receiving element sends when module's address reads communication data the control information of at first reading being resolved, so that finish reading of residual flux letter data according to the communication data word length, and it is stored in buffer unit; After reading whole communication datas, the forwarding target according to purpose is determined from module's address sends to purpose from module with the communication data in the buffer unit by interface unit again;
    Buffer unit is responsible under the control of control module, the communication data of source from module that buffer memory is read by interface unit;
    Interface unit, be responsible for the wishbone bus end to communication data chronologically rule send or receive, simultaneously the communication data that receives is sent to control module, perhaps receive the communication data of control module, be transmitted to purpose again from module.
  5. 5. SOC (system on a chip) according to claim 1 is characterized in that: the mode of the cell stores communication data of described private exchange from module has two kinds:
    First kind is sectional type storage: be that each primary module distributes one section fixed storage space, the communication data that will send to different primary modules according to the purpose primary module address in the control signal deposits in separately in the corresponding space;
    Second kind is the queue-type storage: all communication datas that need transmit are cached in first-in first-out FIFO storehouse in proper order according to read-write, but the purpose primary module address in the control information of the every group communication data of need record, be used for producing and interrupt application, all data are sent out and finish in the FIFO storehouse.
  6. 6. SOC (system on a chip) according to claim 1 is characterized in that: described private exchange primary module read-write communication data has two kinds of patterns:
    First kind is after occupying the bus right to use, reads earlier and the buffer memory communication data, and forces to keep the bus right to use, finishes in this bus holding time communication data is read from buffer unit, is transmitted to purpose again from module;
    Second kind is after occupying the bus right to use, reads earlier and the buffer memory communication data, does not force to keep the bus right to use afterwards; When this or next time obtain the bus right to use, again communication data is read from buffer unit, and be transmitted to purpose from module.
  7. 7. one kind is adopted the described SOC (system on a chip) of claim 1 to realize method for communicating between primary module and the primary module, and it is characterized in that: described method comprises following operation steps:
    (1) apply for the bus right to use after, the source primary module earlier sends the communication data of query type to private exchange from module, reads Query Result again, judges whether private exchange purpose primary module corresponding stored space from module is sky; If be not empty, then carry out subsequent step (2); Otherwise, redirect execution in step (3);
    (2) the source primary module resets to sky by sending replacement type communication data with this section storage space, waits for that perhaps private exchange wherein after the data forwarding, becomes sky from module automatically; Just finish this method operating process;
    (3) the source primary module sends communication data to private exchange from module; Private exchange is resolved the control information that wherein at first receives by its control module after module received communication data, and after according to control information all communication datas being stored in purpose primary module corresponding memory space, the source primary module discharges the bus right to use;
    When (4) communication data that monitors buffer memory when the storage unit of private exchange from module will send, purpose primary module address is sent to the interruption application unit, by interrupting application unit the purpose primary module is carried out priority arbitration, and send the interruption application to priority supreme good primary module;
    (5) receive the purpose primary module application bus right to use that this interruption is applied for; After applying for successfully, earlier send the communication data of reading type in advance from module, and private exchange is informed from module in himself address, so that following one-period is read the data in himself corresponding stored space to private exchange; Perhaps send the query type communication data earlier, inquire about whether the communication data that need read is arranged in its storage space, transmission is read the type communication data in advance and is informed that private exchange is after module again, directly read the data of private exchange in the module corresponding stored space, and finish the reception of whole communication datas according to the communication data word length in the control information that at first receives;
    (6) after the purpose primary module receives all communication datas, it is resolved and extracted valid data; Simultaneously, private exchange is cancelled interruption application signal automatically from module, empties the corresponding stored space; Finish the communication process of this primary module and primary module.
  8. 8. one kind is adopted the described SOC (system on a chip) of claim 1 to realize that it is characterized in that: described method comprises following operation steps from module and from method for communicating between the module:
    (1) after the source is ready to communication data from module according to protocol rule, sends the interruption application to the private exchange primary module;
    (2) the interruption receiving element of private exchange primary module receive active interruption application from module, and make a strategic decision according to priority, receive the communication data of the highest source of priority earlier from module, its control module is according to the communication data word length in the control information that receives earlier, the reception of whole communication datas is finished in the control interface unit, and is written to buffer unit;
    (3) the private exchange primary module keeps the bus right to use, or when applying for the bus right to use once more after release, its control module sends to purpose from module from module's address and communication data word length with the communication data the buffer unit according to purpose in the control information;
    (4) after purpose receives whole communication datas from module, communication data is resolved, extract valid data wherein, just finished this from module and communication process from module according to protocol rule.
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104158627A (en) * 2014-08-25 2014-11-19 北京邮电大学 Multi-protocol automatic identification system and method for heterogeneous link
CN104836710A (en) * 2015-02-10 2015-08-12 数据通信科学技术研究所 Method and apparatus based on one-master with multi-slaves communication of distributed system
CN104980497A (en) * 2015-05-18 2015-10-14 东南大学 Wishbone bus based encapsulate security payload (ESP) encapsulation processing device
CN105069227A (en) * 2015-08-03 2015-11-18 浪潮集团有限公司 Method for building function verification platform based on WISHBONE bus design
CN106845004A (en) * 2017-02-15 2017-06-13 济南浪潮高新科技投资发展有限公司 It is a kind of that system and method is built based on script for functional verification platform
CN107562684A (en) * 2017-08-29 2018-01-09 广州市天正通信有限公司 Control method, device, equipment and storage medium between a kind of plate
CN107562549A (en) * 2017-08-21 2018-01-09 西安电子科技大学 Isomery many-core ASIP frameworks based on on-chip bus and shared drive
CN109164976A (en) * 2016-12-21 2019-01-08 北京忆恒创源科技有限公司 Optimize storage device performance using write buffer
CN110086595A (en) * 2019-04-16 2019-08-02 北京探境科技有限公司 Synchronous bus communications method
CN111432382A (en) * 2020-03-10 2020-07-17 刘天舒 Data transmission method, device and system and NFC storage device
CN111435340A (en) * 2020-01-14 2020-07-21 珠海市杰理科技股份有限公司 Internet bus unit, data transmission method, wishbone internet module and chip

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030145144A1 (en) * 2002-01-30 2003-07-31 International Business Machines Corporation N-way pseudo cross-bar using discrete processor local busses
US20070255874A1 (en) * 2006-04-28 2007-11-01 Jennings Kevin F System and method for target device access arbitration using queuing devices
CN101101581A (en) * 2007-07-27 2008-01-09 江苏中科龙梦科技有限公司 Data reading method of wishbone system structure
CN101930422A (en) * 2010-08-26 2010-12-29 浪潮电子信息产业股份有限公司 Multi-core CPU interconnection structure based on multilayer AHB bus
CN101937412A (en) * 2010-09-14 2011-01-05 硅谷数模半导体(北京)有限公司 System on chip and access method thereof
CN102591817A (en) * 2011-12-30 2012-07-18 中山大学 Multi-bus bridge controller and implementing method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030145144A1 (en) * 2002-01-30 2003-07-31 International Business Machines Corporation N-way pseudo cross-bar using discrete processor local busses
US20070255874A1 (en) * 2006-04-28 2007-11-01 Jennings Kevin F System and method for target device access arbitration using queuing devices
CN101101581A (en) * 2007-07-27 2008-01-09 江苏中科龙梦科技有限公司 Data reading method of wishbone system structure
CN101930422A (en) * 2010-08-26 2010-12-29 浪潮电子信息产业股份有限公司 Multi-core CPU interconnection structure based on multilayer AHB bus
CN101937412A (en) * 2010-09-14 2011-01-05 硅谷数模半导体(北京)有限公司 System on chip and access method thereof
CN102591817A (en) * 2011-12-30 2012-07-18 中山大学 Multi-bus bridge controller and implementing method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
王光: "SoC设计中的片上通信体系结构研究", 《现代电子技术》, no. 304, 1 September 2009 (2009-09-01) *

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104158627A (en) * 2014-08-25 2014-11-19 北京邮电大学 Multi-protocol automatic identification system and method for heterogeneous link
CN104158627B (en) * 2014-08-25 2017-08-15 北京邮电大学 A kind of automatic recognition system and method for heterogeneous links multi-protocols
CN104836710A (en) * 2015-02-10 2015-08-12 数据通信科学技术研究所 Method and apparatus based on one-master with multi-slaves communication of distributed system
CN104836710B (en) * 2015-02-10 2018-06-05 数据通信科学技术研究所 A kind of method and apparatus based on the communication of distributed system one master and multiple slaves
CN104980497B (en) * 2015-05-18 2018-02-27 东南大学 ESP encapsulation process devices based on Wishbone buses
CN104980497A (en) * 2015-05-18 2015-10-14 东南大学 Wishbone bus based encapsulate security payload (ESP) encapsulation processing device
CN105069227A (en) * 2015-08-03 2015-11-18 浪潮集团有限公司 Method for building function verification platform based on WISHBONE bus design
CN109164976A (en) * 2016-12-21 2019-01-08 北京忆恒创源科技有限公司 Optimize storage device performance using write buffer
CN106845004A (en) * 2017-02-15 2017-06-13 济南浪潮高新科技投资发展有限公司 It is a kind of that system and method is built based on script for functional verification platform
CN107562549A (en) * 2017-08-21 2018-01-09 西安电子科技大学 Isomery many-core ASIP frameworks based on on-chip bus and shared drive
CN107562549B (en) * 2017-08-21 2019-12-03 西安电子科技大学 Isomery many-core ASIP framework based on on-chip bus and shared drive
CN107562684B (en) * 2017-08-29 2018-09-21 广州市天正通信有限公司 Control method, device, equipment and storage medium between a kind of plate
CN107562684A (en) * 2017-08-29 2018-01-09 广州市天正通信有限公司 Control method, device, equipment and storage medium between a kind of plate
CN110086595A (en) * 2019-04-16 2019-08-02 北京探境科技有限公司 Synchronous bus communications method
CN111435340A (en) * 2020-01-14 2020-07-21 珠海市杰理科技股份有限公司 Internet bus unit, data transmission method, wishbone internet module and chip
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CN111432382B (en) * 2020-03-10 2020-12-22 刘天舒 Data transmission method, device and system and NFC storage device

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