CN109032987A - A kind of computer system and method accelerating domestic processor based on FPGA - Google Patents
A kind of computer system and method accelerating domestic processor based on FPGA Download PDFInfo
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- CN109032987A CN109032987A CN201810731391.2A CN201810731391A CN109032987A CN 109032987 A CN109032987 A CN 109032987A CN 201810731391 A CN201810731391 A CN 201810731391A CN 109032987 A CN109032987 A CN 109032987A
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
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- G06F15/00—Digital computers in general; Data processing equipment in general
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Abstract
The present invention provides a kind of computer system and method for accelerating domestic processor based on FPGA, including processor unit, and the processor unit includes domestic processor and several fpga chips, several fpga chips are connect by bus with domestic processor；Accelerating module is equipped with inside fpga chip, the accelerating module includes TCP Unload module and the compressed and decompressed module of GZIP；It take FPGA as the core of domestic processor accelerated method, TCP Unload module and the compressed and decompressed module of GZIP are realized inside FPGA, network unloading is provided for domestic processor and stores compressed and decompressed data prediction, the load pressure of domestic processor can effectively be mitigated, it solves the problems, such as that domestic processor data process performance is insufficient, is conducive to application of the domestic processor under the occasion more demanding to processor performance such as big data, artificial intelligence, network security.
Description
Technical field
The present invention relates to relating to domestic processor computer to calculate acceleration technique field, specific one kind makes domestic place based on FPGA
Manage computer system and method that device accelerates.
Background technique
Integrated circuit (IC) can be implemented to execute specific function.A type of IC is programmable IC, such as
Field programmable gate array (FPGA).FPGA is realized, FPGA is generally included can based on concurrent operation with hardware description language
Program the array of piece (programmable tiles).Each programmable chip usually includes programmable interconnection circuit and may be programmed
Both logic circuits.Programmable interconnection circuit is generally included through a large amount of of programmable interconnection point (PIP) different length interconnected
Interconnection line.Programmable logic circuit realizes the logic of user's design using programmable element.
The production domesticization of computer core software and hardware has attracted much attention, and country has put into effect relevant policy and encouraged and Development of Domestic meter
The development of calculation machine.Under the guidance of national policy, autonomous controllable home brewed computer all achieves biggish in software and hardware field
Progress realizes milestone formula development from scratch.
But be limited by the factors such as instruction set, manufacturing process, design level, software ecology, the performance of domestic processor with
All there is larger gaps for X 86 processor, the POWER processor of the manufacturers such as Intel, IBM.With big data, artificial intelligence, net
The development in the fields such as network safety, higher and higher to the performance requirement of computer, domestic processor is difficult to cope with these emerging applications
Requirement to process performance.
Summary of the invention
In order to overcome the deficiencies in the prior art described above, the present invention, which provides, a kind of accelerates domestic processor based on FPGA
Computer system and method, to solve the above technical problems.
The technical scheme is that
A kind of computer system accelerating domestic processor based on FPGA, including processor unit, the processor unit packet
Domestic processor and several fpga chips are included, several fpga chips are connect by bus with domestic processor；
It is equipped with accelerating module inside fpga chip, the accelerating module includes TCP Unload module and the compressed and decompressed module of GZIP,
TCP Unload module, for realizing the pretreatment for carrying out parallel network packet inside FPGA；
The compressed and decompressed module of GZIP, for realizing parallel data compression decompression inside FPGA.
Further, fpga chip is additionally provided with interconnecting interface, is interconnected, is used for by interconnecting interface between fpga chip
Realize that global serial ports is shared.
Further, domestic processor is also connected with storage equipment, and fpga chip is also connected with FLISH flash memory, and storage is set
It is standby also to be connect with fpga chip.
Further, TCP Unload module, for when domestic processor receives data from outside by network, TCP to be unloaded
It carries module to parse network packet, parses core data and be transferred to domestic processor；
TCP Unload module, be also used to when domestic processor by network send data when, TCP Unload module to core data into
Row is packaged, and is then sent by network.
Further, the compressed and decompressed module of GZIP is used for when data compression is stored in storage equipment by domestic processor,
The compressed and decompressed module of GZIP compresses data, deposit storage equipment；
The compressed and decompressed module of GZIP is also used to when domestic processor reads compressed data from storage equipment, GZIP compression solution
Compression module reads data from storage equipment and decompresses, and is transferred to domestic processor.
Technical solution of the present invention also provides a kind of method for accelerating domestic processor based on FPGA, includes the following steps:
Several fpga chips are set in domestic processor computer, several fpga chips pass through bus and domestic processor
Connection；
Setting TCP Unload module and the compressed and decompressed module of GZIP, provide network for domestic processor inside each fpga chip
Unload and store compressed and decompressed data prediction.
Further, setting TCP Unload module and the compressed and decompressed module of GZIP inside each fpga chip of step, are state
Processor is produced network unloading is provided and stores compressed and decompressed data prediction, comprising:
TCP Unload module is realized inside each fpga chip, realizes the data packet processing of the network protocols such as TCP.
Further, setting TCP Unload module and the compressed and decompressed module of GZIP inside each fpga chip of step, are state
Processor is produced network unloading is provided and stores compressed and decompressed data prediction, comprising:
The compressed and decompressed module of GZIP is realized inside each fpga chip, realizes the compressed and decompressed processing of data.
Further, setting TCP Unload module and the compressed and decompressed module of GZIP inside each fpga chip of step, are state
Produce processor provide network unloading and store in compressed and decompressed data prediction for domestic processor provide network unloading and
Compressed and decompressed data prediction is stored, detailed process includes:
When domestic processor receives data from outside by network, TCP Unload module inside fpga chip to network packet into
Row parsing, parses core data and is transferred to domestic processor；
When domestic processor sends data by network, the TCP Unload module of fpga chip is packaged core data, so
It is sent afterwards by network.
Further, setting TCP Unload module and the compressed and decompressed module of GZIP inside each fpga chip of step, are state
Produce processor provide network unloading and store in compressed and decompressed data prediction for domestic processor provide network unloading and
Store compressed and decompressed data prediction, detailed process further include:
The compressed and decompressed module logarithm of GZIP when data compression is stored in storage equipment by domestic processor, inside fpga chip
According to being compressed, deposit stores equipment；
When domestic processor reads compressed data from storage equipment, the compressed and decompressed module of GZIP inside fpga chip is from depositing
Storage equipment reads data and decompresses, and is transferred to domestic processor.
As can be seen from the above technical solutions, the invention has the following advantages that with FPGA for domestic processor accelerated method
Core, TCP Unload module and the compressed and decompressed module of GZIP are realized inside FPGA, network is provided for domestic processor and unloads
Compressed and decompressed data prediction is carried and stored, can effectively mitigate the load pressure of domestic processor, solve domestic place
The problem for managing device data processing performance deficiency, is conducive to domestic processor in big data, artificial intelligence, network security etc. to processing
Application under the higher occasion of device performance requirement.
In addition, design principle of the present invention is reliable, structure is simple, has very extensive application prospect.
It can be seen that compared with prior art, the present invention have substantive distinguishing features outstanding and it is significant ground it is progressive, implementation
Beneficial effect be also obvious.
Detailed description of the invention
Fig. 1 is accelerating module schematic diagram inside fpga chip；
Fig. 2 is that domestic processor computer calculates the parallel acceleration pattern diagram accelerated；
Fig. 3 is that embodiment two provides the computer system schematic diagram for accelerating domestic processor based on FPGA.
Specific embodiment
The present invention will be described in detail with reference to the accompanying drawing and by specific embodiment, and following embodiment is to the present invention
Explanation, and the invention is not limited to following implementation.
It is as follows in conjunction with Fig. 1-Fig. 3 illustrated embodiments:
Embodiment one
A kind of computer system accelerating domestic processor based on FPGA, including processor unit, the processor unit packet
Domestic processor 1 and a fpga chip 2 are included, fpga chip 2 is connect by bus with domestic processor 1；
Accelerating module is equipped with inside the fpga chip 2, the accelerating module includes TCP Unload module 2.2 and GZIP compression solution
Compression module 2.1,
TCP Unload module 2.2, for realizing the pretreatment for carrying out parallel network packet inside fpga chip；
The compressed and decompressed module 2.1 of GZIP, for realizing parallel data compression decompression inside fpga chip.
Domestic processor 1 is also connected with storage equipment, and fpga chip 2 is also connected with FLISH flash memory；Store equipment also with
Fpga chip 2 connects.
TCP Unload module 2.2 is used for when domestic processor 1 receives data from outside by network, TCP Unload module
2.2 pairs of network packets parse, and parse core data and are transferred to domestic processor 1；
TCP Unload module 2.2 is also used to when domestic processor 1 sends data by network, and TCP Unload module 2.2 is to core
Data are packaged, and are then sent by network.
The compressed and decompressed module 2.1 of GZIP is used for when data compression is stored in storage equipment by domestic processor 1, GZIP
Compressed and decompressed module 2.1 compresses data, deposit storage equipment；
The compressed and decompressed module 2.1 of GZIP is also used to when domestic processor 1 reads compressed data from storage equipment, GZIP pressure
Contracting decompression module 2.1 reads data from storage equipment and decompresses, and is transferred to domestic processor 1.
The method of acceleration based on above system, includes the following steps:
When domestic processor 1 receives data from outside by network, the TCP Unload module 2.2 inside fpga chip 2 is to network
Packet is parsed, and is parsed core data and is transferred to domestic processor 1；
When domestic processor 1 sends data by network, the TCP Unload module 2.2 of fpga chip 2 beats core data
Packet, is then sent by network.
The compressed and decompressed mould of GZIP when data compression is stored in storage equipment by domestic processor 1, inside fpga chip 1
Block 2.1 compresses data, deposit storage equipment；
The compressed and decompressed module of GZIP when domestic processor 1 reads compressed data from storage equipment, inside fpga chip 2
2.1 read data from storage equipment and decompress, and are transferred to domestic processor 1.
Embodiment two
A kind of computer system accelerating domestic processor based on FPGA, including processor unit, the processor unit packet
Domestic processor 1 and at least two fpga chips 2 are included, each fpga chip 2 is connect by bus with domestic processor 1；
Accelerating module is equipped with inside each fpga chip 2, the accelerating module includes TCP Unload module 2.2 and GZIP pressure
Contracting decompression module 2.1；
TCP Unload module 2.2, for realizing the pretreatment for carrying out parallel network packet inside fpga chip 2；
The compressed and decompressed module 2.1 of GZIP, for realizing parallel data compression decompression inside fpga chip.
Each fpga chip 2 is additionally provided with interconnecting interface, is interconnected between fpga chip 2 by interconnecting interface, for real
Existing overall situation serial ports is shared.
Domestic processor 1 is also connected with storage equipment, and fpga chip 2 is also connected with FLISH flash memory, storage equipment also with
Fpga chip 2 connects.
TCP Unload module 2.2 is used for when domestic processor 1 receives data from outside by network, TCP Unload module
2.2 pairs of network packets parse, and parse core data and are transferred to domestic processor 1；
TCP Unload module 2.2 is also used to when domestic processor 1 sends data by network, and TCP Unload module 2.2 is to core
Data are packaged, and are then sent by network.
The compressed and decompressed module 2.1 of GZIP is used for when data compression is stored in storage equipment by domestic processor, GZIP
Compressed and decompressed module 2.1 compresses data, deposit storage equipment；
The compressed and decompressed module 2.1 of GZIP is also used to when domestic processor 1 reads compressed data from storage equipment, GZIP pressure
Contracting decompression module 2.1 reads data from storage equipment and decompresses, and is transferred to domestic processor 1.
Embodiment three
A method of accelerating domestic processor based on FPGA, includes the following steps:
Several fpga chips are set in domestic processor computer, several fpga chips pass through bus and domestic processor
Connection；
TCP Unload module is realized inside each fpga chip, realizes the data packet processing of the network protocols such as TCP.
The compressed and decompressed module of GZIP is realized inside each fpga chip, realizes the compressed and decompressed processing of data.
When domestic processor receives data from outside by network, the TCP Unload module inside fpga chip is to network
Packet is parsed, and is parsed core data and is transferred to domestic processor；
When domestic processor sends data by network, the TCP Unload module of fpga chip is packaged core data, so
It is sent afterwards by network.
The compressed and decompressed module of GZIP when data compression is stored in storage equipment by domestic processor, inside fpga chip
Data are compressed, deposit storage equipment；
When domestic processor reads compressed data from storage equipment, the compressed and decompressed module of GZIP inside fpga chip is from depositing
Storage equipment reads data and decompresses, and is transferred to domestic processor.
Description and claims of this specification and term " first ", " second ", " third " " in above-mentioned attached drawing
The (if present)s such as four " are to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should manage
The data that solution uses in this way are interchangeable under appropriate circumstances, so as to the embodiment of the present invention described herein can in addition to
Here the sequence other than those of diagram or description is implemented.In addition, term " includes " and " having " and their any deformation,
It is intended to cover and non-exclusive includes.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. a kind of computer system for accelerating domestic processor based on FPGA, which is characterized in that described including processor unit
Processor unit includes domestic processor and several fpga chips, several fpga chips are connected by bus and domestic processor
It connects；
Accelerating module is equipped with inside fpga chip, the accelerating module includes TCP Unload module and the compressed and decompressed module of GZIP；
TCP Unload module, for realizing the pretreatment for carrying out parallel network packet inside FPGA；
The compressed and decompressed module of GZIP, for realizing parallel data compression decompression inside FPGA.
2. a kind of computer system for accelerating domestic processor based on FPGA according to claim 1, which is characterized in that
Fpga chip is additionally provided with interconnecting interface, is interconnected between fpga chip by interconnecting interface, for realizing global serial ports
It is shared.
3. a kind of computer system for accelerating domestic processor based on FPGA according to claim 2, which is characterized in that
Domestic processor is also connected with storage equipment, and fpga chip is also connected with FLISH flash memory, storage equipment also with fpga chip
Connection.
4. a kind of computer system for accelerating domestic processor based on FPGA according to claim 3, which is characterized in that
TCP Unload module, for when domestic processor receives data from outside by network, TCP Unload module to be to network packet
It is parsed, parses core data and be transferred to domestic processor；
TCP Unload module, be also used to when domestic processor by network send data when, TCP Unload module to core data into
Row is packaged, and is then sent by network.
5. a kind of computer system for accelerating domestic processor based on FPGA according to claim 3, which is characterized in that
The compressed and decompressed module of GZIP is used for when data compression is stored in storage equipment by domestic processor, GZIP Compress softwares
Contracting module compresses data, deposit storage equipment；
The compressed and decompressed module of GZIP is also used to when domestic processor reads compressed data from storage equipment, GZIP compression solution
Compression module reads data from storage equipment and decompresses, and is transferred to domestic processor.
6. a kind of method for accelerating domestic processor based on FPGA, which comprises the steps of:
Several fpga chips are set in domestic processor computer, several fpga chips pass through bus and domestic processor
Connection；
Accelerating module is equipped with inside each fpga chip, the accelerating module includes TCP Unload module and GZIP compression solution
Compression module provides network unloading for domestic processor and stores compressed and decompressed data prediction.
7. a kind of method for accelerating domestic processor based on FPGA according to claim 6, which is characterized in that step is every
Setting TCP Unload module and the compressed and decompressed module of GZIP inside a fpga chip, for domestic processor provide network unloading with
Store compressed and decompressed data prediction, comprising:
TCP Unload module is realized inside each fpga chip, realizes the data packet processing of the network protocols such as TCP.
8. a kind of method for accelerating domestic processor based on FPGA according to claim 6, which is characterized in that step is every
Setting TCP Unload module and the compressed and decompressed module of GZIP inside a fpga chip, for domestic processor provide network unloading with
Store compressed and decompressed data prediction, comprising:
The compressed and decompressed module of GZIP is realized inside each fpga chip, realizes the compressed and decompressed processing of data.
9. a kind of method for accelerating domestic processor based on FPGA according to claim 7, which is characterized in that step is every
Setting TCP Unload module and the compressed and decompressed module of GZIP inside a fpga chip, for domestic processor provide network unloading with
It stores and provides network unloading in compressed and decompressed data prediction for domestic processor and to store compressed and decompressed data pre-
Processing, detailed process include:
When domestic processor receives data from outside by network, TCP Unload module inside fpga chip to network packet into
Row parsing, parses core data and is transferred to domestic processor；
When domestic processor sends data by network, the TCP Unload module of fpga chip is packaged core data, so
It is sent afterwards by network.
10. a kind of method for accelerating domestic processor based on FPGA according to claim 8, which is characterized in that step
Setting TCP Unload module and the compressed and decompressed module of GZIP inside each fpga chip provide network unloading for domestic processor
Network unloading is provided for domestic processor in compressed and decompressed data prediction with storage and stores compressed and decompressed data
Pretreatment, detailed process further include:
The compressed and decompressed module logarithm of GZIP when data compression is stored in storage equipment by domestic processor, inside fpga chip
According to being compressed, deposit stores equipment；
When domestic processor reads compressed data from storage equipment, the compressed and decompressed module of GZIP inside fpga chip is from depositing
Storage equipment reads data and decompresses, and is transferred to domestic processor.
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Cited By (5)
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| CN109857024A (en) * | 2019-02-01 | 2019-06-07 | 京微齐力(北京)科技有限公司 | The unit performance test method and System on Chip/SoC of artificial intelligence module |
| CN109886416A (en) * | 2019-02-01 | 2019-06-14 | 京微齐力(北京)科技有限公司 | The System on Chip/SoC and machine learning method of integrated AI's module |
| CN109933369A (en) * | 2019-02-01 | 2019-06-25 | 京微齐力(北京)科技有限公司 | The System on Chip/SoC of integrated single-instruction multiple-data stream (SIMD) framework artificial intelligence module |
| CN113671880A (en) * | 2021-08-24 | 2021-11-19 | 中科亿海微电子科技（苏州）有限公司 | Financial data acceleration system and method |
| CN114238187A (en) * | 2022-02-24 | 2022-03-25 | 苏州浪潮智能科技有限公司 | FPGA-based full-stack network card task processing system |
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