CN109065545A - The flattening method of three-dimensional storage and its stack layer - Google Patents
The flattening method of three-dimensional storage and its stack layer Download PDFInfo
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- CN109065545A CN109065545A CN201810923512.3A CN201810923512A CN109065545A CN 109065545 A CN109065545 A CN 109065545A CN 201810923512 A CN201810923512 A CN 201810923512A CN 109065545 A CN109065545 A CN 109065545A
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 238000003860 storage Methods 0.000 title claims abstract description 41
- 230000002093 peripheral effect Effects 0.000 claims abstract description 94
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims description 16
- 238000001459 lithography Methods 0.000 claims description 11
- 238000005253 cladding Methods 0.000 claims description 3
- 230000000717 retained effect Effects 0.000 claims description 3
- 230000002459 sustained effect Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 190
- 239000000463 material Substances 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 239000000377 silicon dioxide Substances 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
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- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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Abstract
The present invention provides a kind of three-dimensional storage and its flattening methods of stack layer.Method includes the following steps: providing substrate, the semiconductor structure has core space, stepped region and peripheral region；The first insulating layer and the first stop-layer with preset thickness are sequentially formed in peripheral region；Stack layer is formed in the core space, stepped region and peripheral region；Hierarchic structure is formed on the stack layer of the stepped region, and at least removes a part of the peripheral region stack layer；Second insulating layer is formed on the core space, stepped region and peripheral region；Remove the second insulating layer of the core space and peripheral region；And the second insulating layer of stepped region is planarized.
Description
Technical field
The invention mainly relates to the planarizations of method for semiconductor manufacturing more particularly to a kind of three-dimensional storage and its stack layer
Method.
Background technique
In order to overcome the limitation of two-dimensional storage device, industry has been developed that the memory device with three-dimensional (3D) structure,
Integration density is improved by the way that memory cell is three-dimensionally disposed in substrate.
In the three-dimensional storage part of such as 3D nand flash memory, storage array may include the core with channel structure
(core) area and stepped region (stair step, SS).Settable peripheral region except storage array.In the system of three-dimensional storage part
During work, the planarization of stack layer (stack) is always a difficult point.2 lithography steps are generally needed just to be able to achieve at present flat
Smoothization.
Summary of the invention
The technical problem to be solved in the present invention is to provide three-dimensional storage and its flattening methods of stack layer, it is possible to reduce
One lithography step.
In order to solve the above technical problems, the present invention provides a kind of flattening method of the stack layer of three-dimensional storage, packet
It includes following steps: substrate is provided, the substrate has core space, stepped region and peripheral region；Sequentially forming in peripheral region has in advance
If the first insulating layer and the first stop-layer of thickness；Stack layer is formed in the core space, stepped region and peripheral region；In the rank
Hierarchic structure is formed on the stack layer in terraced area, and at least removes a part of the peripheral region stack layer；In the core space, rank
Second insulating layer is formed on terraced area and peripheral region；Remove the second insulating layer of the core space and peripheral region；And to stepped region
Second insulating layer planarized.
In one embodiment of this invention, in the step of forming the stack layer, the upper table of the stack layer of the core space
Face and the upper surface of the first stop-layer of the peripheral region are generally concordant.
In one embodiment of this invention, in the step of core space, stepped region and peripheral region form stack layer, institute
The stack layer for stating core space has the second stop-layer for being located at sustained height with the first stop-layer of the peripheral region.
In one embodiment of this invention, the step at least removing a part of the peripheral region stack layer is to form institute
It is executed during stating hierarchic structure.
In one embodiment of this invention, the step of planarizing to the second insulating layer of stepped region is in the peripheral region
The first stop-layer at stop.
In one embodiment of this invention, the step of planarizing to the second insulating layer of stepped region is in the peripheral region
The first stop-layer and the core space the second stop-layer at stop.
In one embodiment of this invention, the first insulation when removing the stack layer of the peripheral region, in the peripheral region
The side wall residual fraction stack layer of layer.
In one embodiment of this invention, the first insulating layer and first with preset thickness is sequentially formed in peripheral region to stop
Only the step of layer includes: at the beginning of sequentially forming the first initial insulating layer and first with preset thickness on the semiconductor structure
Beginning stop-layer；The the first initial stop-layer and the first initial insulating layer for removing the core space and stepped region, to be retained
The first stop-layer and the first insulating layer in the peripheral region.
In one embodiment of this invention, the step of removing the second insulating layer of the core space and peripheral region includes carrying out
Lithography and etching.
In one embodiment of this invention, the step of removing the stack layer of the peripheral region includes lithography and etching.
The present invention also proposes that a kind of three-dimensional storage, including core space, stepped region and peripheral region, the stepped region have rank
Terraced structure, the peripheral region has the first insulating layer of cladding peripheral circuit, wherein first insulating layer is towards the ladder
The side wall of structure has stacked structure, and the stacked structure is identical as the height of the hierarchic structure.
In one embodiment of this invention, three-dimensional storage further include positioned at the hierarchic structure and the stacked structure it
Between insulating regions.
In one embodiment of this invention, the stacked structure has the inclined side towards the hierarchic structure.
In one embodiment of this invention, the peripheral region also has the first stop-layer for covering first insulating layer.
Compared with prior art, a photoetching is only needed in the flattening method of the stack layer of three-dimensional storage of the invention
Stack layer can be made to planarize.And stop-layer need not be covered on the first insulating layer of the invention, therefore is being planarized
When, will grind comparatively fast.
Detailed description of the invention
Fig. 1 is the flattening method flow chart of the stack layer of the three-dimensional storage of one embodiment of the invention.
Fig. 2A -2G is in the example process of the flattening method of the stack layer of the three-dimensional storage of one embodiment of the invention
Diagrammatic cross-section.
Fig. 3 A-3B is schematic diagram of the one embodiment of the invention in peripheral region formation the first insulating layer and the first stop-layer.
Fig. 4 is the schematic diagram of remaining stack layer in the three-dimensional storage of one embodiment of the invention.
Fig. 5 A-5I is the flattening method flow chart as a kind of stack layer of the three-dimensional storage compared.
Specific embodiment
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, therefore the present invention is by the limit of following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason
Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing
Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under
Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party
To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers
" between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.
In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first
Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features
Embodiment, such first and second feature may not be direct contact.
The method of the embodiment of the present invention description production three-dimensional storage is right especially in three-dimensional storage manufacturing process
The method that its stack layer is planarized.Conventional flattening method generally needs 2 lithography steps, the following implementation of the present invention
The method of example description can reduce by 1 lithography step.
Fig. 1 is the flattening method flow chart of the stack layer of the three-dimensional storage of one embodiment of the invention.Fig. 2A -2G is this
Invent the diagrammatic cross-section in the example process of the flattening method of the stack layer of the three-dimensional storage of an embodiment.Join below
The method for examining the formation channel structure of description the present embodiment shown in Fig. 1-2 G.
In step 102, semiconductor structure is provided.
This semiconductor structure is at least part that will be used for structure of the follow-up process to ultimately form three-dimensional storage.
Semiconductor structure can have the area core (core), stepped region (Stair Step) and the area periphery (periphery).Core space is to use
In the region for forming storage unit；Stepped region is used to form the region of wordline connection circuit.Peripheral region is to be used to form periphery electricity
The region on road.In terms of vertical direction, this semiconductor structure can have substrate and cover the layer or structure of substrate.
In the sectional view of semiconductor structure exemplified by Fig. 2A, semiconductor structure 200a may include substrate 201.Substrate
201 be typically siliceous substrates, such as Si, SOI (silicon-on-insulator), SiGe, Si:C etc., although this and it is non-limiting.Substrate
201 can be divided into area core (core) 210, stepped region (Stair Step) 220 and area periphery (periphery) 230.Substrate 201
On can cover some layers or structure as needed.Such as peripheral circuit 231 and covering are formd on the substrate of peripheral region
The protective layer 232 of peripheral circuit.
Although there is described herein the exemplary composition of initial semiconductor structure, it is to be understood that, one or more features
It can be omitted, substitute or increase to from this semiconductor structure in this semiconductor structure.
In step 104, the first insulating layer and the first stop-layer with preset thickness are sequentially formed in peripheral region.
In this step, the first insulating layer can be formed to protect the circuit in peripheral region.First insulating layer can further shape
At the first stop-layer, so that etching and/or planarization be allowed to stop at desired height in subsequent technique.
In the sectional view of the semiconductor structure exemplified by Fig. 2 B, formd on the peripheral region 230 of semiconductor structure 200b
First insulating layer 202 and the first stop-layer 203.The mode for forming the first insulating layer 202 may include deposition.It can be from known each
Suitable technique is chosen in kind depositing operation, such as LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD.First insulating layer 202
Material can be silicon nitride, silica, silicon carbide, silicon oxynitride, aluminium oxide etc..The mode for forming the first stop-layer 203 can
Including deposition.Can be from known various depositing operations, such as chosen in LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD
Suitable technique.The material of first stop-layer can be selected according to the subsequent material to be etched, this will be described below.
Here, the first insulating layer 202 and the first stop-layer 203 can have preset thickness Th, this thickness can refer to will
It is arranged in the thickness for the stack layer that core space 210 is formed.Typically, it is expected that the upper surface and periphery of the stack layer of core space
The upper surface of first stop-layer 203 in area is concordant or generally concordant.Therefore default thickness can be set with reference to this target
Spend Th.For generally concordant, in preset range that the difference in height of two upper surfaces can be enabled.
In step 106, stack layer is formed in core space, stepped region and peripheral region.
In this step, stack layer is covered on the semiconductor structure that step 104 is formed.Stack layer may include being alternately stacked
Multiple first material layers and multiple second material layers.
In the sectional view of the semiconductor structure exemplified by Fig. 2 C, the core space 210 of semiconductor structure 200c, stepped region
220 and peripheral region 230 on form stack layer 204.Stack layer 204 mainly includes first material layer 204a and second material layer
The alternately stacked lamination of 204b.For example, first material layer 204a and second material layer 204b be silicon nitride and silica combination,
Silica and (undoped) polysilicon or combination, silicon oxide or silicon nitride and the combination of amorphous carbon of amorphous silicon etc..With nitridation
It, can be using chemical vapor deposition (CVD), atomic layer deposition (ALD) or other are suitable heavy for the combination of silicon and silica
Product method, successively replaces cvd silicon oxide (for example, second material layer 204b) and silicon nitride on substrate semiconductor structure 200b
(for example, first material layer 204a) forms the stack layer 204.
In one embodiment, stack layer 204 can also have the second stop-layer 204c.Second stop-layer 204c can be rear
Etching and/or planarization is allowed to stop at desired height in continuous technique.The material of second stop-layer 204c can be wanted according to subsequent
The material of etching selects, this will be described below.
In step 108, hierarchic structure, and the one of the stack layer of at least removal peripheral region are formed on the stack layer of stepped region
Part.
In this step, can be by a part of the stack layer of removal stepped region to form hierarchic structure, and at least remove
A part of the stack layer of peripheral region.This 2 steps can be completed in same removal process.Such as forming hierarchic structure
In the process, a part of the stack layer of peripheral region is removed together.The mode for removing stack layer may include lithography and etching.This is this
Field routine techniques, it is not reinflated herein.After the completion of this step, the first stop-layer position with peripheral region will form in core space
In the second stop-layer of sustained height.
In the sectional view of the semiconductor structure exemplified by Fig. 2 D, remained in the core space 210 of semiconductor structure 200d
For stack layer as stacked structure 211, stepped region 220 forms hierarchic structure 221, and then eliminates stack layer in peripheral region, dew
First stop-layer 203 out.There is the dummy gate layer 211a (or grid layer) and wall being alternately stacked in stacked structure 211
211b.Dummy gate layer 211a comes from first material layer 204a above-mentioned, and wall 211b then comes from second material layer above-mentioned
204b.Stacked structure 211 can also have the second stop-layer 211c, be located at same height with the first stop-layer 203 of peripheral region 230
Degree.During removing stack layer, there is recess 223, and the heap formed with remaining part stack layer in stepped region 220
Stack structure 222 is located at the side wall of the first insulating layer of peripheral region 230.Stacked structure 222 can have inclining towards hierarchic structure
Prism S.
In step 110, second insulating layer is formed on core space, stepped region and peripheral region.
In this step, second insulating layer is covered on the semiconductor structure that step 108 is formed, second insulating layer is distributed in
Core space, stepped region and peripheral region.Second insulating layer can play the role of for being isolated with peripheral region stepped region.
In the sectional view of the semiconductor structure exemplified by Fig. 2 E, the core space 210 of semiconductor structure 200e, stepped region
220 and peripheral region 230 on cover second insulating layer 205.In this example, second insulating layer 205 has the first sublayer 205a
With the second sublayer 205b.The material of first sublayer 205a and the second sublayer 205b are, for example, silicon nitride, silica, silicon carbide, nitrogen
Silica, aluminium oxide etc..By taking silica as an example, the first sublayer 205a and the second sublayer 205b can have different manufacture crafts.
First sublayer 205a can be to be formed with high-density plasma chemical vapor deposition (HDP CVD) technique.Second sublayer 205b
It can be grown and be formed using TEOS source.
In step 112, the second insulating layer of core space and peripheral region is removed.
In this step, core space and the undesirable second insulating layer in peripheral region are removed, and retain stepped region second is exhausted
Edge layer.In this step, the first stop-layer and the second stop-layer (if yes) can allow stops the step of removal second insulating layer
In desired height.
In the sectional view of the semiconductor structure exemplified by Fig. 2 F, the core space 210 of semiconductor structure 200f and peripheral region
Second insulating layer in 230 is removed, and leaves the part second insulating layer 205 ' of stepped region.Remove second insulating layer 205
Method be, for example, lithography and etching, it is not reinflated herein.In etching process, the first stop-layer 203 and the second stop-layer
211c protects the core space 210 below them and the structure of peripheral region 230.Here, second insulating layer 205 and the first stop-layer
203, higher etching ratio is needed between the second stop-layer 211c.Such as when second insulating layer 205 is oxide (as aoxidized
Silicon) when, the first stop-layer 203 and the second stop-layer 211c are, for example, nitride (such as silicon nitride).
In step 114, the second insulating layer of stepped region is planarized.
In this step, the semiconductor structure that step 112 obtains is planarized, thus make include peripheral region part
The whole surface of second insulating layer is smooth.During planarization, the first stop-layer of peripheral region can make planarization stop
Only in the height where its surface.When core space has the second stop-layer, the second stop-layer is it is also possible that planarization stops at
Height where its surface.
Part in the sectional view of the semiconductor structure exemplified by Fig. 2 G, in the peripheral region 220 of semiconductor structure 200g
Second insulating layer has been flattened, and obtains flat insulating regions 224.Insulating regions 224 may include the first subregion 224a and
Second subregion 224b, the two can be made of different technique and/or material.Illustrative planarization method is, for example, to be changed
It learns mechanical lapping (CMP).
In the stack layer planarization process of the present embodiment, it is only necessary in the removal core space of step 112 and peripheral region
One of lithography step is carried out in the step for second insulating layer, therefore can be omitted one of lithography step compared to usual manner.
Flow chart has been used to be used to illustrate operation performed by method according to an embodiment of the present application herein.It should be understood that
, the operation of front not necessarily accurately carries out in sequence.On the contrary, various steps can be handled according to inverted order or simultaneously
Suddenly.Meanwhile or during other operations are added to these, or from these processes remove a certain step or number step operation.
For example, step 104 can be completed jointly by 2 steps.Fig. 3 A-3B is one embodiment of the invention in peripheral region shape
At the schematic diagram of the first insulating layer and the first stop-layer.With reference to shown in Fig. 3 A, sequentially formed on semiconductor structure 300a first
The first initial initial stop-layer 203a of insulating layer 202a and first with preset thickness, then as Fig. 3 B removes core space 210
With the first stop-layer and the first insulating layer of stepped region 220, to obtain the first stop-layer 203 positioned at peripheral region 230 and the
One insulating layer 202.
Above-described embodiment is formed by semiconductor structure, and using subsequent conventional steps, three-dimensional storage can be obtained
Part.Semiconductor structure 200g, which is formed by, with reference to the present embodiment herein describes three-dimensional storage according to an embodiment of the invention
Device.Three-dimensional storage may include core space 210, stepped region 220 and peripheral region 230.Stepped region 220 has hierarchic structure 221.Week
Border area 230 has the first insulating layer 202 of cladding peripheral circuit 231.First side wall of the insulating layer 202 towards hierarchic structure 221
With stacked structure 222, stacked structure 222 is identical as the height of hierarchic structure 221.
Further, three-dimensional storage may include the insulating regions 224 between hierarchic structure 221 and stacked structure 222.
In one embodiment, stacked structure 222 has the inclined side S towards hierarchic structure.
In one embodiment, peripheral region 230 also has the first stop-layer 203 of the first insulating layer 202 of covering.First stops
Only layer 203 be used to allowing etching stopping in manufacturing process, and be retained in final three-dimensional storage.
Fig. 4 is the schematic diagram of remaining stacked structure in the three-dimensional storage of one embodiment of the invention.Refering to what is shown in Fig. 4,
In the three-dimensional storage to complete, stacked structure 222 is remained, with inclined side S.
The other details of the three-dimensional storage of the present embodiment can refer to description above, not reinflated herein.
Fig. 5 A-5I is the flattening method flow chart as a kind of stack layer of the three-dimensional storage compared.With reference to Fig. 5 A
It is shown, it may include substrate 501 in semiconductor structure 500a.Substrate 501 can be divided into core space 510, stepped region 520 and peripheral region
530.Such as peripheral circuit 531 has been formd on the substrate 501 of peripheral region and has covered the protective layer 532 of peripheral circuit.It connects
As shown in Figure 5 B, the first insulating layer 502 is formd on the peripheral region 430 of semiconductor structure 500b.Then in semiconductor structure
Stack layer 504 is formd on the core space 510 of 500b, stepped region 520 and peripheral region 530, obtains the semiconductor structure such as Fig. 5 C
500b.Stack layer 504 mainly includes first material layer 504a and the alternately stacked lamination of second material layer 504b.Then such as Fig. 5 D
It is shown, hierarchic structure 521 is formed by a part of the stack layer of removal stepped region 520.Simultaneously in semiconductor structure 500d
In, stack layer is remained in core space 510 as stacked structure 511, and then eliminate stack layer in peripheral region 530, expose the
One insulating layer 502.In addition, being located in stepped region 520 there are also the stacked structure 522 that the remaining part stack layer in part is formed
The side wall of first insulating layer 502 of peripheral region 530.The height of stacked structure 522 is less than hierarchic structure 521.Then such as Fig. 5 E,
Second insulating layer 505 is covered on the core space 510 of semiconductor structure 500e, stepped region 520 and peripheral region 530.In this example
In, second insulating layer 505 has the first sublayer 505a and the second sublayer 505b.Then as illustrated in figure 5f, semiconductor structure is removed
Second insulating layer in the peripheral region 530 of 500f is removed, and leaves core space 510, the part second of stepped region 520 is insulated
Layer 505 '.Then as depicted in fig. 5g, covered on the first insulating layer 502 and part second insulating layer 505 ' of semiconductor structure 500g
Lid etching stop layer 506.Then as illustrated in fig. 5h, in the part second insulating layer of semiconductor structure 500h removal core space 510
With partial etching stop-layer 506, retain part second insulating layer 505 " and stepped region 520 and the peripheral region of stepped region 520
530 partial etching stop-layer 506.Finally as shown in fig. 5i, part second insulating layer 505 " and the part of stepped region 520 are removed
Etching stop layer 506 obtains flat semiconductor structure 500i.
Compared with the flattening method shown in Fig. 5 A-5I, in the embodiment of the present invention, it is only necessary to which a photoetching can make heap
Stack flat.And with reference to shown in Fig. 2 E-2G, in the embodiment of the present invention, it need not cover and stop on insulating layer 205,205 '
Only layer, therefore while planarizing to the semiconductor structure 200f of Fig. 2 F, will grind comparatively fast.In contrast, to the half of Fig. 5 H
When conductor structure 500h is planarized, it will need first to grind off the partial etching stop-layer 506 ' on surface, grinding rate decline.
In the context of the present invention, three-dimensional storage can be 3D flash memory, such as 3D nand flash memory.Three-dimensional storage
Type can be charge storage type flash memory or floating gate type flash memory.
The application has used particular words to describe embodiments herein.As " one embodiment ", " embodiment ",
And/or " some embodiments " means a certain feature relevant at least one embodiment of the application, structure or feature.Therefore, it answers
Emphasize and it is noted that " embodiment " or " one embodiment " that is referred to twice or repeatedly in this specification in different location or
" alternate embodiment " is not necessarily meant to refer to the same embodiment.In addition, certain in one or more embodiments of the application
Feature, structure or feature can carry out combination appropriate.
Although the present invention is described with reference to current specific embodiment, those of ordinary skill in the art
It should be appreciated that above embodiment is intended merely to illustrate the present invention, can also make in the case where no disengaging spirit of that invention
Various equivalent change or replacement out, therefore, as long as to the variation of above-described embodiment, change in spirit of the invention
Type will all be fallen in the range of following claims.
Claims (14)
1. a kind of flattening method of the stack layer of three-dimensional storage, comprising the following steps:
Substrate is provided, the substrate has core space, stepped region and peripheral region；
The first insulating layer and the first stop-layer with preset thickness are sequentially formed in peripheral region；
Stack layer is formed in the core space, stepped region and peripheral region；
Hierarchic structure is formed on the stack layer of the stepped region, and at least removes a part of the peripheral region stack layer；
Second insulating layer is formed on the core space, stepped region and peripheral region；
Remove the second insulating layer of the core space and peripheral region；
The second insulating layer of stepped region is planarized.
2. the method according to claim 1, wherein in the step of forming the stack layer, the core space
The upper surface of stack layer and the upper surface of the first stop-layer of the peripheral region are generally concordant.
3. being stacked the method according to claim 1, wherein being formed in the core space, stepped region and peripheral region
In the step of layer, the stack layer of the core space is located at the second of sustained height with the first stop-layer with the peripheral region and stops
Only layer.
4. the method according to claim 1, wherein at least removing the step of a part of the peripheral region stack layer
It suddenly is executed during forming the hierarchic structure.
5. method according to claim 1 or 2, which is characterized in that planarized to the second insulating layer of stepped region
Step stops at the first stop-layer of the peripheral region.
6. method according to claim 1 or 3, which is characterized in that planarized to the second insulating layer of stepped region
Step stops at the first stop-layer of the peripheral region and the second stop-layer of the core space.
7. the method according to claim 1, wherein when removing the stack layer of the peripheral region, on the periphery
The side wall residual fraction stack layer of first insulating layer in area.
8. the method according to claim 1, wherein it is exhausted to sequentially form first with preset thickness in peripheral region
The step of edge layer and the first stop-layer includes:
The first initial insulating layer and the first initial stop-layer with preset thickness are sequentially formed on the semiconductor structure；
The the first initial stop-layer and the first initial insulating layer of the core space and stepped region are removed, to obtain being retained in described
The first stop-layer and the first insulating layer of peripheral region.
9. the method according to claim 1, wherein removing the second insulating layer of the core space and peripheral region
Step includes carrying out lithography and etching.
10. the method according to claim 1, wherein the step of removing the stack layer of the peripheral region includes light
It carves and etches.
11. a kind of three-dimensional storage, including core space, stepped region and peripheral region, the stepped region has hierarchic structure, the week
Border area has the first insulating layer of cladding peripheral circuit, wherein first insulating layer has towards the side wall of the hierarchic structure
Stacked structure, the stacked structure are identical as the height of the hierarchic structure.
12. three-dimensional storage as claimed in claim 11, which is characterized in that further include being located at the hierarchic structure and the heap
Insulating regions between stack structure.
13. three-dimensional storage as claimed in claim 11, which is characterized in that the stacked structure has towards the ladder knot
The inclined side of structure.
14. three-dimensional storage as claimed in claim 12, which is characterized in that the peripheral region also has covering described first absolutely
First stop-layer of edge layer.
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