CN109244076B - 3D memory device - Google Patents
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- CN109244076B CN109244076B CN201811026959.7A CN201811026959A CN109244076B CN 109244076 B CN109244076 B CN 109244076B CN 201811026959 A CN201811026959 A CN 201811026959A CN 109244076 B CN109244076 B CN 109244076B
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- 238000003860 storage Methods 0.000 abstract description 7
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
Disclosed is a 3D memory device including: a core region having a channel hole; an auxiliary region comprising a virtual hole and/or a trench; the bottom layer of the 3D storage device along the direction perpendicular to the surface of the 3D storage device is a substrate, wherein an epitaxial layer is arranged at the bottom of the channel hole, and an oxide layer is arranged at the bottom of the virtual hole and/or the groove. According to the embodiment of the invention, the oxide layer is formed in the virtual hole and/or the groove of the auxiliary area, and the epitaxial layer is formed in the channel hole of the core area, so that the problems of uneven epitaxial layer, current leakage and the like caused by forming the epitaxial layer are solved.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a 3D memory device.
Background
The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As feature sizes of semiconductor fabrication processes become smaller, memory density of memory devices becomes higher. In order to further increase the storage density, three-dimensional structured memory devices (i.e., 3D memory devices) have been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can improve integration in multiple per unit area of a wafer, and can reduce cost.
The 3D memory device includes a core region forming a memory cell and an auxiliary region forming a peripheral structure. In a 3D memory device, such as a 3D NAND flash memory, an epitaxial layer needs to be formed at the bottom of a channel hole of a re-core region. During this process, the Dummy Hole (Dummy Hole) and Trench (Trench) bottom in the barrier (barrier) of the through array contact (Through Array Contact, TAC) area are also open in some auxiliary areas, such as the Step area (SS), so that an epitaxial layer is formed at the Dummy Hole (Dummy Hole) and Trench bottom together, for example.
The diameter and height of the trench and the trench hole at the dummy hole and the TAC barrier are different, resulting in problems of non-uniformity of the epitaxial layer, current leakage, and the like.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a 3D memory device that can solve the problems of non-uniformity of an epitaxial layer, current leakage, and the like due to the formation of the epitaxial layer in an auxiliary region.
According to an aspect of the present invention, there is provided a 3D memory device including:
a core region having a channel hole;
an auxiliary region comprising a virtual hole and/or a trench;
the bottom layer of the 3D storage device along the direction perpendicular to the surface of the 3D storage device is a substrate, wherein an epitaxial layer is arranged at the bottom of the channel hole, and an oxide layer is arranged at the bottom of the virtual hole and/or the groove.
Preferably, the auxiliary region includes a stepped region having the dummy hole therein and a through array contact region having the trench therein.
Preferably, the channel hole, the dummy hole and the trench have a structure of blocking insulation layer-charge trapping layer-tunneling insulation layer-channel layer-dielectric layer.
Preferably, the channel hole is closed when the oxide layer is formed at the bottom of the dummy hole and the trench.
Preferably, the dummy hole and the trench are closed when an epitaxial layer is formed at the bottom of the channel hole.
Preferably, the channel hole extends to a bottom substrate of the semiconductor structure, and a first groove with a certain depth is formed in the substrate of the semiconductor structure.
Preferably, the epitaxial layer is formed in the first groove.
Preferably, the dummy hole and the trench extend to a bottom substrate of the semiconductor structure, and a second groove with a certain depth is formed in the substrate of the semiconductor structure.
Preferably, the oxide layer is formed in the second recess.
Preferably, the core region includes a stacked structure including a plurality of interlayer insulating layers and a plurality of sacrificial layers alternately stacked.
According to the 3D memory device provided by the invention, the oxide layer is formed in the virtual hole and/or the groove of the auxiliary area, and the epitaxial layer is formed in the channel hole of the core area, so that the problems of uneven epitaxial layer, current leakage and the like caused by forming the epitaxial layer in the auxiliary area are solved.
Furthermore, an oxide layer is formed in the virtual hole and/or the groove through the same mask layer, and then an epitaxial layer is formed in the channel hole, so that the process difficulty is simplified.
Furthermore, an epitaxial layer is formed in the channel hole through the same mask layer, and then an oxide layer is formed in the virtual hole and/or the groove, so that the process difficulty is simplified.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a flowchart of a method of manufacturing a 3D memory device according to a first embodiment of the present invention;
fig. 2A to 2L are cross-sectional views showing various stages of a manufacturing method of a 3D memory device according to a first embodiment of the present invention;
fig. 3 illustrates a flowchart of a method of manufacturing a 3D memory device according to another embodiment of the present invention;
fig. 4A to 4L are cross-sectional views showing various stages of a manufacturing method of a 3D memory device according to a first embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples.
The term "above" as used herein refers to above the plane of the substrate, and may refer to direct contact between materials, or may be spaced apart.
Fig. 1 shows a flowchart of a method of manufacturing a 3D memory device according to a first embodiment of the present invention. Fig. 2 a-2 l show cross-sectional views of stages of a method of manufacturing a 3D memory device according to a first embodiment of the invention.
In step S102, a semiconductor structure is provided.
The semiconductor structure is at least a portion of a structure that will be used in subsequent processes to ultimately form a 3D memory device. The semiconductor structure may include a core region and an auxiliary region, wherein the core region is a region including the memory cell, and the auxiliary region is a region including the peripheral structure.
In the cross-sectional view of the semiconductor structure shown in fig. 2A, the semiconductor structure 200a includes a core region 210, a step region 220, and a Through Array Contact (TAC) region 230. The core region 210 is used to form a memory array, the step region 220 is used to form interconnects, and the TAC region 230 is used to form through-array barrier structures (Through Array Barrier, TAB). It should be noted that the layout of the core region 210, the step region 220, and the TAC region 230 in the figure does not necessarily represent the positions of these regions in the actual 3D memory device.
The core region 210, the step region 220, and the TAC region 230 may have a common substrate 201. The material of the substrate 201 is, for example, silicon. A stack structure 240 and an insulating structure 250 are provided on the substrate 201, the stack structure 240 covering the core region 210, and the insulating structure 250 covering the step region 220 and the TAC region 230. The insulating structure 250 is composed of, for example, silicon oxide.
The stacked structure 240 includes a plurality of interlayer insulating layers 241 and a plurality of sacrificial layers 242 alternately stacked, and the sacrificial layers 242 are replaced with conductor layers. In this embodiment, the interlayer insulating layer 241 is made of silicon oxide, the sacrificial layer 242 is made of silicon nitride, for example, and a Chemical Vapor Deposition (CVD), an Atomic Layer Deposition (ALD) or other suitable deposition method may be used to sequentially and alternately deposit an inter-metal dielectric layer (e.g., silicon oxide, etc.) and a metal replacement sacrificial layer (e.g., silicon nitride, etc.) on the substrate 201.
A dielectric layer 260 and a first hard mask layer 270 are also provided on the stacked structure 240 and the insulating structure 250. Dielectric layer 260 is comprised of, for example, silicon oxide and first hard mask layer 270 is comprised of, for example, silicon nitride.
Although an exemplary composition of an initial semiconductor structure is described herein, it is understood that one or more features may be omitted from, substituted for, or added to this semiconductor structure. Furthermore, the illustrated materials of the layers are merely exemplary, and materials such as substrate 201 may also be other silicon-containing substrates such as SOI (silicon on insulator), siGe, si: C, and the like.
In step S104, the semiconductor structure is etched to form a channel hole in the core region and a dummy hole and/or trench in the auxiliary region.
Here, the channel holes, the dummy holes and the trenches are formed in the core region and the auxiliary region of the semiconductor structure by the same photolithography process. When the auxiliary region includes the stepped region 220, a dummy hole may be formed. When the auxiliary region includes the TAC region 230, a trench may be formed. When the auxiliary region includes the step region 220 and the TAC region 230, the dummy holes and the trenches may be formed at the same time.
In this step, the process of photolithography may be various known suitable steps. For example, a hard mask layer is grown, exposed to light after covering the photoresist layer, and then etched, cleaned, and the like.
In the cross-sectional view of the semiconductor structure illustrated in fig. 2B, the core region 210 of the semiconductor structure 200B has a plurality of channel holes 211 therein. Each channel hole 211 penetrates through the first hard mask layer 270, the dielectric layer 260 and the stacked structure 240 to the substrate 201, forming a first recess of a certain depth. The stepped region 220 has a plurality of dummy holes 221 therein; the TAC region 230 has a plurality of grooves 231 therein. Each dummy hole 221 and trench 231 penetrates through the first hard mask layer 270, the dielectric layer 260 and the insulating structure 250 to reach the substrate 201, forming a second recess of a certain depth.
In step S106, a blocking layer is formed on the semiconductor structure to block the channel hole, the dummy hole and/or the trench.
In this embodiment, a blocking material is deposited on the semiconductor structure at a high rate to form a blocking layer 280, the blocking layer 280 blocking the channel holes 211, dummy holes 221, and trenches 231. The encapsulation layer 280 is composed of silicon oxide, for example.
In step S108, a second hard mask layer is covered on the encapsulation layer.
In this embodiment, the second hard mask layer 290 is covered so as to form an oxide layer, an epitaxial layer, at the bottom of the subsequent dummy holes and/or trenches, respectively, for the bottom of the channel holes.
In the cross-sectional view of the semiconductor structure illustrated in fig. 2C, the surface of the semiconductor structure 200C is covered with a capping layer 280 and a second hard mask layer 290. The second hard mask layer 290 herein may include an amorphous carbon layer (e.g., APFM (a-C)) and an anti-reflective dielectric coating (e.g., silicon oxynitride (SiON)). However, it is understood that other materials may be selected for the second hard mask layer 290. The number of layers of the second hard mask layer 290 may also vary, for example, the second hard mask layer 290 may have only one layer or more than two layers.
In step S110, the second hard mask layer and the sealing layer located in the auxiliary area are etched to expose the dummy holes and/or trenches.
The cross-sectional views of the semiconductor structure illustrated in fig. 2D-2E illustrate the process of this step, where the surface of the semiconductor structure 200c is first covered with a photoresist layer 300, exposed through a photomask for the auxiliary area, and then etched to form a desired photoresist pattern, resulting in the semiconductor structure 200D, where the photoresist layer 300 includes a photoresist coating (Photo Resist Coating, PR); thereafter, the second hard mask layer 290 and the blocking layer 280 located in the auxiliary area are etched on the semiconductor structure 200d by means of a photoresist pattern and the dummy holes 221 and/or trenches 231 are exposed, resulting in a semiconductor structure 200e, wherein the blocking layer 280 only blocks the channel holes 211 of the core area 210.
In a preferred embodiment, the etching is also followed by a dry photoresist removal (Asher) and a WET Clean (WET Clean).
In step S112, an oxide layer is formed at the bottom of the dummy hole and the trench.
In the cross-sectional view of the semiconductor structure illustrated in fig. 2F, an oxide, such as silicon oxide, is deposited in the semiconductor structure 200 e. The deposited oxide fills into the dummy holes 221 of the step region 220 and/or the trenches 231 of the TAC region 230, and in particular, the second grooves, thereby forming the semiconductor structure 200f. Methods of forming the oxide layer are, for example, in-situ vapor generation (In-Situ Steam Generation, ISSG), thermal oxidation (Thermal Oxidation), or atomic layer deposition (Atomic Layer Deposition, ALD), etc.
In step S114, the blocking layer in the core region is removed to expose the channel hole.
In the cross-sectional view of the semiconductor structure illustrated in fig. 2G, the blocking layer 280 located in the core region is removed to expose the channel hole 211, and then WET cleaning (WET Clean) is performed, thereby forming the semiconductor structure 200G. The method of removing the encapsulation layer 280 of the core region may be, for example, planarization, such as Chemical Mechanical Polishing (CMP).
In step S116, an epitaxial layer is formed at the bottom of the channel hole.
In the cross-sectional view of the semiconductor structure illustrated in fig. 2H, an epitaxial layer is formed at the bottom of the channel hole of the core region 210 of the semiconductor structure 200g, specifically, within the first recess, thereby forming the semiconductor structure 200H. The material of the epitaxial layer is, for example, silicon. The epitaxial layer may be formed, for example, by selective epitaxial growth (Selective Epitaxial Growth, SEG).
In a preferred embodiment, step S118 (not shown) and step S120 (not shown) are also included.
In step S118, a single-layer and/or multi-layer composite structure of oxide-nitride-oxide-polysilicon-oxide is formed in the channel hole, the dummy hole and the trench in order, but the material is not limited to the materials and combinations mentioned herein.
In the formation of the 3D memory device, other processes are performed for each of the channel holes 211, each of the dummy holes 221, and each of the trenches 231, in addition to the epitaxial layer at the bottom of each of the channel holes 211, each of the dummy holes 221, and the oxide layer of each of the trenches 231.
In the cross-sectional view of the semiconductor structure illustrated in fig. 2I, for example, an oxide-nitride-oxide-polysilicon-oxide (ONOPO) structure may also be formed within the channel hole 211 along its sidewalls from the outside to the inside. The ONOPO structure at the bottom of the channel hole 211 is etched until the epitaxial layer 212 is leaked and the epitaxial layer 212 is over-etched to a certain depth, thereby forming the semiconductor structure 200i.
The ONOPO structure is formed from the outside to the inside, and is a blocking insulating layer 213, a charge trapping layer 214, a tunneling insulating layer 215, a channel layer 216, and a dielectric layer 217. Layers 213, 214, and 215 constitute a storage layer. In the example of fig. 2I, an exemplary material of the blocking insulating layer 213 and the tunneling insulating layer 215 is silicon oxide, and an exemplary material of the charge trapping layer 214 is silicon nitride, forming a silicon oxide-silicon nitride-silicon oxide (ONO) structure; an exemplary material for the channel layer 216 is polysilicon. It will be appreciated that other materials may be selected for these layers. For example, the material of the blocking insulating layer 213 may include a high K (dielectric constant) oxide layer; the charge trapping layer 214 may be a floating gate structure, for example comprising a polysilicon material; the material of channel layer 216 may include single crystal silicon, single crystal germanium, siGe, si: C, siGe: C, siGe: H, and the like semiconductor materials. An exemplary material for the dielectric layer 217 is silicon oxide.
In the cross-sectional view of the semiconductor structure illustrated in fig. 2J, the masking oxide layer 217 is removed within the channel hole 211 and then a semiconductor material growth (e.g., polysilicon growth) is performed, thereby placing the channel layer 216 in communication with the epitaxial layer 212 to form the semiconductor structure 200J. This step typically forms a channel layer on the surface of the semiconductor structure.
In the process performed for each channel hole, a filling layer 218 may be further formed in the channel hole 211, and in the cross-sectional view of the semiconductor structure illustrated in fig. 2K, each filling layer 218 is formed in each channel hole 211 of the core region 210 of the semiconductor structure 200j. An exemplary material for the filler layer 218 is silicon oxide. The filler layer 218 is formed, for example, by atomic layer deposition. The filling layer 218 fills each of the channel holes 211. To this end, the process performed for the channel hole 211 ends.
Likewise, an oxide-nitride-oxide-polysilicon-oxide (ONOPO) structure may be formed in the dummy hole 221 sequentially from the outside to the inside along the sidewalls thereof. The ONOPO structure at the bottom of the dummy hole 221 is etched until the oxide layer 222 is leaked and the oxide layer 222 is over-etched to a certain depth, thereby forming the semiconductor structure 200i. The ONOPO structure is formed from the outside to the inside as a blocking insulating layer 223, a charge trapping layer 224, a tunneling insulating layer 225, a channel layer 226, and a dielectric layer 227, respectively. The dielectric layer 227 within the dummy holes 221 is removed and then a semiconductor material growth (e.g., polysilicon growth) is performed, thereby connecting the channel layer 226 to the oxide layer 222 to form the semiconductor structure 200j. This step typically forms a channel layer on the surface of the semiconductor structure. Also formed within dummy holes 221 may be a fill layer 228, an exemplary material for fill layer 228 is silicon oxide. The fill layer 228 is formed, for example, by atomic layer deposition. The filling layer 228 fills each dummy hole 221. To this end, the process performed for the dummy holes 221 ends.
Similarly, an oxide-nitride-oxide-polysilicon-oxide (ONOPO) structure may be formed within the trench 231, sequentially from the outside to the inside along the sidewalls thereof. The ONOPO structure at the bottom of trench 231 is etched until oxide layer 232 is leaked and oxide layer 232 is over-etched to a certain depth, thereby forming semiconductor structure 200i. The ONOPO structure is formed sequentially from the outside to the inside as a blocking insulating layer 233, a charge trapping layer 234, a tunneling insulating layer 235, a channel layer 236, and a dielectric layer 237, respectively. The dielectric layer 237 within the trench 231 is removed and then a semiconductor material growth (e.g., polysilicon growth) is performed, thereby placing the channel layer 236 in communication with the oxide layer 232 to form the semiconductor structure 200j. This step typically forms a channel layer on the surface of the semiconductor structure. A fill layer 238 may also be formed within the trench 231, with an exemplary material for the fill layer 238 being silicon oxide. The fill layer 238 is formed, for example, by atomic layer deposition. The filling layer 238 fills each trench 231. To this point, the process performed for the trench 231 ends.
In step S120, the sacrificial layer to be located in the laminated structure of the core region is replaced with a conductor layer.
In the cross-sectional view of the semiconductor structure shown in fig. L, the sacrificial layer 241 in the stacked structure 240 is replaced with a conductor layer 243, resulting in the semiconductor structure 200L.
According to the manufacturing method of the 3D memory device, the oxide layer is formed in the virtual hole and/or the groove of the auxiliary area, the epitaxial layer is formed in the channel hole of the core area, and the problems of uneven epitaxial layer, current leakage and the like caused by the fact that the epitaxial layer is formed in the auxiliary area are solved.
Furthermore, an oxide layer is formed in the virtual hole and/or the groove through the same mask layer, and then an epitaxial layer is formed in the channel hole, so that the process difficulty is simplified.
Fig. 3 illustrates a flowchart of a method of manufacturing a 3D memory device according to another embodiment of the present invention; fig. 4A to 4K are cross-sectional views showing various stages of a manufacturing method of a 3D memory device according to a first embodiment of the present invention.
In step S302, a semiconductor structure is provided.
The semiconductor structure is at least a portion of a structure that will be used in subsequent processes to ultimately form a 3D memory device. The semiconductor structure may include a core region and an auxiliary region, wherein the core region is a region including the memory cell, and the auxiliary region is a region including the peripheral structure.
In the cross-sectional view of the semiconductor structure shown in fig. 4A, the semiconductor structure 400a includes a core region 410, a step region 420, and a Through Array Contact (TAC) region 430. The core region 410 is used to form a memory array, the step region 420 is used to form interconnects, and the TAC region 430 is used to form a through array barrier structure (Through Array Barrier, TAB). It should be noted that the layout of the core region 410, the step region 420 and the TAC region 430 in the figure does not necessarily represent the positions of these regions in the actual 3D memory device.
The core region 410, the step region 420, and the TAC region 430 may have a common substrate 401. The material of the substrate 401 is, for example, silicon. A stack structure 440 and an insulating structure 450 are provided on the substrate 401, the stack structure 440 covering the core region 410, and the insulating structure 450 covering the step region 420 and the TAC region 430. The insulating structure 450 is composed of, for example, silicon oxide.
The stacked structure 440 includes a plurality of interlayer insulating layers 441 and a plurality of sacrificial layers 442 stacked alternately, and the sacrificial layers 442 are replaced with conductor layers. In this embodiment, the interlayer insulating layer 441 is made of silicon oxide, the sacrificial layer 442 is made of silicon nitride, for example, and a Chemical Vapor Deposition (CVD), an Atomic Layer Deposition (ALD) or other suitable deposition method may be used to sequentially and alternately deposit an inter-metal dielectric layer (e.g., silicon oxide, etc.) and a metal replacement sacrificial layer (e.g., silicon nitride, etc.) on the substrate 401.
A dielectric layer 460 and a first hard mask layer 470 are also provided on the stacked structure 440 and the insulating structure 450. The dielectric layer 460 is comprised of, for example, silicon oxide and the first hard mask layer 470 is comprised of, for example, silicon nitride.
Although an exemplary composition of an initial semiconductor structure is described herein, it is understood that one or more features may be omitted from, substituted for, or added to this semiconductor structure. Furthermore, the illustrated materials of the layers are merely exemplary, and materials such as substrate 401 may also be other silicon-containing substrates such as SOI (silicon on insulator), siGe, si: C, and the like.
In step S304, the semiconductor structure is etched to form a channel hole in the core region and a dummy hole and/or trench in the auxiliary region.
Here, the channel holes, the dummy holes and the trenches are formed in the core region and the auxiliary region of the semiconductor structure by the same photolithography process. When the auxiliary region includes the stepped region 420, a dummy hole may be formed. When the auxiliary region includes the TAC region 430, a trench may be formed. When the auxiliary region includes the step region 420 and the TAC region 430, the dummy holes and the trenches may be formed at the same time.
In this step, the process of photolithography may be various known suitable steps. For example, a hard mask layer is grown, exposed to light after covering the photoresist layer, and then etched, cleaned, and the like.
In the cross-sectional view of the semiconductor structure illustrated in fig. 4B, the core region 410 of the semiconductor structure 400B has a plurality of channel holes 411 therein. Each channel hole 411 penetrates the first hard mask layer 470, the dielectric layer 460 and the stack structure 440 to reach the substrate 401, forming a first recess of a certain depth. The stepped region 420 has a plurality of virtual holes 421 therein; the TAC region 430 has a plurality of grooves 431 therein. Each dummy hole 421 and trench 431 penetrates through the first hard mask layer 470, the dielectric layer 460 and the insulating structure 450 to reach the substrate 401, forming a second recess of a certain depth.
In step S306, a blocking layer is formed on the semiconductor structure to block the channel hole, the dummy hole, and/or the trench.
In this embodiment, a capping material is deposited on the semiconductor structure at a high rate to form a capping layer 480, the capping layer 480 capping the channel holes 411, dummy holes 421, and trenches 431. The encapsulation layer 480 is composed of silicon oxide, for example.
In step S308, a second hard mask layer is covered on the encapsulation layer.
In this embodiment, the second hard mask layer 490 is covered to form an oxide layer, an epitaxial layer, at the bottom of the subsequent dummy holes and/or trenches, respectively, at the bottom of the channel holes.
In the cross-sectional view of the semiconductor structure illustrated in fig. 4C, the surface of the semiconductor structure 400C is covered with the encapsulation layer 480 and the second hard mask layer 490. The second hard mask layer 490 herein may include an amorphous carbon layer (e.g., APFM (a-C)) and an antireflective dielectric coating (e.g., silicon oxynitride (SiON)). However, it is understood that other materials may be selected for the second hard mask layer 490. The number of layers of the second hard mask layer 490 may also vary, for example, the second hard mask layer 490 may have only one layer or more than two layers.
In step S310, the second hard mask layer and the blocking layer in the core region are etched to expose the channel hole.
The cross-sectional views of the semiconductor structure illustrated in fig. 4D-4E illustrate the process of this step, where the surface of the semiconductor structure 400c is first covered with a photoresist layer 500, exposed through a photomask for the auxiliary area, and then etched to form the desired photoresist pattern, resulting in the semiconductor structure 400D, where the photoresist layer 500 includes a photoresist coating (Photo Resist Coating, PR); thereafter, a second hard mask layer 490 and a blocking layer 480 located in the core region are etched on the semiconductor structure 400d by means of a photoresist pattern and the channel holes 411 are exposed, resulting in a semiconductor structure 400e, wherein the blocking layer 480 only blocks the dummy holes 421 and/or the trenches 431 of the auxiliary region.
In a preferred embodiment, the etching is also followed by a dry photoresist removal (Asher) and a WET Clean (WET Clean).
In step S312, an epitaxial layer is formed at the bottom of the channel hole.
In the cross-sectional view of the semiconductor structure illustrated in fig. 4F, an epitaxial layer is formed at the bottom of the channel hole of the core region 410 of the semiconductor structure 400e, specifically, within the first recess, thereby forming the semiconductor structure 400F. The material of the epitaxial layer is, for example, silicon. The epitaxial layer may be formed, for example, by selective epitaxial growth (Selective Epitaxial Growth, SEG).
In step S314, the blocking layer in the auxiliary area is removed to expose the dummy holes and/or trenches.
In the cross-sectional view of the semiconductor structure illustrated in fig. 4G, the blocking layer 480 located in the auxiliary area is removed to expose the dummy holes 421 and/or the trenches 431, and then WET cleaning (WET Clean) is performed, thereby forming a semiconductor structure 400G. The method of removing the encapsulation layer 480 of the auxiliary area may be, for example, planarization, such as Chemical Mechanical Polishing (CMP).
In step S316, an oxide layer is formed at the dummy holes and the bottoms of the trenches.
In the cross-sectional view of the semiconductor structure illustrated in fig. 4H, an oxide, such as silicon oxide, is deposited in the auxiliary region of the semiconductor structure 400g. The deposited oxide fills into the dummy holes 421 of the step region 420 and/or the trenches 431 of the TAC region 430, and in particular, the second grooves, thereby forming the semiconductor structure 400h. Methods of forming the oxide layer are, for example, in-situ vapor generation (In-Situ Steam Generation, ISSG), thermal oxidation (Thermal Oxidation), or atomic layer deposition (Atomic Layer Deposition, ALD), etc.
In a preferred embodiment, step S318 (not shown) and step S320 (not shown) are also included.
In step S318, a blocking insulating layer-charge trapping layer-tunneling insulating layer-channel layer-dielectric layer is sequentially formed in the channel hole, the dummy hole and the trench, and the selected material may be a single-layer and/or multi-layer combination structure of oxide-nitride-oxide-polysilicon-oxide, but is not limited to the materials and combinations mentioned herein. In the formation of the 3D memory device, other processes are performed for each of the channel holes 411, each of the dummy holes 421, and each of the trenches 431, in addition to the epitaxial layer at the bottom of each of the channel holes 411, each of the dummy holes 421, and the oxide layer of each of the trenches 431.
In the cross-sectional view of the semiconductor structure illustrated in fig. 4I, for example, an oxide-nitride-oxide-polysilicon-oxide (ONOPO) structure may also be formed within the channel hole 411 along its sidewalls from the outside to the inside. The ONOPO structure at the bottom of the channel hole 411 is etched until the epitaxial layer 412 is leaked and the epitaxial layer 412 is over-etched to a certain depth, thereby forming the semiconductor structure 400i.
The ONOPO structure is formed from the outside to the inside, and is a blocking insulating layer 413, a charge trapping layer 414, a tunneling insulating layer 415, a channel layer 416, and a dielectric layer 417. Layers 413, 414, and 415 constitute a storage layer. In the example of fig. 4I, an exemplary material of the blocking insulating layer 413 and the tunneling insulating layer 415 is silicon oxide, and an exemplary material of the charge trapping layer 414 is silicon nitride, forming a silicon oxide-silicon nitride-silicon oxide (ONO) structure; an exemplary material for channel layer 416 is polysilicon. It will be appreciated that other materials may be selected for these layers. For example, the material of the barrier insulating layer 413 may include a high-K oxide layer; the charge trapping layer 414 may be a floating gate structure, for example comprising a polysilicon material; the material of channel layer 416 may include single crystal silicon, single crystal germanium, siGe, si: C, siGe: C, siGe: H, and the like semiconductor materials. An exemplary material for the dielectric layer 417 is silicon oxide.
In the cross-sectional view of the semiconductor structure illustrated in fig. 4J, the masking oxide layer 417 is removed within the channel hole 411 and then a semiconductor material growth (e.g., polysilicon growth) is performed, thereby placing the channel layer 416 in communication with the epitaxial layer 412 to form the semiconductor structure 400J. This step typically forms a channel layer on the surface of the semiconductor structure.
In the process performed for each channel hole, a filling layer 418 may also be formed in the channel hole 411, and in the cross-sectional view of the semiconductor structure illustrated in fig. 4K, each filling layer 418 is formed in each channel hole 411 of the core region 410 of the semiconductor structure 400j. An exemplary material for the filler layer 418 is silicon oxide. The fill layer 418 is formed, for example, by atomic layer deposition. The filling layer 418 fills each of the channel holes 411. To this end, the process performed for the channel hole 411 ends.
Likewise, an oxide-nitride-oxide-polysilicon-oxide (ONOPO) structure may be formed in the dummy hole 421 sequentially from the outside to the inside along the sidewall thereof. The ONOPO structure at the bottom of dummy hole 421 is etched until oxide layer 422 is leaked and oxide layer 422 is over-etched to a certain depth, thereby forming semiconductor structure 400i. The ONOPO structure is formed sequentially from the outside to the inside as a blocking insulating layer 423, a charge trapping layer 424, a tunneling insulating layer 425, a channel layer 426, and a dielectric layer 427, respectively. The dielectric layer 427 within the dummy holes 421 is removed and then semiconductor material growth (e.g., polysilicon growth) is performed, thereby placing the channel layer 426 in communication with the oxide layer 422 to form the semiconductor structure 400j. This step typically forms a channel layer on the surface of the semiconductor structure. Also formed within dummy holes 421 may be a fill layer 428, an exemplary material for fill layer 428 being silicon oxide. The filling layer 428 is formed by, for example, atomic layer deposition. The filling layer 428 fills each dummy hole 421. To this end, the process performed for the dummy holes 421 ends.
Similarly, an oxide-nitride-oxide-polysilicon-oxide (ONOPO) structure may be formed within trench 431 sequentially from the outside to the inside along the sidewalls thereof. The ONOPO structure at the bottom of trench 431 is etched until oxide layer 432 is leaked and oxide layer 432 is over-etched to a certain depth, thereby forming semiconductor structure 400i. The ONOPO structure is formed sequentially from the outside to the inside as a blocking insulating layer 433, a charge trapping layer 434, a tunneling insulating layer 435, a channel layer 436, and a dielectric layer 437, respectively. The dielectric layer 437 within the trench 431 is removed and then a semiconductor material growth (e.g., polysilicon growth) is performed, thereby placing the channel layer 436 in communication with the oxide layer 432 to form the semiconductor structure 400j. This step typically forms a channel layer on the surface of the semiconductor structure. A fill layer 438 may also be formed within the trench 431, with an exemplary material for the fill layer 438 being silicon oxide. The fill layer 438 is formed, for example, by atomic layer deposition. The fill layer 438 fills each trench 431. To this end, the process performed for trench 431 ends.
In step S320, the sacrificial layer to be located in the laminated structure of the core region is replaced with a conductor layer.
In the cross-sectional view of the semiconductor structure shown in fig. L, the sacrificial layer 241 in the stacked structure 240 is replaced with a conductor layer 443, resulting in a semiconductor structure 400L.
According to the manufacturing method of the 3D memory device, the oxide layer is formed in the virtual hole and/or the groove of the auxiliary area, the epitaxial layer is formed in the channel hole of the core area, and the problems of uneven epitaxial layer, current leakage and the like caused by the fact that the epitaxial layer is formed in the auxiliary area are solved.
Furthermore, an oxide layer is formed in the virtual hole and/or the groove through the same mask layer, and then an epitaxial layer is formed in the channel hole, so that the process difficulty is simplified.
A flowchart is used herein to describe the operations performed by the methods according to embodiments of the present application. It should be appreciated that the foregoing operations are not necessarily performed in order precisely. Rather, the various steps may be processed in reverse order or simultaneously. At the same time, other operations are added to or removed from these processes. For example, some steps are not necessary, and may be omitted or replaced with other steps.
The semiconductor structure formed by the embodiment can be subjected to the subsequent conventional steps to obtain the three-dimensional memory device.
Referring to fig. 2L and 4L, a three-dimensional memory device according to an embodiment of the present invention may include a core region (210/410), a step region (220/420), and a through array contact region (230/430). The core region has a channel hole (211/411) therein, the step region has a dummy hole (221/421) therein, and the through array contact region has a trench (231/431) therein. The bottom layer of the three-dimensional memory device along the direction perpendicular to the surface of the three-dimensional memory device is a substrate (201/401), wherein the bottom of the channel hole (211/411) is provided with an epitaxial layer, and the bottom of the virtual hole (221/421) and/or the groove (231/431) is provided with an oxide layer. The auxiliary region includes a stepped region (220/420) and a through-array contact region (230/430). The channel holes (211/411), dummy holes (221/421) and trenches (231/431) have a barrier insulating layer-charge trapping layer-tunneling insulating layer-channel layer-dielectric layer structure. The channel holes (211/411) are closed when an oxide layer is formed at the bottom of the dummy holes (221/421) and the trenches (231/431). The dummy holes (221/421) and the trenches (231/431) are closed when an epitaxial layer is formed at the bottom of the channel holes (211/411). The channel hole (211/411) extends to a bottom substrate (201/401) of the semiconductor structure and forms a first recess of a certain depth in the substrate of the semiconductor structure. The epitaxial layer is formed in the first groove. The dummy holes (221/421) and the trenches (231/431) extend to a bottom substrate (201/401) of the semiconductor structure, and a second groove of a certain depth is formed in the substrate of the semiconductor structure. The oxide layer is formed in the second groove. The core region (210/410) includes a stacked structure (240/440), the stacked structure (240/440) including a plurality of interlayer insulating layers (241/441) and a plurality of conductor layers (243/443) stacked alternately.
According to the 3D memory device provided by the invention, the oxide layer is formed in the virtual hole and/or the groove of the auxiliary area, and the epitaxial layer is formed in the channel hole of the core area, so that the problems of uneven epitaxial layer, current leakage and the like caused by forming the epitaxial layer in the auxiliary area are solved.
Other details of the three-dimensional memory device, such as the structure of the memory array, peripheral interconnections, etc., are not central to the present invention and are not described further herein.
In the context of the present invention, the three-dimensional memory device may be a 3D flash memory, such as a 3D nand flash memory.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (7)
1. A 3D memory device, comprising:
a core region having a channel hole;
an auxiliary region comprising a stepped region having a virtual hole therein and/or a through array contact region having a trench therein;
the bottom layer of the 3D memory device along the direction perpendicular to the surface of the 3D memory device is a substrate, wherein an epitaxial layer is arranged at the bottom of the channel hole, an oxide layer is arranged at the bottom of the virtual hole and/or the groove, the epitaxial layer and the oxide layer are not formed simultaneously, if the epitaxial layer is formed before the oxide layer, the virtual hole and the groove are closed when the epitaxial layer is formed at the bottom of the channel hole, and if the oxide layer is formed before the epitaxial layer, and the channel hole is closed when the oxide layer is formed at the bottom of the virtual hole and the groove.
2. The 3D memory device of claim 1, wherein the channel hole, dummy hole, and trench each have a barrier insulating layer-charge trapping layer-tunneling insulating layer-channel layer-dielectric layer structure therein.
3. The 3D memory device of claim 1, wherein the channel hole extends to an underlying substrate of the 3D memory device and forms a first recess of a depth in the substrate of the 3D memory device.
4. The 3D memory device of claim 3, wherein the epitaxial layer is formed within the first recess.
5. The 3D memory device of claim 1, wherein the dummy holes and the trenches extend to an underlying substrate of the 3D memory device and a second recess of a depth is formed in the substrate of the 3D memory device.
6. The 3D memory device of claim 5, wherein the oxide layer is formed within the second recess.
7. The 3D memory device of claim 1, wherein the core region comprises a stacked structure including a plurality of interlayer insulating layers and a plurality of conductor layers alternately stacked.
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| CN111162080B (en) * | 2020-01-03 | 2021-04-20 | 长江存储科技有限责任公司 | Three-dimensional memory, preparation method of three-dimensional memory and electronic equipment |
| CN111326525B (en) * | 2020-03-13 | 2023-09-26 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
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