CN107833892B - A kind of oxide fill method of top layer selection grid tangent line - Google Patents
A kind of oxide fill method of top layer selection grid tangent line Download PDFInfo
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- CN107833892B CN107833892B CN201711167889.2A CN201711167889A CN107833892B CN 107833892 B CN107833892 B CN 107833892B CN 201711167889 A CN201711167889 A CN 201711167889A CN 107833892 B CN107833892 B CN 107833892B
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention provides a kind of oxide fill methods of top layer selection grid tangent line, by the way that the filling of oxide material in top layer selection grid tangent line channel is used high-density plasma chemical vapor deposition method (HDP-CVD), obtained fill oxide can effectively resist harmful etching that the fluoro-gas in subsequent tungsten grid forming process removes, it is filled to avoid the formation of etching channel by tungsten deposition, and then unnecessary tungsten residual is avoided, improve the properties of product of 3D NAND flash memory structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of production methods of 3D NAND flash memory structure, specifically
It is filled out to avoid occurring in subsequent gate polar curve and tungsten common source forming process a kind of remaining oxide of top layer selection grid tangent line of tungsten
Fill method.
Background technique
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges: physics limit, and the existing developing technique limit and storage electronics are close
Spend limit etc..In this context, the production to solve difficulty and the lower unit storage unit of pursuit that planar flash memory encounters
Cost, a variety of different three-dimensional (3D) flash memories structures are come into being, such as 3D NOR (3D or non-) flash memory and 3D
NAND (3D and non-) flash memory.
Wherein, storage element is used three dimensional pattern stacked in multi-layers using its small size, large capacity as starting point by 3D NAND
It is highly integrated be design concept, produce high unit area storage density, the memory of efficient storage unit performance,
The prevailing technology designed and produced through becoming emerging memory.
Meanwhile in current 3D NAND structure, be by by memory cell be three-dimensionally disposed in substrate come
Improve integration density, wherein channel layer is stood vertically on substrate, grid be divided into lower layer's selection gate, middle layer control grid with
And top layer selection gate (Top Select Gate) three parts, by the way that grid signal is distributed in three groups of gate electrodes to reduce
Crosstalk between signal.Specifically, the device of the upper and lower is as selection transistor --- gate height/thickness is biggish
Vertical MOSFET, gate dielectric layer are conventional single layer high-g value；The device in middle layer be used as memory cell string, gate height/
Thickness is smaller, gate dielectric layer be tunnel layer, accumulation layer, barrier layer stacked structure.
Wherein, it usually is provided with top layer selection grid tangent line (Top Select Gate Cut) in the middle part of finger memory block,
The top layer selection grid (Top Select Gate) for referring to memory block is divided into two parts, and top layer selection grid tangent line is usual
It is formed by oxide material, and is prepared using atom layer deposition process (ALD).Usually use top layer selection grid tangent line
The etching technics of (Top Select Gate Cut) etches away the ON layer 2-3 (2-3Tiers) for stacking top layer, as blocking
(Block) channel, specific preparation process flow include the following steps (referring to Fig. 1 a-1f):
S1: forming multilayer lamination structure, and referring to Fig. 1 a, firstly, providing substrate 10, the substrate surface is formed with multilayer
The interlayer dielectric layer 20 and sacrificial dielectric layer 30 being staggeredly stacked, the sacrificial dielectric layer 30 are formed in adjacent interlayer dielectric layer
Between 20；The interlayer dielectric layer 20 is generally silica, the sacrificial dielectric layer 30, to form ON stacked structure (ON
Stacks)；
S2: forming the step structure of stacked structure, and referring to Fig. 1 b, the prior art is can be used in the technique for forming step structure
In conventional process；
S3: deposition plug oxide skin(coating) is deposition plug oxide skin(coating) first to cover the Step-edge Junction referring to Fig. 1 c
Then structure planarizes the plug oxide skin(coating) using chemical mechanical milling tech (CMP)；
S4: carrying out photoetching to form top layer selection grid tangent line (Top Select Gate Cut), first referring specifically to Fig. 1 d
First, composite hard mask layer 40 is formed in the plug oxide layer surface of planarization, described to answer mask layer include the nothing sequentially formed
The photoresist layer that the SiON layer 42 and SiON layer surface that amorphous carbon layer (A-C) 41, the amorphous carbon layer surface (A-C) are formed are formed
43；Then implement photoetching in the position for needing to form selection grid tangent line (Top Select Gate Cut) to remove corresponding position
The photoresist layer 43 to form photoetching channel 50；
S5: it is performed etching to form top layer selection grid tangent line (Top Select Gate Cut), referring to Fig. 1 e, specifically
For using conventional etching technics, along the photoetching channel 50, etching forms top layer selection grid tangent line (Top Select downwards
Gate Cut) channel 60, and composite hard mask layer is removed to expose plug oxide layer surface；In the process, it is desirable that etching
The position of the interlevel oxide dielectric layer 21 of ON stacked structure is rested on, and not destroy the silicon nitride sacrifice of oxide underlayer
Dielectric layer；
S6: top layer selection grid tangent line (Top Select Gate Cut) channel is filled, referring to Fig. 1 f, specially
Top layer selection grid tangent line oxide material 70 is filled in channel 60 using atom layer deposition process (ALD).
And back-end process (the Back after forming top layer selection grid tangent line (Top Select Gate Cut) technique
End of Line, abbreviation BEOL) in (a-d referring to fig. 2, wherein 70 ' be ALD fill oxide, 80 for tungsten fill), also have
Tungsten grid (W-Gate) forming step (referring to fig. 2 a), tungsten common source (W-Array Common Source, abbreviation W-ACS)
Forming step (referring to fig. 2 c) etc..
However, in above-mentioned steps S6, although carrying out oxide filling using atom layer deposition process (ALD) can obtain
The good filling effect of top layer selection grid tangent line channel (Top Select Gate Cut Trench) is obtained, i.e., without apparent
Gap (Seam) or vacancy (Void), but the oxide that so filling is formed has than the increasing of rest part using plasma
Vapour deposition process (Plasma Enhanced Chemical Vapor Deposition, the abbreviation PECVD) preparation of extensive chemical
By the corrosion rate of the faster hydrofluoric acid of medium of oxides layer (HF) wet etching (Wet Etch) and the corrosion speed of fluoro-gas
Rate, therefore in subsequent annealing treating process step and the forming step of tungsten grid (W-Gate), it is easy to due to hydrofluoric acid
(HF) removing (Fluorin Outgas) of wet etching (Wet Etch) and/or fluoro-gas and cause ALD filling oxidation
Object 70 ' is etched and top area (Top Area) is caused butterfly (Dishing) shape defect occur, in addition formed groove 90 (referring to
Fig. 2 b), and groove 90 is in the forming step of subsequent tungsten common source (W-ACS), deposited tungsten filling 80 fill up (referring to
Fig. 2 c), and will also be difficult to be removed in subsequent tungsten common source (W-ACS) chemical mechanical grinding (CMP) and become tungsten and remain
80 ' (W Residue) (d and Fig. 3 referring to fig. 2), to directly affect the performance of three-dimensional (3D) flash memories.
Therefore, how to avoid top layer selection grid tangent line formed after tungsten grid line and tungsten common source forming process in
There is tungsten residual, it is most important for the preparation and performance of three-dimensional (3D) flash memories, it is always those skilled in the art
Member endeavours the direction of research.
Summary of the invention
The purpose of the present invention is to provide a kind of tungsten grid line avoided after top layer selection grid tangent line is formed and tungsten are total
Occur the oxide fill method of the remaining top layer selection grid tangent line of tungsten in source electrode forming process, is dodged to improve three-dimensional (3D)
Deposit the performance of memory.
To achieve the goals above, the invention proposes a kind of oxide fill methods of top layer selection grid tangent line, including
Following steps:
Multilayer lamination structure is formed in substrate surface, specifically, firstly, providing substrate, the substrate surface is formed with more
The interlayer dielectric layer and sacrificial dielectric layer, the sacrificial dielectric layer that layer is staggeredly stacked are formed between adjacent interlayer dielectric layer；
Then, the smooth surface of top layer interlayer dielectric layer is obtained using chemical mechanical milling tech；
One layer of chemical mechanical grinding cutoff layer is deposited on the smooth surface；
Photoetching is carried out to form top layer selection grid tangent line (Top Select Gate Cut), specifically, first in chemistry
Compound lithography layer is formed on the surface of mechanical lapping cutoff layer；Then selection grid tangent line (Top Select Gate is being needed to form
Cut implement photoetching in position)；
It is performed etching to form top layer selection grid tangent line (Top Select Gate Cut), specifically, being carved using conventional
Etching technique forms the channel of top layer selection grid tangent line (Top Select Gate Cut) in aforementioned photoetching position, and described in removal
Compound lithography layer is to expose the surface of the chemical mechanical grinding cutoff layer；
Top layer selection grid tangent line (Top Select Gate Cut) channel is filled, specifically, using high density
Plasma chemical vapor deposition method (High Density Plasma CVD, HDP-CVD) deposits filling top in the channel
Layer selection grid tangent line oxide material；
Extra top layer selection grid tangent line oxide material is removed, specifically, using chemical mechanical milling tech, it will be right
In the chemical mechanical grinding cutoff layer table when top layer selection grid tangent line (Top Select Gate Cut) channel is filled
The extra top layer selection grid tangent line oxide material removal that face is formed, to expose chemical mechanical grinding cut-off layer surface and shape
At smooth surface；
Remove the chemical mechanical grinding cutoff layer.
Further, the inter-level dielectric layer material is oxide, and the sacrificial dielectric layer material is silicon nitride, thus
It is formed ON stacked structure (ON Stacks).
Further, the chemical mechanical grinding cutoff layer is silicon nitride hardmask layer (SiN HM).
Further, the removal chemical mechanical grinding cutoff layer, using phosphoric acid (H3PO4) solution.
Further, the compound lithography layer includes the amorphous carbon layer (A-C) sequentially formed, SiON layers and photoresist
Layer.
Further, described to etch a certain interlayer dielectric layer for resting on stacked structure；
Especially preferred, the etching rests on 2nd, 3rd or 4th interlayer dielectric layer of the stacked structure since top.
Further, to extra top layer selection grid tangent line (Top Select Gate Cut) channel fill oxide
Removal, using chemical mechanical milling tech (CMP).
Further, the chemical mechanical milling tech (CMP) in the step of substrate surface forms multilayer lamination structure is
The lower chemical mechanical grinding of grinding rate (Buffer CMP).
It further, further include depositing trench plug oxide after removing the chemical mechanical grinding cutoff layer
(CH Plug Oxide), specifically, being deposited on the surface of top layer interlayer dielectric layer and top layer selection grid tangent line oxide material
Plug oxide, and silicon nitride hardmask layer is formed in plug oxide surface.
Compared with prior art, the beneficial effects are mainly reflected as follows:
First, the filling of oxide material uses high-density plasma in top layer selection grid tangent line channel of the invention
It learns vapour deposition (HDP-CVD), obtained fill oxide can effectively be resisted fluorine-containing in subsequent tungsten grid forming process
Harmful etching of gas removal, to avoid the formation of etching channel and be filled by tungsten deposition, and then avoids unnecessary tungsten
Residual；
Second, one layer of silicon nitride hardmask layer (SiN HM) is deposited as chemical mechanical grinding cutoff layer, after enabling to
It is continuous that the oxidation that extra high-density plasma chemical vapor deposition method deposits is effectively removed using chemical mechanical milling tech
Object material.
Third, using phosphoric acid (H3PO4) solution, in removal chemical mechanical grinding cutoff layer meanwhile, it is capable to avoid for oxygen
The removal of compound material；
Through the above steps, so that can't be produced in the back-end process that subsequent tungsten grid is formed and tungsten common source is formed
Raw tungsten residual, to improve the performance of three-dimensional (3D) flash memories.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are general for this field
Logical technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to this hair
Bright limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Fig. 1 a-f is the process flow diagram for forming top layer selection grid tangent line in the prior art；
Fig. 2 a-d is the process flow diagram for being subsequently formed tungsten grid and tungsten common source in the prior art；
Fig. 3 is the remaining stereoscan photograph of tungsten in the prior art；
Fig. 4 a-g is the process flow diagram that top layer selection grid tangent line is formed in the present invention；
Fig. 5 a-c is the process flow diagram that tungsten grid and tungsten common source are subsequently formed in the present invention.
Specific embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although showing this in attached drawing
Disclosed illustrative embodiments, it being understood, however, that may be realized in various forms the disclosure without that should be illustrated here
Embodiment is limited.It is to be able to thoroughly understand the disclosure on the contrary, providing these embodiments, and can incite somebody to action
The scope of the present disclosure is fully disclosed to those skilled in the art.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
Energy and structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that in any practical embodiments
In exploitation, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, another embodiment is changed by one embodiment.Additionally, it should think this development may be it is complicated and
It is time-consuming, but to those skilled in the art it is only routine work.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.According to following explanation and right
Claim, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and makes
With non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Fig. 4 a-4g is please referred to, in the present embodiment, proposes a kind of etching process of top layer selection grid tangent line, is wrapped
Include following steps:
S100: multilayer lamination structure is formed in substrate surface, and obtains the smooth surface of top layer interlayer dielectric layer；
S200: one layer of chemical mechanical grinding cutoff layer is deposited on the smooth surface；
S300: photoetching is carried out to form top layer selection grid tangent line (Top Select Gate Cut)；
S400: it is performed etching to form top layer selection grid tangent line (Top Select Gate Cut)；
S500: top layer selection grid tangent line (Top Select Gate Cut) channel is filled；
S600: extra top layer selection grid tangent line oxide material is removed；
S700: the chemical mechanical grinding cutoff layer is removed；
S800: depositing trench plug oxide.
Specifically, Fig. 4 a is please referred to, and in the step s 100, progress step S110 first, the shape on the surface of substrate 100
At multilayer lamination structure, the interlayer dielectric layer 110 of multi-layer intercrossed stacking specially is formed on 100 surface of substrate and is sacrificed
Dielectric layer 120, the sacrificial dielectric layer 120 are formed between adjacent interlayer dielectric layer 110, wherein the substrate 100 is
Silicon substrate, the interlayer dielectric layer 110 are oxide, and for example, ethyl orthosilicate (TEOS), the sacrificial dielectric layer 120 is
Nitride, for example, silicon nitride (SiN), to form the ON stacked structure (ON Stacks) of multilayer；Then carry out step
S120 obtains the smooth surface 130 of top layer interlayer dielectric layer 110 using chemical mechanical milling tech (CMP), based on just
The characteristic of silester (TEOS), the chemical mechanical milling tech (CMP) in step S120 are lower using grinding rate
Chemical mechanical grinding (Buffer CMP).
Fig. 4 b is please referred to, in step s 200, one layer of chemical mechanical grinding is deposited on the smooth surface and cuts
Only layer 140, in order to give full play to the effect of chemical mechanical grinding cut-off, the chemical mechanical grinding cutoff layer 140 is hard material
The bed of material, preferably silicon nitride hardmask layer (SiN HM).
Please refer to Fig. 4 c, in step S300, for formed top layer selection grid tangent line (Top Select Gate Cut) into
Row photoetching, specifically, first carry out step S310, compound lithography layer 150 is formed on stacked structure surface, specifically include with
Lower step: S311 forms amorphous carbon layer (A-C) 151 on the surface of stacked structure and is used as light-absorption layer；Optionally, it is walked
Rapid S312 forms SiON layers on the surface of amorphous carbon layer (A-C) and is used as anti-reflecting layer 152；Step S313 is carried out, compound
150 surface of lithography layer forms photoresist layer 153；Then step S320 is carried out, selection grid tangent line (Top is being needed to form
Select Gate Cut) position implement photoetching with remove corresponding position photoresist 153 formed photoetching channel 160；
Please refer to Fig. 4 d, in step S400, for formed top layer selection grid tangent line (Top Select Gate Cut) into
Row etching, specifically, etching forms top layer selection grid tangent line downwards along the photoetching channel 160 using conventional etching technics
(Top Select Gate Cut) channel 170, and compound lithography layer 150 is removed to expose chemical mechanical grinding cutoff layer 140
Surface.Wherein the etch-stop stays in a certain interlevel oxide dielectric layer 110 of stacked structure and cannot be nitride sacrifice
Dielectric layer 120, in the present embodiment, the preferably described etching rest on 3rd interlayer dielectric layer of the stacked structure since top
110, the number of plies of the interlevel oxide dielectric layer 110 specifically stopped certainly can be according to actual needs to determine completely, such as
It is also possible to the 2nd, the 4th since top or other layers.
Fig. 4 e is please referred to, in step S500, to top layer selection grid tangent line (Top Select Gate Cut) channel 170
Oxide 180 is carried out to fill, the technique of filling uses high-density plasma chemical vapor deposition method (HDP-CVD), and in order to fill
That divides is filled top layer selection grid tangent line (Top Select Gate Cut) channel 170, and the HDP-CVD's carried out is heavy
Product technique, will necessarily form unwanted layer of oxide material 180 ' on the surface of chemical mechanical grinding cutoff layer 140.
Fig. 4 f is please referred to, in step S600, removes extra top layer selection grid tangent line layer of oxide material 180 ', such as
It is aforementioned, due to inevitably foring the layer of oxide material 180 ' not needed, in this step, using chemistry
Mechanical milling tech (CMP) is removed extra top layer selection grid tangent line layer of oxide material 180 ', until exposingization
It learns 140 surface of mechanical lapping cutoff layer and simultaneously forms smooth surface 190, it is hard due to chemical mechanical grinding cutoff layer 140
Matter characteristic plays the role of cut-off positioning, convenient for the removing of undesired oxide material layer 180 ' and the shape of smooth surface 190
At.
Fig. 4 g is please referred to, in step S700, removes the chemical mechanical grinding cutoff layer 140 to expose top layer interlayer
Dielectric layer 110, since present invention employs silicon nitride hardmask layer (SiN HM) to be used as chemical mechanical grinding cutoff layer 140, and
Phosphoric acid (H3PO4) solution for silicon nitride have excellent Etch selectivity, without excessively removing interlevel oxide dielectric layer,
Therefore phosphoric acid (H is used3PO4) solution wet process removal chemical mechanical grinding cutoff layer 140.
In step S800 (not shown), after removing the chemical mechanical grinding cutoff layer 140, step is carried out
S810, depositing trench plug oxide (CH Plug Oxide), specifically, being cut in top layer interlayer dielectric layer and top layer selection grid
The surface of line oxide material deposits plug oxide；Step S820 is then carried out, forms silicon nitride in plug oxide surface
Hard mask layer.
The HDP-CVD fill oxide material 180 ' that technique of the invention is formed, since it has good hydrofluoric acid wet process
The corrosion resistance of etching and fluoro-gas, therefore be not in fill oxide in subsequent tungsten grid forming step
The etching channel (referring to Fig. 5 a) at 180 ' place of material, thus will not be deposited in subsequent tungsten common source forming step
Tungsten 200, which is filled, goes forward side by side (referring to Fig. 5 b) without forming tungsten residual after the chemical mechanical grinding of subsequent tungsten common source
(referring to Fig. 5 c).
To sum up, the filling of oxide material uses high-density plasma in top layer selection grid tangent line channel of the invention
It learns vapour deposition (HDP-CVD), obtained fill oxide can effectively be resisted fluorine-containing in subsequent tungsten grid forming process
Harmful etching of gas removal, to avoid the formation of etching channel and be filled by tungsten deposition, and then avoids unnecessary tungsten
Residual, to improve the performance of three-dimensional (3D) flash memories.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited to
This, anyone skilled in the art in the technical scope disclosed by the present invention, the variation that can readily occur in or replaces
It changes, should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
It protects subject to range.
Claims (8)
1. a kind of oxide fill method of top layer selection grid tangent line, comprising the following steps:
Multilayer lamination structure is formed in substrate surface, specifically, the substrate surface is formed with multilayer friendship firstly, providing substrate
The interlayer dielectric layer and sacrificial dielectric layer, the sacrificial dielectric layer that mistake stacks are formed between adjacent interlayer dielectric layer；Then,
The smooth surface of top layer interlayer dielectric layer is obtained using chemical mechanical milling tech；The chemical mechanical milling tech is to grind
It grinds the lower chemical mechanical grinding of rate (Buffer CMP)；
One layer of chemical mechanical grinding cutoff layer is deposited on the smooth surface；The chemical mechanical grinding cutoff layer is
Silicon nitride hardmask layer (SiN HM)；
Photoetching is carried out to form top layer selection grid tangent line (Top Select Gate Cut), specifically, grinding first in chemical machinery
It grinds and forms compound lithography layer on the surface of cutoff layer；Then selection grid tangent line (Top Select Gate Cut) is being needed to form
Position implement photoetching；
It is performed etching to form top layer selection grid tangent line (Top Select Gate Cut), specifically, using conventional etching process
The channel of top layer selection grid tangent line (Top Select Gate Cut) is formed in aforementioned photoetching position, and removes the complex light
Layer is carved to expose the surface of the chemical mechanical grinding cutoff layer；
Top layer selection grid tangent line (Top Select Gate Cut) channel is filled, specifically, using high-density plasma
CVD method (High Density Plasma CVD, HDP-CVD) deposits filling top layer selection grid in the channel
Tangent line oxide material；
Extra top layer selection grid tangent line oxide material is removed, specifically, will select top layer using chemical mechanical milling tech
It selects when grid tangent line (Top Select Gate Cut) channel is filled in chemical mechanical grinding cut-off layer surface formation
Extra top layer selection grid tangent line oxide material removal, to expose chemical mechanical grinding cut-off layer surface and be formed smooth
Surface；
Remove the chemical mechanical grinding cutoff layer.
2. according to the method described in claim 1, it is characterized by:
The inter-level dielectric layer material is oxide, and the sacrificial dielectric layer material is silicon nitride, to form ON stacked structure
(ON Stacks)。
3. according to the method described in claim 1, it is characterized by:
The removal chemical mechanical grinding cutoff layer, using phosphoric acid (H3PO4) solution.
4. according to the method described in claim 1, it is characterized by:
The compound lithography layer includes the amorphous carbon layer (A-C) sequentially formed, SiON layers and photoresist layer.
5. according to the method described in claim 1, it is characterized by:
It is described to etch a certain interlayer dielectric layer for resting on stacked structure.
6. according to the method described in claim 5, it is characterized by:
The etching rests on 2nd, 3rd or 4th interlayer dielectric layer of the stacked structure since top.
7. according to the method described in claim 1, it is characterized by:
Removal to extra top layer selection grid tangent line (Top Select Gate Cut) channel fill oxide, using
Chemical mechanical milling tech (CMP).
8. according to the method described in claim 1, it is characterized by:
It further include depositing trench plug oxide (CH Plug Oxide) after removing the chemical mechanical grinding cutoff layer,
Specifically, depositing plug oxide, Yi Ji on the surface of top layer interlayer dielectric layer and top layer selection grid tangent line oxide material
Plug oxide surface forms silicon nitride hardmask layer.
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