CN109037323B - 具有选择性生成的2deg沟道的常关型hemt晶体管及其制造方法 - Google Patents
具有选择性生成的2deg沟道的常关型hemt晶体管及其制造方法 Download PDFInfo
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Abstract
常关型HEMT晶体管包括:异质结构,异质结构包括沟道层和沟道层上的势垒层;异质结构中的2DEG层;与势垒层的第一区域接触的绝缘层;以及穿过绝缘层的整个厚度的栅极电极,栅极电极终止于与势垒层的第二区域接触。势垒层和绝缘层具有晶格常数的失配(“晶格失配”),晶格常数的失配仅在势垒层的第一区域中生成机械应力,引起在位于势垒层的第一区域下方的二维传导沟道的第一部分中的第一电子浓度,第一电子浓度大于位于势垒层的第二区域下方的二维传导沟道的第二部分中的第二电子浓度。
Description
技术领域
本公开涉及常关型高电子迁移率场效应晶体管(“高电子迁移率晶体管”或HEMT)以及用于制造HEMT晶体管的方法。具体地,本公开涉及并入氧化镍的外延层的常关型HEMT晶体管。
背景技术
已知基于在异质结处(即,在具有不同带隙的半导体材料之间的界面处)的高迁移率二维电子气(2DEG)层的形成的高电子迁移率场效应晶体管(“高电子迁移率晶体管”或HEMT)。例如,已知基于氮化铝镓(AlGaN)层和氮化镓(GaN)层之间的异质结的HEMT晶体管。
基于AlGaN/GaN异质结的HEMT晶体管提供了许多优点,这使得它们特别适合并广泛用于各种应用。例如,HEMT晶体管用于高性能功率开关的高击穿阈值;传导沟道中电子的高迁移率使得能够制造高频放大器;此外,2DEG中的高浓度电子提供低导通电阻(RON)。
由于氮化镓衬底的高成本,通常通过在硅衬底上生长AlGaN和GaN层来制造基于AlGaN/GaN异质结的HEMT晶体管。因此,由此制成的HEMT晶体管是平面型的;即,它们具有在平行于衬底的平面上排列的源极电极、栅极电极和漏极电极。
为了便于在高功率应用中使用HEMT晶体管,引入了常关型沟道HEMT晶体管。
用于生产常关型HEMT晶体管的已知解决方案在于使用凹入式栅极端子。在WantaeLim et al.,“Normally Off Operationof Recessed Gate AlGaN/GaN HFETs for HighPower Applications”,Electrochem.Solid State Lett.2011,volume 14,issue 5,H205H207中已知该类型器件的一个示例。然而,该解决方案由于在栅极区域下方的区域中的低电子迁移率而具有缺陷,并且由于栅极区域和漏极区域之间的高电场引起可能的击穿,使得栅极电介质的可靠性差。
另一常关型HEMT晶体管是所谓的“p型GaN”栅极晶体管,其中栅极区域包括在p型GaN区域上延伸的栅极电极。该解决方案具有诸如从栅极区域观察到的高薄层电阻的缺陷,并且需要将施加到栅极电极的电压限制在低于6V的值的缺陷。
因此,已认为有必要提供克服上述问题中的至少一些的常关型HEMT晶体管。
发明内容
因此,根据本公开,常关型HEMT晶体管包括:包括半导体沟道层和沟道层上的半导体势垒层的半导体异质结构;异质结构内的二维传导沟道;与势垒层的第一区域接触的绝缘层;以及延伸穿过绝缘层的整个厚度的栅极电极,栅极电极终止于与势垒层的第二区域接触。势垒层和绝缘层具有晶格常数的失配(“晶格失配”),晶格常数的失配在势垒层的第一区域中生成机械应力,引起位于势垒层的第一区域下方的在二维传导沟道的第一部分中的第一电子浓度,该第一电子浓度大于位于势垒层的第二区域下方的二维传导沟道的第二部分中的第二电子浓度。
一种用于制造HEMT晶体管的方法包括:形成异质结构,包括形成沟道层并在沟道层上形成势垒层,从而在异质结内生成二维传导沟道;形成与势垒层的第一区域接触的绝缘层;以及形成穿过绝缘层的整个厚度的栅极电极,栅极电极与势垒层的第二区域接触。形成势垒层和绝缘层包括:仅在势垒层的第一区域中生成机械应力,所述机械应力是由势垒层和绝缘层之间的晶格常数的失配(“晶格失配”)而导致的,所述机械应力引起在位于势垒层的第一区域下方的二维传导沟道的第一部分中的第一电子浓度,第一电子浓度大于位于势垒层的第二区域下方的二维传导沟道的第二部分中的第二电子浓度。
附图说明
为了更易于理解本公开,现在将参考附图、纯粹通过非限制性示例来描述本发明的优选实施例,其中:
图1以截面图示出了根据本公开的一个实施例的HEMT晶体管;
图2以截面图示出了根据本公开的另一实施例的HEMT晶体管;
图3以截面图示出了根据本公开的又一实施例的HEMT晶体管;
图4示出了根据图1-图3中所示的任何实施例的HEMT晶体管的相应区域中2DEG层中的电子浓度的变化;以及
图5A至图5F示出了制造图1的HEMT晶体管的步骤。
具体实施方式
图1示出了在具有彼此正交的轴线X、Y、Z的三轴线***中的常关型HEMT器件1,HEMT器件1包括:由例如硅或碳化硅(SiC)或蓝宝石(Al2O3)制成的衬底2;本征氮化镓(GaN)的沟道层4,沟道层4在衬底2之上延伸并具有在约1μm至5μm范围内的厚度;本征氮化铝镓(AlGaN)的势垒层6,或者更一般地,基于氮化镓的三元或四元合金(例如,AlxGa1-xN、AlInGaN、InxGa1-xN、AlxIn1-xAl)的化合物的势垒层6,势垒层6在沟道层4上延伸并具有在约5nm至30nm范围内的厚度tB;电介质材料(例如,氧化镍(NiO))的绝缘层7,绝缘层7在势垒层6的上侧6a上延伸;以及延伸到源极区域10和漏极区域12之间的绝缘层7中的栅极区域8。
沟道层4和势垒层6形成异质结构3。衬底2、沟道层4和势垒层6在下文中由术语“半导体本体”5整体表示。异质结构3因此在沟道层4的下侧4a(是与下层衬底2的界面的一部分)以及势垒层6的上侧6a之间延伸。沟道层4和势垒层6通常由这样的材料制成,即,当如图1所示耦合在一起时,它们形成允许形成区域13或二维气体(2DEG)层的异质结。
栅极区域8通过绝缘层7的相应部分与源极区域10和漏极区域12横向(即,沿X)分离。栅极区域8为凹型;即,栅极区域8延伸穿过绝缘层7的深度,以到达势垒层6。换言之,栅极区域8形成在被挖掘而穿过绝缘层7的沟槽9中;可选地,沟槽9延伸穿过势垒层6的一部分并终止于势垒层6内。可选地,根据另一实施例,沟槽9完全延伸穿过势垒层6的一部分。栅极电介质层8a延伸到沟槽9中、面向沟槽9的底部和侧壁。栅极金属化8b完成沟槽9的填充并延伸到栅极电介质层8a上。栅极电介质层8a和栅极金属化层8b形成HEMT器件1的栅极区域。
由导电材料(例如,金属材料)制成的源极区域10和漏极区域12在深度方向上在半导体本体5中穿过整个势垒层6延伸,终止于势垒层6与沟道层4之间的界面处。
根据本公开的一个方面,2DEG区域延伸到沟道层4和绝缘层7下方的势垒层6之间的界面,即,沟道层4和势垒层6之间的界面部分中对应于绝缘层7沿Z的投影。特别地,由于栅极电介质层8a延伸穿过绝缘层7的整个厚度(沿Z轴),以到达并接触势垒层6,所以2DEG区域不存在于栅极区域8下方;特别地,2DEG区域不存在于对应于与势垒层6接触的栅极区域8沿Z的投影的沟道层4和势垒层6之间界面部分中。
根据进一步的实施例,根据需要,半导体本体5可以包括适当掺杂或者本征类型的单层或多个层的GaN或者GaN合金。
例如,图2示出了根据本发明的另一实施例的常关型HEMT晶体管21,其中半导体本体5还包括在衬底2与异质结构3之间的缓冲层22。由相同的附图标记表示并且不再进一步描述图2的HEMT晶体管21与图1的HEMT晶体管1所共用的元件。参考图2,缓冲层22允许在栅极区域中的传导沟道中更好地消耗二维电子气(2DEG),并且特别可用于减小垂直泄漏电流。
图3示出了根据本公开的另一实施例的常关型HEMT晶体管31。由相同的附图标记标识并且不再进一步描述图3的HEMT晶体管31与图2的HEMT晶体管21所共有的元件。参考图3,HEMT晶体管31包括在缓冲层22和异质结构3之间延伸的掩埋层32。
申请人已发现,由于缓冲层22包括杂质,例如碳,该杂质以本身已知方式用于衰减朝向衬底2的垂直泄漏,所以缓冲层22具有高浓度的陷阱态,陷阱态促进空穴发射并且因此导致在缓冲层22内形成负电荷层,这减小了2DEG区域中的电子浓度并且因此增加了HEMT晶体管的导通状态电阻。
为了克服该缺陷,掩埋层32由P型掺杂半导体材料制成,并且源极区域10与掩埋层32直接电接触,使得掩埋层32可以被偏置,以促进空穴从掩埋层32到缓冲层22的传递。因此缓冲层22中的负电荷层被中和。
为了优化该过程,申请人已发现,优选地根据以下关系来选择沟道层4的厚度tu、掩埋层32的掺杂剂物质的表面浓度NA和掩埋层32的厚度tp:
其中q是元电荷;B是缓冲层22的半导体材料的带隙;EA是陷阱态与缓冲层22的价带之间的距离;ε是空穴提供层32的半导体材料的电介质常数。特别地,沟道层4的厚度tu在100nm到500nm的范围内,掩埋层32的掺杂剂物质的表面浓度NA大于6〃1016cm-2,并且掩埋层32的厚度tp大于300nm。
参考上述所有实施例,绝缘层7的存在影响2DEG区域中电子浓度ns(x)的空间分布,其中x是沿X轴线测量的坐标。特别地,绝缘层7的作用涉及由绝缘层7和势垒层6之间的晶格失配引起的应力(换言之,绝缘层7和势垒层6具有相对于彼此不对称的相应晶体结构以及不同尺寸的晶格间隔)。例如,在上述实施例中,绝缘层7(NiO)的材料和势垒层6的材料(AlGaN)之间存在5%的晶格失配。
在进一步的实施例中,可以使用除了NiO以外的材料,例如,CeO2、Gd2O3或La2O3,在P.Fiorenza et al.,“High permittivity cerium oxide thin films on AlGaN/GaNheterostructures”,APPLIED PHYSICS LETTERS 103,112905(2013);Jon F.Ihlefeld etal.,“AlGaN composition dependence of the band offsets for epitaxial Gd2O3/AlxGa1 xN(0≤x≤0.67)heterostructures”,APPLIED PHYSICS LETTERS 105,012102(2014);以及Jon F.Ihlefeld et al.,“Band offsets of La2O3 on(0001)GaN grown byreactive molecular beam epitaxy”,APPLIED PHYSICS LETTERS 102,162903(2013)中讨论了这些材料在GaN衬底上的制备。
可以通过使用在Ambacher,O.et al.,“Two dimensional electron gasesinduced by spontaneous and piezoelectric polarization charges in N and Gaface AlGaN/GaN heterostructures”,Journ.of Appl.Phys.,vol.85,no.6,pp.3222,3233中所公开的模型来解释由绝缘层7和势垒层6之间的晶格失配引起的应力对2DEG区域中电子浓度ns(x)的影响,该文献描述了通过压电极化效应在AlGaN/GaN异质结构的2DEG区域中生成电荷。
具体地,已知在本公开的一个实施例中,2DEG区域的电子浓度ns(x)取决于形成势垒层6的铝的摩尔分数和AlGaN层的厚度。参考图4,申请人已发现,对于形成势垒层6的AlGaN层中铝的10%的摩尔分数和所述层的10nm厚度,2DEG区域在不存在NiO绝缘层7的情况下被耗尽(图4中的曲线S1),而在存在NiO绝缘层7的情况下,其具有ns(x)>6.0〃1012cm2的电子浓度(图4中的曲线S2)。
因此,势垒层6和绝缘层7具有晶格常数的失配(“晶格失配”),晶格常数的失配仅在势垒层6与绝缘层7接触的区域中生成机械应力,从而增加后者的第一部分中的二维传导沟道相对于二维传导沟道的第二部分的电子浓度的ns(x),该第一部分在势垒层6与绝缘层7接触的区域下方(即,对应于沿Z轴、与XY平面正交的投影),该第二部分在势垒层6与绝缘层7不接触的区域下方(即,对应于沿Z轴、与XY平面正交的投影)。
以下参考图5A至图5F描述制造HEMT器件1的步骤。图5A示出了根据本公开的一个实施例的在制造HEMT器件1的步骤期间晶片40的一部分的截面图。由相同的附图标记表示晶片40与上面参考图1描述的和在所述图1中示出的元件相同的元件。具体地,在图5A中,包括:例如由硅(Si)或碳化硅(SiC)或氧化铝(Al2O3)制成的衬底2的晶片40,晶片40具有沿方向Z彼此相对的正面2a和背面2b;氮化镓(GaN)的沟道层4,沟道层4的下侧4a与衬底2的正面2a相邻并重叠;以及在沟道层4上延伸的铝和氮化镓(AlGaN)势垒层6。势垒层6和沟道层4形成异质结构3。
然后,在势垒层6的正面6a上形成厚度为10nm至150nm的电介质材料(例如,氧化镍(NiO))的绝缘层7(图5B)。通过在势垒层6(AlGaN)上外延生长NiO而形成绝缘层7。参考Roccaforte,F.et al.,“Epitaxial NiO gate dielectric on AlGaN/GaNheterostructures”,Appl.Phys.Lett.,vol.100,p.063511,2012,已知在AlGaN上外延生长NiO可以通过称为MOCVD(“金属有机化学气相沉积”)的沉积工艺来进行。具体而言,通过使用Ni(tta)2tmeda作为有机金属前体来生长氧化镍的绝缘层7。在生长过程之前,在氢氟酸和盐酸(Hf/HCl)的混合物中清洗晶片40,以除去势垒层6的正面6a上的自然氧化物。在MOCVD反应器中使用流量为150sccm的氩气作为载气并且流量为200sccm的氧气作为反应气体来执行沉积,从而将有机金属前体的温度保持在160℃,并且在整个沉积时间(10分钟)内将衬底2的温度保持在450℃。
如图5C所示,然后通过例如光刻和蚀刻的步骤,选择性地去除绝缘层7,以选择性地去除晶片40区域中将在随后的步骤中形成HEMT器件1的栅极区域8的层的部分。
如图5C所示,蚀刻步骤可以在下层势垒层6处停止,或者可以继续进入势垒层6的一部分,或者可以完全蚀刻势垒层6。在两种情况下,下层势垒层6的表面部分6'被暴露。例如通过干法蚀刻进行势垒层6的蚀刻。例如,势垒层6所去除的部分沿Z的深度形成1nm至20nm范围内的腔。以这种方式,将沟槽9形成为延伸穿过绝缘层7的整个厚度。
如图5D所示,然后通过例如沉积,形成例如由氮化铝(AlN)、氮化硅(SiN)、氧化铝(Al2O3)和氧化硅(SiO2)中选择的材料构成的栅极电介质层8a。栅极电介质层8a的厚度选自5nm至50nm的范围(例如,30nm)。
如图5E所示,然后执行栅极电介质层8a和绝缘层7的掩模蚀刻的一个或多个进一步的步骤,以去除在晶片40的区域(其中形成HEMT器件1的源极区域10和漏极区域12)中延伸的这些层的选择部分。特别地,沿X轴在沟槽9的相对侧上形成孔34a和34b。
如图5F所示,然后通过沉积导电材料(特别是诸如钛(Ti)或铝(Al)的金属或其合金或化合物)、通过使用已知光刻方法在孔34a、34b中溅射或蒸发来执行形成欧姆接触的步骤,以制造源极区域和漏极区域10、12。
然后在例如约500℃至700℃范围内的温度下、30秒至120秒的时间段内,执行快速热退火(RTA)步骤,以在源极区域10和漏极区域12以及下层区域(包含二维气体2DEG)之间形成欧姆接触。
然后执行在晶片30上沉积导电材料的步骤,以使用已知的光刻方法在栅极电介质层8a上形成栅极金属化物8b,从而填充沟槽9并因此形成栅极区域8。例如,栅极金属化物8b由诸如钽(Ta)、氮化钽(TaN)、氮化钛(TiN)、钯(Pa)、钨(W)、硅化钨(WSi2)、钛/铝(Ti/Al)、或镍/金(Ni/Au)的金属材料形成。以这种方式形成图1所示的HEMT器件1。
根据以上描述,根据本公开的公开内容的优点是显而易见的。特别地,本公开使得可以在不降低栅极区域下方的迁移率的情况下并且在不受栅极区域中存在泄漏电流的性能限制的情况下,提供常关型晶体管条件。
最后,在不脱离本公开的保护范围的情况下,本文描述并示出的解决方案显然可以进行修改和变化。
例如,例如通过从AlSiCu/Ti、Al/Ti、W接点、或其他材料形成触点,晶片表面上的触点(源极、漏极和栅极)的金属化可以使用文献中已知的任何变型来进行。
附加地,沟道层4和势垒层6可以由从IIIV族化合物材料(例如,InGaN/GaN或AlN/GaN)中选择的其他材料制成。
上述各种实施例可以被组合来提供进一步的实施例。根据以上详细描述,可以对这些实施例做出这些改变和其他改变。通常,在所附权利要求中,所使用的术语不应被解释为将权利要求限制为说明书和权利要求书中所公开的具体实施例,而是应被解释为包括所有可能的实施例以及这样的权利要求所授权的等同物的全部范围。因此,权利要求不受本公开的限制。
Claims (19)
1.一种常关型高电子迁移率晶体管HEMT,包括:
半导体异质结构,包括半导体沟道层以及在所述沟道层上的半导体势垒层;
所述异质结构内的二维传导沟道;
与所述势垒层的第一区域接触的外延绝缘层;以及
栅极区域,延伸穿过所述外延绝缘层的整个厚度,并且包括栅极电介质和栅极金属化物,所述栅极区域与所述势垒层的第二区域接触,
其中所述势垒层和所述外延绝缘层具有晶格常数的失配,所述晶格常数的失配在所述势垒层的所述第一区域中生成机械应力,引起在位于所述势垒层的所述第一区域下方的所述二维传导沟道的第一部分中的第一电子浓度,所述第一电子浓度大于位于所述势垒层的所述第二区域下方的、所述二维传导沟道的第二部分中的第二电子浓度。
2.根据权利要求1所述的常关型高电子迁移率晶体管HEMT,其中所述二维传导沟道的所述第二电子浓度基本上为零。
3.根据权利要求1所述的常关型高电子迁移率晶体管HEMT,其中所述异质结构被配置为使得在没有所述外延绝缘层的情况下,不形成二维传导沟道。
4.根据权利要求1所述的常关型高电子迁移率晶体管HEMT,其中所述沟道层和所述势垒层由相应化合物材料制成,所述化合物材料包括III-V族元素,并且其中所述外延绝缘层由使得所述外延绝缘层和所述势垒层之间的所述晶格常数的失配处在1%至20%的范围内的材料制成。
5.根据权利要求1所述的常关型高电子迁移率晶体管HEMT,其中所述外延绝缘层由氧化镍制成,并且其中所述势垒层由氮化铝镓制成,所述势垒层具有处在5%至20%的范围内的铝的摩尔浓度,并且所述势垒层具有5nm至30nm范围内的厚度。
6.根据权利要求1所述的常关型高电子迁移率晶体管HEMT,还包括:
源极电极,在所述栅极区域的第一侧上延伸穿过所述外延绝缘层和所述势垒层的整个厚度,终止于所述势垒层和所述沟道层之间的界面处;以及
漏极电极,在所述栅极区域的第二侧上延伸穿过所述外延绝缘层和所述势垒层的整个厚度,并终止于所述势垒层和所述沟道层之间的所述界面处,所述栅极区域的所述第二侧与所述栅极区域的所述第一侧相对,并且
其中所述栅极电介质与所述势垒层的所述第二区域接触,而不产生将形成所述二维传导沟道的机械应力。
7.根据权利要求1所述的常关型高电子迁移率晶体管HEMT,还包括:
在所述沟道层下方延伸的缓冲层,所述缓冲层包括被配置为生成陷阱态的杂质,所述陷阱态促进从所述缓冲层发射空穴,由此在所述缓冲层内形成负电荷层;
在所述缓冲层和所述沟道层之间延伸的P型掺杂半导体材料的空穴提供层;
源极电极,在所述栅极区域的第一侧上延伸并且与所述空穴提供层直接电接触;以及
漏极电极,在所述栅极区域的第二侧上延伸穿过所述外延绝缘层的整个厚度并穿过所述势垒层,并终止于所述势垒层和所述沟道层之间的界面处,所述栅极区域的所述第二侧与所述栅极区域的所述第一侧相对。
8.一种用于制造常关型HEMT晶体管的方法,包括:
形成异质结构,包括形成沟道层并在所述沟道层上形成势垒层;
在所述异质结构内生成二维传导沟道;
形成与所述势垒层的第一区域接触的外延绝缘层;以及
形成穿过所述外延绝缘层的整个厚度的栅极区域,包括形成与所述势垒层的第二区域接触的栅极电介质和在所述栅极电介质上的栅极金属化物,
其中形成所述势垒层和所述外延绝缘层包括:仅在所述势垒层的所述第一区域中生成机械应力,所述机械应力是由所述势垒层和所述外延绝缘层之间的晶格常数的失配而导致的,所述机械应力引起在位于所述势垒层的所述第一区域下方的所述二维传导沟道的第一部分中的第一电子浓度,所述第一电子浓度大于位于所述势垒层的所述第二区域下方的所述二维传导沟道的第二部分中的第二电子浓度。
9.根据权利要求8所述的方法,其中所述二维传导沟道的所述第二电子浓度基本上为零。
10.根据权利要求8所述的方法,其中形成所述异质结构包括:形成所述异质结构,使得在没有由与所述外延绝缘层接触引起的所述机械应力的情况下,不形成二维传导沟道。
11.根据权利要求8所述的方法,其中形成所述沟道层和所述势垒层包括:选择相应的化合物材料,所述化合物材料包括III-V族元素,并且其中形成所述外延绝缘层包括:选择使得所述外延绝缘层和所述势垒层之间的所述晶格常数的失配处在1%至20%的范围内的材料。
12.根据权利要求8所述的方法,其中形成所述外延绝缘层包括:外延生长氧化镍,并且其中形成所述势垒层包括:形成氮化铝镓层,所述氮化铝镓层具有处在5%至20%的范围内的铝的摩尔浓度,并且具有5nm至30nm范围内的厚度。
13.根据权利要求8所述的方法,所述栅极电介质被形成为与所述势垒层的所述第二区域接触,而不产生将生成在所述二维传导沟道中的电子浓度的机械应力。
14.根据权利要求8所述的方法,还包括:
在所述栅极区域的第一侧上形成穿过所述外延绝缘层和所述势垒层的整个厚度的源极电极,以到达所述势垒层和所述沟道层之间的界面;以及
在所述栅极区域的第二侧上形成穿过所述外延绝缘层和所述势垒层的整个厚度的漏极电极,以到达所述势垒层和所述沟道层之间的所述界面,所述栅极区域的所述第二侧与所述栅极区域的所述第一侧相对。
15.根据权利要求8所述的方法,还包括:
在所述沟道层下方形成包括杂质的缓冲层,所述杂质能够生成促进从所述缓冲层发射空穴的陷阱态,从而在所述缓冲层内形成负电荷层;
在所述缓冲层和所述沟道层之间形成P型掺杂半导体材料的空穴提供层;
在所述栅极区域的第一侧上形成与所述空穴提供层直接电接触的源极电极;以及
在所述栅极区域的第二侧上形成穿过所述外延绝缘层和所述势垒层的所述整个厚度的漏极电极,以到达所述势垒层和所述沟道层之间的界面,所述栅极区域的所述第二侧与所述栅极区域的所述第一侧相对。
16.一种制造常关型HEMT晶体管的方法,包括:
形成异质结构,包括形成沟道层并在所述沟道层上形成势垒层;
直接地在所述势垒层的顶部表面上外延生长晶体绝缘层;以及
通过完全蚀刻穿过所述晶体绝缘层来形成沟槽,所述沟槽直接地在所述势垒层的第一区域上留下所述晶体绝缘层的部分、并且暴露所述势垒层的第二区域;以及
在所述沟槽中形成栅极区域,包括形成与所述势垒层的所述第二区域接触的栅极电介质和在所述栅极电介质上的栅极金属化物;
其中外延生长所述晶体绝缘层以及形成所述沟槽包括:在所述势垒层的所述第一区域中生成机械应力,以及在所述势垒层的所述第二区域与所述沟道层之间的界面处不形成二维传导沟道的情况下,在所述势垒层的所述第一区域和所述沟道层之间的界面处生成所述二维传导沟道,所述机械应力是由所述势垒层和所述晶体绝缘层之间的晶格常数的失配而导致的。
17.根据权利要求16所述的方法,其中外延生长所述晶体绝缘层包括:外延生长氧化镍,并且其中形成所述势垒层包括:形成氮化铝镓层,所述氮化铝镓层具有处在5%至20%的范围内的铝的摩尔浓度。
18.根据权利要求16所述的方法,还包括:
在所述栅极区域的第一侧上形成穿过所述晶体绝缘层和所述势垒层的整个厚度的源极电极,以到达所述势垒层和所述沟道层之间的所述界面;以及
在所述栅极区域的第二侧上形成穿过所述晶体绝缘层和所述势垒层的所述整个厚度的漏极电极,以到达所述势垒层和所述沟道层之间的所述界面,所述栅极区域的所述第二侧与所述栅极区域的所述第一侧相对。
19.根据权利要求16所述的方法,还包括:
在所述沟道层下方形成包括杂质的缓冲层,所述杂质能够生成促进从所述缓冲层发射空穴的陷阱态,从而在所述缓冲层内形成负电荷层;
在所述缓冲层和所述沟道层之间形成P型掺杂半导体材料的空穴提供层;
在所述栅极区域的第一侧上形成与所述空穴提供层直接电接触的源极电极;以及
在所述栅极区域的第二侧上形成穿过所述晶体绝缘层和所述势垒层的整个厚度的漏极电极,以到达所述势垒层和所述沟道层之间的所述界面,所述栅极区域的所述第二侧与所述栅极区域的所述第一侧相对。
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