CN108987460A - A kind of diode and preparation method thereof - Google Patents
A kind of diode and preparation method thereof Download PDFInfo
- Publication number
- CN108987460A CN108987460A CN201810823535.7A CN201810823535A CN108987460A CN 108987460 A CN108987460 A CN 108987460A CN 201810823535 A CN201810823535 A CN 201810823535A CN 108987460 A CN108987460 A CN 108987460A
- Authority
- CN
- China
- Prior art keywords
- layer
- epitaxial layer
- epitaxial
- groove
- conduction type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000002360 preparation method Methods 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 76
- 229920005591 polysilicon Polymers 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 239000002184 metal Substances 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims description 60
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 38
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 19
- 235000012239 silicon dioxide Nutrition 0.000 claims description 19
- 239000000377 silicon dioxide Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 15
- 238000000407 epitaxy Methods 0.000 claims description 14
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 7
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 claims description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims 2
- 241000790917 Dioxys <bee> Species 0.000 claims 1
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims 1
- 239000004408 titanium dioxide Substances 0.000 claims 1
- 238000011084 recovery Methods 0.000 abstract description 23
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 description 27
- 239000000463 material Substances 0.000 description 23
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 238000002513 implantation Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000001657 homoepitaxy Methods 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- 239000012808 vapor phase Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical group [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 2
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical group B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 231100001261 hazardous Toxicity 0.000 description 2
- 238000001534 heteroepitaxy Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000002028 premature Effects 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 239000013049 sediment Substances 0.000 description 2
- 229910052711 selenium Inorganic materials 0.000 description 2
- 239000011669 selenium Substances 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000009514 concussion Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66121—Multilayer diodes, e.g. PNPN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66128—Planar diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention relates to a kind of diode and its manufacturing methods, the diode includes: the substrate of the first conduction type, it is formed in the first buried layer of the second conduction type in substrate and the second buried layer of the first conduction type, it is alternate with each other that the second epitaxial layer for being grown on the first epitaxial layer and the first conduction type of the second conduction type of substrate is laminated, the first groove and second groove of the first buried layer and the second buried layer are extended respectively to through the first epitaxial layer and the second epitaxial layer, filling is formed in the first polysilicon layer of the second conduction type of first groove and second groove and the second polysilicon layer of the first conduction type respectively, the anode metal being connect with the first polysilicon layer, the cathodic metal being connect with the second polysilicon layer.Since first groove is connect with the first buried layer, second groove is connect with the second buried layer, so that the diode, during Reverse recovery, cathode terminal can retain a certain amount of carrier, to be provided with softer reverse recovery characteristic.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of diode and its manufacturing methods.
Background technique
Superjunction diode (Super Junction diode, SJ diode) is a kind of comb being alternatively formed by the area P and the area N
The PN junction diode of shape junction, and must satisfy charge balance conditions between the area P and the area N, have higher than general-purpose diode
Breakdown voltage, be typically used in the power electronics fields such as high frequency, high-power.
It include two stages in one duty cycle of superjunction diode, when being forward recovery period and Reverse recovery respectively
Phase.Forward recovery period be diode since forward conduction to there is higher transient voltage drop, by after a certain period of time
It can be in the process of stable state, which reflects forward recovery characteristic；Reverse recovery period refers to diode from just
The process of reverse blocking state is restored to on state, which is often shorter than forward recovery time, but still needs to this time
Shorten, because long reverse recovery time means increasing for loss.
With the development of power electronics technology, power switch diode needs to have the electrology characteristic become better and better, that is, has
Low forward voltage drop, low conducting resistance and fast and soft reverse recovery characteristic.However use the superjunction of traditional structure and technique
Diode component has begun the demand that people are not achieved, and the reverse characteristic of especially superjunction diode is usually that harder recovery is special
Property, cause to generate harmful current or voltage concussion during Reverse recovery, seriously endangers the rear class component in circuit.
Summary of the invention
The present invention provides a kind of diode, makes it have soft reverse recovery characteristic, and have lower forward voltage drop.
On the one hand, the present invention provides a kind of diode, comprising:
The substrate of first conduction type；
Buried layer, the second buried layer of the first buried layer and the first conduction type including the second conduction type, the buried layer pass through
Injection is formed in the substrate；
Epitaxial layer, the epitaxial layer include the first epitaxial layer of the second conduction type and the second extension of the first conduction type
Layer, when first epitaxial layer or more than one second epitaxial layer, first epitaxial layer and the second epitaxial layer are mutual
It is alternately laminated to be grown on the substrate；
First groove and second groove run through first epitaxial layer and second epitaxial layer, extend respectively to described
First buried layer and second buried layer；
First polysilicon layer of the second conduction type and the second polysilicon layer of the first conduction type, filling is formed in respectively
The first groove and second groove；
The anode metal being connect with first polysilicon layer；
The cathodic metal being connect with second polysilicon layer.
On the other hand, the present invention provides a kind of manufacturing method of diode, comprising:
The substrate of first conduction type is provided；
It injects to form buried layer in the upper surface of the substrate, the buried layer includes the first buried layer and of the second conduction type
Second buried layer of one conduction type；
In the substrate grown epitaxial layer, the epitaxial layer includes the first epitaxial layer and first of the second conduction type
Second epitaxial layer of conduction type, when first epitaxial layer or more than one second epitaxial layer, first extension
Layer and the stacking growth alternate with each other of the second epitaxial layer；
Through first epitaxial layer and second epitaxial layer, first buried layer and second buried layer are extended to,
It is respectively formed first groove and second groove, the first polysilicon layer of the second conduction type is filled in the first groove, in institute
State the second polysilicon layer that second groove fills the first conduction type；
Form the anode metal connecting with first polysilicon layer and the cathode connecting with second polysilicon layer gold
Belong to.
Technical solution of the present invention, by the first epitaxial layer of substrate alternating growth and the second epitaxial layer, and first
Groove is connect with the first buried layer, and second groove is connect with the second buried layer so that the first polysilicon layer and the first epitaxial layer simultaneously to
Second epitaxial layer injects hole, and the second polysilicon layer and the second epitaxial layer inject electronics to the first epitaxial layer simultaneously, therefore the
It is full of a large amount of nonequilibrium carrier in one epitaxial layer and the second epitaxial layer, conductivity modulation effect is generated, so that the diode is led
There is lower forward voltage drop after logical, and make the diode in Reverse recovery period, cathode terminal can retain a certain amount of
Carrier, therefore have softer reverse recovery characteristic.
Detailed description of the invention
The attached drawing for constituting a part of the invention is used to provide further understanding of the present invention, schematic reality of the invention
It applies example and its explanation is used to explain the present invention, do not constitute improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is a kind of structural schematic diagram for diode that some embodiments of the invention provide；
Fig. 2 is a kind of structural schematic diagram for diode that other embodiments of the invention provide；
Fig. 3 is a kind of manufacturing process schematic diagram for diode that some embodiments of the invention provide；
Fig. 4 be some embodiments of the invention provide a kind of diode fabricating method substrate inject to be formed the first buried layer and
Structural schematic diagram after second buried layer；
Fig. 5 be some embodiments of the invention provide a kind of diode fabricating method be formed on the substrate the first epitaxial layer it
Structural schematic diagram afterwards；
Fig. 6 is that a kind of diode fabricating method that some embodiments of the invention provide is formed outside second on the first epitaxial layer
Prolong the structural schematic diagram after layer；
Fig. 7 is that a kind of diode fabricating method that some embodiments of the invention provide is alternatively formed multiple the in substrate
Structural schematic diagram after one epitaxial layer and multiple second epitaxial layers；
Fig. 8 is that a kind of diode fabricating method that some embodiments of the invention provide runs through the first epitaxial layer and the second extension
Layer forms first groove and fills the structural schematic diagram after the first polysilicon layer；
Fig. 9 is that a kind of diode fabricating method that some embodiments of the invention provide runs through the first epitaxial layer and the second extension
Layer forms second groove and fills the structural schematic diagram after the second polysilicon layer.
Description of symbols:
1: substrate；3: the first buried layers；5: the second buried layers；7a: the first epitaxial layer；7b: the second epitaxial layer；8: first groove；
9: the first polysilicon layers；10: second groove；11: the second polysilicon layers；13: anode metal；15: cathodic metal；17: titanium dioxide
Silicon layer；19: suspended metal field plate.
Specific embodiment
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings, it should be understood that preferred reality described herein
Apply example only for the purpose of illustrating and explaining the present invention and is not intended to limit the present invention.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without making creative work belongs to the model that the present invention protects
It encloses.It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can be mutual group
It closes.
It should be appreciated that ought use in this specification and in the appended claims, term " includes " and "comprising" instruction
The presence of described feature, step, but the presence or addition of one or more of the other feature, step is not precluded.
In the description of the present invention, it is to be understood that, the instructions such as term " on ", "lower", "inner", "outside", " running through "
Orientation or positional relationship is to be based on the orientation or positional relationship shown in the drawings, and is merely for convenience of the description present invention and simplification is retouched
It states, rather than indication or suggestion structure must have a particular orientation, be constructed and operated in a specific orientation, therefore cannot understand
For limitation of the present invention.In addition, term " first ", " second " etc. are used for description purposes only, and it should not be understood as instruction or dark
Show relative importance or implicitly indicates the quantity of indicated technical characteristic.The spy of " first ", " second " etc. is defined as a result,
Sign can explicitly or implicitly include one or more of the features.In the description of the present invention, unless otherwise indicated,
The meaning of " plurality " is two or more.
Technical solution of the present invention is related to designing and manufacturing for semiconductor devices, and semiconductor refers to that a kind of electric conductivity can be controlled
System, conductive extensions can be from insulator to the material changed between conductor, and common semiconductor material has silicon, germanium, GaAs etc., and
Silicon is most powerful, one kind for being most widely used in various semiconductor materials.Semiconductor is divided into intrinsic semiconductor, p-type
Semiconductor and N-type semiconductor, free from foreign meter and without lattice defect semiconductor is known as intrinsic semiconductor, in pure silicon crystal
It mixes triad (such as boron, indium, gallium), is allowed to replace the seat of silicon atom in lattice, P-type semiconductor is just formed, pure
Silicon crystal in mix pentad (such as phosphorus, arsenic), be allowed to replace the position of silicon atom in lattice, be formed N-type and partly lead
The conduction type of body, P-type semiconductor and N-type semiconductor is different, and in an embodiment of the present invention, the first conduction type is N-type, the
Two conduction types are p-type, in an embodiment of the present invention, if not otherwise specified, the preferred doping of every kind of conduction type from
Son is all that can be changed to the Doped ions with same conductivity type, is just repeated no more below.
The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
Such as Fig. 1, some embodiments of the invention provide a kind of diode, comprising: the substrate 1 of the first conduction type；Buried layer, packet
The first buried layer 3 of the second conduction type and the second buried layer 5 of the first conduction type are included, the buried layer is formed in described by injection
In substrate 1；Epitaxial layer, the epitaxial layer include outside the first epitaxial layer 7a of the second conduction type and the second of the first conduction type
Prolong a layer 7b, when second epitaxial layer of the first epitaxial layer 7a or described 7b is more than one, the first epitaxial layer 7a and second
Epitaxial layer 7b stacking alternate with each other is grown on the substrate 1；First groove 8 and second groove 10, outside described first
Prolong layer 7a and the second epitaxial layer 7b, extends respectively to first buried layer 3 and second buried layer 5；Second conduction type
The first polysilicon layer 9 and the first conduction type the second polysilicon layer 11, filling is formed in the first groove 8 and the respectively
Two grooves 10；The anode metal 13 being connect with first polysilicon layer 9；The cathode gold being connect with second polysilicon layer 11
Belong to 15.
Technical solution of the present invention, by alternating growth the first epitaxial layer 7a on substrate 1 and the second epitaxial layer 7b, and
First groove 8 is connect with the first buried layer 3, and second groove 10 is connect with the second buried layer 5, so that outside the first polysilicon layer 9 and first
Prolong layer 7a and injects hole to the second epitaxial layer 7b simultaneously, and the second polysilicon layer 11 and the second epitaxial layer 7b are simultaneously to the first extension
Layer 7a injects electronics, therefore a large amount of nonequilibrium carrier is full of in the first epitaxial layer 7a and the second epitaxial layer 7b, generates conductance
Mudulation effect so that having lower forward voltage drop after the diode current flow, and makes the diode in Reverse recovery period,
Its cathode terminal can retain a certain amount of carrier, therefore have softer reverse recovery characteristic.
Specifically, referring to Figure 1, the material of the substrate 1 can be silicon substrate 1, germanium substrate 1 etc., in present embodiment
In, the material of the substrate 1 is preferably silicon substrate 1, and silicon is most common, cheap and stable performance semiconductor material.In this hair
In bright embodiment, first conduction type is N-type, i.e. N- substrate, and the Doped ions of the substrate 1 are phosphorus or arsenic etc., institute
It is low-doped for stating 1 doping concentration of substrate, it is preferred that 1 resistivity of N- substrate is very high, at least more than 280ohm*CM, so that device
Part performance is more preferably.
Specifically, referring to Figure 1, injecting buried layer by photoetching in the upper surface of substrate 1, buried layer includes the second conduction type
The first buried layer 3 and the first conduction type the second buried layer 5, first buried layer 3 is low-doped, i.e. P- buried layer, described second
Buried layer 5 is highly doped, i.e. N+ buried layer, and the shape and area of first buried layer 3 and the second buried layer 5 do not do particular determination, described
First buried layer 3 is 1, and the second buried layer 5 is 2, and the first buried layer 3 is located at the centre of 2 the second buried layers 5, and specific location does not limit
It is fixed, it is preferred that it is boron that the first buried layer 3, which injects element, and Implantation Energy 100KeV, implantation dosage is 3E11~5E11CM-2, second buries
It is antimony that layer 5, which injects element, and Implantation Energy 120KeV, implantation dosage is 4E15~8E15CM-2, so that technique is easier to realize, device
Performance is more preferable.Further, Fig. 2 is referred to, first buried layer 3 and the second buried layer 5 can also all be 1, be formed in described
The area of the both ends of substrate 1, first buried layer 3 and the second buried layer 5 is also without concrete restriction.Further, it first buries
The quantity of layer 3 and the second buried layer 5 can also be respectively 2 and 1, and the second buried layer 5 is located at the centre of 2 the first buried layers 3 at this time,
Its position is not particularly limited.
Specifically, referring to Figure 1, being epitaxially-formed the first epitaxial layer 7a, the first epitaxial layer for the first time on substrate 1
The conduction type of 7a must with the conduction type of substrate 1 on the contrary, i.e. P- epitaxial layer, the first epitaxial layer 7a by technique more
Simple homoepitaxy is formed, i.e., the material of the described first epitaxial layer 7a is identical as the material of the substrate 1, when the material of substrate 1
When material is silicon, the material of the first epitaxial layer 7a is also silicon, and homoepitaxy technology difficulty is low, and technology controlling and process is easier, at it
In his embodiment, the first epitaxial layer 7a can also be formed by hetero-epitaxy, and the material of the first epitaxial layer 7a may be used also
For semiconductor materials such as germanium, selenium.More specifically, the epitaxial growth method can be vapor phase epitaxial growth, rheotaxial growth
Method, vacuum evaporation growth method, high-frequency sputtering growth method, molecular beam epitaxial growth method etc., preferably chemical vapor deposition method (or
Claim vapor phase epitaxial growth), chemical vapor deposition method is a kind of to be reacted and formed sediment on solid matrix surface with vapor reaction raw material
Product is a kind of epitaxial growth method of comparative maturity at the technique of solid thin layer or film, and this method sprays silicon and doped chemical
On the substrate 1, uniformity is reproducible, and step coverage is excellent.Preferably, outside first time epitaxial growth first
Prolong layer 7a to grow using high temperature epitaxy, the first epitaxial layer 7a of first time epitaxial growth with a thickness of 6 ± 0.3 μm, resistivity is
The first epitaxial layer 7a thickness of 50 ± 15ohm*CM, first time epitaxial growth are slightly thick, due to during high temperature epitaxy is grown
Buried layer impurity in substrate 1 can on return about 2 μm or so of diffusion, above return the first epitaxial layer 7a thickness of rear first time epitaxial growth with
Other layers are of uniform thickness, it is ensured that when device of the present invention is reverse-biased, each layer is completely depleted, improves pressure resistance.
Specifically, referring to Figure 1, carrying out second of epitaxial growth on the first epitaxial layer 7a of first time epitaxial growth
The second epitaxial layer 7b, i.e. N- epitaxial layer, the growing method of the same first epitaxial layer 7a of epitaxial growth method principle are formed, but is used
Low-temperature epitaxy growth, temperature is within the scope of 800 DEG C~950 DEG C, so that structure below will not return diffusion upwards, it is preferred that
Second epitaxial layer 7b of second of epitaxial growth with a thickness of 4 ± 0.3 μm, resistivity is 50 ± 15ohm*CM, so that outside first
It is identical as the thickness of the second epitaxial layer 7b after diffusion by returning for buried layer to prolong the thickness of layer 7a, it is ensured that device of the present invention is anti-
When inclined, each layer is completely depleted, improves pressure resistance.
Further, referring to Figure 1, it can also continue to use and the second epitaxial layer 7b on above-mentioned second epitaxial layer 7b
Identical growing method carries out epitaxial growth and is alternatively formed the first epitaxial layer 7a and the second epitaxial layer 7b, and it is raw to be all made of low-temperature epitaxy
Long method is formed, and temperature is within the scope of 800 DEG C~950 DEG C, in the embodiment of the present invention, forms 7 layers of epitaxial layer altogether, technique is easy to
It realizes, and device performance is superior, in other embodiments, the quantity of epitaxial layer may be other quantity, but the number of plies is unsuitable
Excessively, otherwise technique is difficult to realize.In the embodiment of the present invention, the epitaxial layer of last time epitaxial growth is the second conduction type
First epitaxial layer 7a, in other embodiments, the epitaxial layer of last time epitaxial growth can also be the of the first conduction type
Two epitaxial layer 7b, it is preferred that be epitaxially-formed positioned at the first epitaxial layer 7a and last time of first time epitaxial growth outer
The thickness for prolonging the first epitaxial layer 7a and the second epitaxial layer 7b between layer is identical, is 4 ± 0.3 μm, and resistivity is 50 ±
15ohm*CM, more preferably, the epitaxial layer being epitaxially-formed for the last time with a thickness of 2 ± 0.2 μm, intermediate epitaxial layer
It is to be formed fully- depleted area by the interaction thereon with its lower two epitaxial layer, every side exhausts 2 μm, therefore needs 4 μm, and last
Layer epitaxial layer forms depletion region, in order to form fully- depleted area, so thick because can only interact with epitaxial layer below
It is 2 μm that degree, which wants thin half, and each epitaxial layer is completely depleted, improves the pressure-resistant performance of device, in other embodiments, the thickness of epitaxial layer
Degree can be with other numerical value.By multiple epitaxy technique, so that multiple first epitaxial layer 7a and the second epitaxial layer 7b are longitudinal mutual
Intersection stacks, so that the first epitaxial layer 7a and the second epitaxial layer 7b are completely depleted in off state, entire epitaxial layer is risen
To the effect of Withstand voltage layer, it is similar to intrinsic layer, making electric-field intensity distribution is approximately distributed rectangular, so that the breakdown voltage of device
It greatly improves.Therefore diode of the present invention has breakdown voltage more higher than conventional diode, simultaneously turns on resistance and still maintains
In previous level.Further, referring to Figure 1, silicon dioxide growth can also be carried out on the last layer epitaxial layer to be formed
Silicon dioxide layer 17, with a thickness of 0.6 ± 0.06 μm, silicon dioxide layer 17 plays the role of protecting device silicon dioxide layer 17.
Specifically, referring to Figure 1-2, go out by lithographic definition the area of first groove 8 in the silicon dioxide layer 17 of semiconductor
Domain directly can also go out the first ditch by lithographic definition in top layer's epitaxial layer in the embodiment of no silicon dioxide layer 17
Then the region of slot 8 carries out deep etching and forms first groove 8, first groove 8 is outside all first epitaxial layer 7a and second
Prolong a layer 7b and extend to substrate 1, the position of first groove 8 and quantity are corresponding with the position of the first buried layer 3 and quantity, first groove
8 will connect with the first buried layer 3 in substrate 1, it is preferred that the groove depth of first groove 8 is greater than 32 μm, later in first groove 8
P+ polysilicon filling deposit, etching the first polysilicon layer 9 of formation are carried out, P+ polysilicon doping source is diborane (B2H6), and P+ is more
The square resistance of crystal silicon is low-doped, preferably 3~5ohm/.
Specifically, referring to Figure 1-2, go out by lithographic definition the area of second groove 10 in the silicon dioxide layer 17 of semiconductor
Domain directly can also go out the second ditch by lithographic definition in top layer's epitaxial layer in the embodiment of no silicon dioxide layer 17
Then the region of slot 10 carries out deep etching and forms second groove 10, second groove 10 is through all first epitaxial layer 7a and the
Two epitaxial layer 7b extend to substrate 1, and the position of second groove 10 and quantity are corresponding with the position of the second buried layer 5, second groove
10 will connect with the second buried layer 5 in substrate 1, it is preferred that the groove depth of second groove 10 is equally greater than 32 μm, later second
Groove 10 carry out N+ polysilicon filling deposit, etching formed the second polysilicon layer 11, N+ polysilicon doping source be phosphine (PH3) or
Phosphorus oxychloride (POCL3), the square resistance of N+ polysilicon are 4~6ohm/.
P+ polysilicon and P- epitaxial layer inject hole to N- epitaxial layer simultaneously, and N+ polysilicon and N- epitaxial layer are simultaneously to P-
Epitaxial layer injects electronics, is then filled with a large amount of nonequilibrium carriers in P- epitaxial layer and N- epitaxial layer, generates conductance modulation effect
It answers, so that having lower forward voltage drop after diode current flow.Due to the P+ polysilicon and N+ polysilicon energy in structure of the invention
It is enough to generate carriers more more than the common area P+ and the area N+, therefore this structure has positive pressure more lower than traditional diode
Drop.
Specifically, referring to Figure 1, carrying out metal sputtering processes to semiconductor front, then by photoetching, etching, formed
Anode metal 13 and cathodic metal 15, anode metal 13 and the first polysilicon layer 9 are connected to anode, the quantity of anode metal 13
Corresponding with the position of the first polysilicon layer 9 and quantity with position, cathodic metal 15 is connect with the second polysilicon layer 11, as yin
Pole, the quantity of cathodic metal 15 and position are corresponding with the position of the second polysilicon layer 11 and quantity.Preferably, metal thickness
Usually at 4 μm or more, to guarantee enough current capacities.
Diode of the present invention is connected by the first polysilicon layer 9 with the first buried layer 3, and the second polysilicon layer 11 is buried with second
Layer 5 is connected, and the PIN diode that together form one in parallel of substrate 1, since PIN diode is in reverse recovery, yin
A certain amount of carrier can be retained between extreme N+ polysilicon, N+ buried layer and N- substrate, therefore be provided with softer reversed
Recovery characteristics.And use traditional structure and the diode of technique that often there is harder reverse recovery characteristic, electric current and electricity
Pressure will undergo bad oscillation, or even generate destructive voltage spike, these hazardous noises most probably cause in circuit
The premature failure of component, and the present invention can avoid these disadvantages.
Further, anode metal 13 is formed by photoetching, etching after semiconductor front carries out metal sputtering processes
Can also form suspended metal field plate 19 while with cathodic metal 15, suspended metal field plate 19 not with anode metal 13 and cathode
Metal 15 connects, and effect is can internally to elapse transverse electric field, reduces surface field intensity, keeps field distribution more equal
It is even, be conducive to play one's part to the full when each epitaxial layer exhausts, therefore be able to bear higher breakdown reverse voltage, have more stable
Electrology characteristic.
Some embodiments of the invention provide a kind of manufacturing method of diode, for manufacturing above-mentioned diode, refer to figure
3, it is a kind of manufacturing process schematic diagram for diode that some embodiments of the invention provide.
As shown in figure 3, a kind of diode fabricating method that some embodiments of the invention provide may comprise steps of
S101-S109。
S101: the substrate 1 of the first conduction type is provided.
Specifically, referring to Fig. 4, carrier of the substrate 1 as semiconductor devices primarily serves the effect of support, institute
The material for stating substrate 1 can be silicon substrate 1, germanium substrate 1 etc., and in the present embodiment, the material of the substrate 1 is preferably silicon lining
Bottom 1, silicon are most common, cheap and stable performance semiconductor material.In an embodiment of the present invention, first conduction type
For N-type, i.e. N- substrate, the Doped ions of the substrate 1 are phosphorus or arsenic etc., 1 doping concentration of substrate be it is low-doped, preferably
, 1 resistivity of N- substrate is very high, at least more than 280ohm*CM, so that device performance is more preferably.
S103: injecting to form buried layer in 1 upper surface of substrate, and the first buried layer 3 and first including the second conduction type is conductive
Second buried layer 5 of type.
Specifically, referring to Fig. 4, buried layer is injected by photoetching in the upper surface of substrate 1, buried layer includes the second conduction type
The first buried layer 3 and the first conduction type the second buried layer 5, first buried layer 3 is low-doped, i.e. P- buried layer, described second
Buried layer 5 is highly doped, i.e. N+ buried layer, and the shape and area of first buried layer 3 and the second buried layer 5 do not do particular determination, described
First buried layer 3 is 1, and the second buried layer 5 is 2, and the first buried layer 3 is located at the centre of 2 the second buried layers 5, and specific location does not limit
It is fixed, it is preferred that it is boron that the first buried layer 3, which injects element, and Implantation Energy 100KeV, implantation dosage is 3E11~5E11CM-2, second buries
It is antimony that layer 5, which injects element, and Implantation Energy 120KeV, implantation dosage is 4E15~8E15CM-2, so that technique is easier to realize, device
Performance is more preferable.Further, Fig. 2 is referred to, first buried layer 3 and the second buried layer 5 can also all be 1, be formed in described
The area of the both ends of substrate 1, first buried layer 3 and the second buried layer 5 is also without concrete restriction.Further, it first buries
The quantity of layer 3 and the second buried layer 5 can also be respectively 2 and 1, and the second buried layer 5 is located at the centre of 2 the first buried layers 3 at this time,
Its position is not particularly limited.
S105: in the growing epitaxial layers of substrate 1, epitaxial layer includes the first epitaxial layer 7a and first of the second conduction type
Second epitaxial layer 7b of conduction type.
Specifically, referring to Fig. 5, it is epitaxially-formed the first epitaxial layer 7a, the first epitaxial layer for the first time on substrate 1
The conduction type of 7a must with the conduction type of substrate 1 on the contrary, i.e. P- epitaxial layer, the first epitaxial layer 7a by technique more
Simple homoepitaxy is formed, i.e., the material of the described first epitaxial layer 7a is identical as the material of the substrate 1, when the material of substrate 1
When material is silicon, the material of the first epitaxial layer 7a is also silicon, and homoepitaxy technology difficulty is low, and technology controlling and process is easier, at it
In his embodiment, the first epitaxial layer 7a can also be formed by hetero-epitaxy, and the material of the first epitaxial layer 7a may be used also
For semiconductor materials such as germanium, selenium.More specifically, the epitaxial growth method can be vapor phase epitaxial growth, rheotaxial growth
Method, vacuum evaporation growth method, high-frequency sputtering growth method, molecular beam epitaxial growth method etc., preferably chemical vapor deposition method (or
Claim vapor phase epitaxial growth), chemical vapor deposition method is a kind of to be reacted and formed sediment on solid matrix surface with vapor reaction raw material
Product is a kind of epitaxial growth method of comparative maturity at the technique of solid thin layer or film, and this method sprays silicon and doped chemical
On the substrate 1, uniformity is reproducible, and step coverage is excellent.Preferably, outside first time epitaxial growth first
Prolong layer 7a to grow using high temperature epitaxy, the first epitaxial layer 7a of first time epitaxial growth with a thickness of 6 ± 0.3 μm, resistivity is
The first epitaxial layer 7a thickness of 45~65ohm*CM, first time epitaxial growth are slightly thick, due to during high temperature epitaxy is grown
Buried layer impurity in substrate 1 can on return about 2 μm or so of diffusion, above return the first epitaxial layer 7a thickness of rear first time epitaxial growth with
Other layers are of uniform thickness, it is ensured that when device of the present invention is reverse-biased, each layer is completely depleted, improves pressure resistance.
Specifically, referring to Fig. 6, second of epitaxial growth is carried out on the first epitaxial layer 7a of first time epitaxial growth
The second epitaxial layer 7b, i.e. N- epitaxial layer, the growing method of the same first epitaxial layer 7a of epitaxial growth method principle are formed, but is used
Low-temperature epitaxy growth, temperature is within the scope of 800 DEG C~950 DEG C, so that structure below will not return diffusion upwards, it is preferred that
Second epitaxial layer 7b of second of epitaxial growth with a thickness of 4 ± 0.3 μm, resistivity is 50 ± 15ohm*CM, so that outside first
It is identical as the thickness of the second epitaxial layer 7b after diffusion by returning for buried layer to prolong the thickness of layer 7a, it is ensured that device of the present invention is anti-
When inclined, each layer is completely depleted, improves pressure resistance.
Further, Fig. 7 is referred to, can also continue to use and the second epitaxial layer 7b on above-mentioned second epitaxial layer 7b
Identical growing method carries out epitaxial growth and is alternatively formed the first epitaxial layer 7a and the second epitaxial layer 7b, and it is raw to be all made of low-temperature epitaxy
Long method is formed, and temperature is within the scope of 800 DEG C~950 DEG C, in the embodiment of the present invention, forms 7 layers of epitaxial layer altogether, technique is easy to
It realizes, and device performance is superior, in other embodiments, the quantity of epitaxial layer may be other quantity, but the number of plies is unsuitable
Excessively, otherwise technique is difficult to realize.In the embodiment of the present invention, the epitaxial layer of last time epitaxial growth is the second conduction type
First epitaxial layer 7a, in other embodiments, the epitaxial layer of last time epitaxial growth can also be the of the first conduction type
Two epitaxial layer 7b, it is preferred that be epitaxially-formed positioned at the first epitaxial layer 7a and last time of first time epitaxial growth outer
The thickness for prolonging the first epitaxial layer 7a and the second epitaxial layer 7b between layer is identical, is 4 ± 0.3 μm, and resistivity is 50 ±
15ohm*CM, more preferably, the epitaxial layer being epitaxially-formed for the last time with a thickness of 2 ± 0.2 μm, intermediate epitaxial layer
It is to be formed fully- depleted area by the interaction thereon with its lower two epitaxial layer, every side exhausts 2 μm, therefore needs 4 μm, and last
Layer epitaxial layer forms depletion region, in order to form fully- depleted area, so thick because can only interact with epitaxial layer below
It is 2 μm that degree, which wants thin half, and each epitaxial layer is completely depleted, improves the pressure-resistant performance of device, in other embodiments, the thickness of epitaxial layer
Degree can be with other numerical value.By multiple epitaxy technique, so that multiple first epitaxial layer 7a and the second epitaxial layer 7b are longitudinal mutual
Intersection stacks, so that the first epitaxial layer 7a and the second epitaxial layer 7b are completely depleted in off state, entire epitaxial layer is risen
To the effect of Withstand voltage layer, it is similar to intrinsic layer, making electric-field intensity distribution is approximately distributed rectangular, so that the breakdown voltage of device
It greatly improves.Therefore diode of the present invention has breakdown voltage more higher than conventional diode, simultaneously turns on resistance and still maintains
In previous level.Further, Fig. 8 is referred to, silicon dioxide growth can also be carried out on the last layer epitaxial layer and is formed
Silicon dioxide layer 17, with a thickness of 0.6 ± 0.06 μm, silicon dioxide layer 17 plays the role of protecting device silicon dioxide layer 17.
S107: running through the first epitaxial layer 7a and the second epitaxial layer 7b, extends to the first buried layer 3 and the second buried layer 5, respectively shape
At first groove 8 and second groove 10, the first polysilicon layer 9 of the second conduction type is filled in first groove 8, in second groove
Second polysilicon layer 11 of 10 the first conduction types of filling.
Specifically, refer to Fig. 8, go out by lithographic definition the region of first groove 8 in the silicon dioxide layer 17 of semiconductor,
In the embodiment of no silicon dioxide layer 17, first groove 8 directly can also be gone out by lithographic definition in top layer's epitaxial layer
Region, then carry out deep etching formed first groove 8, first groove 8 run through all first epitaxial layer 7a and the second extension
Layer 7b extends to substrate 1, and the position of first groove 8 and quantity are corresponding with the position of the first buried layer 3 and quantity, first groove 8
It to be connect with the first buried layer 3 in substrate 1, then carry out deep etching and form first groove 8, it is preferred that the slot of first groove 8
It is greater than 32 μm deeply, forms the first polysilicon layer 9, P+ polycrystalline in the progress P+ polysilicon filling of first groove 8 deposit, etching later
Silicon doped source is diborane (B2H6), and the square resistance of P+ polysilicon is low-doped, preferably 3~5ohm/.
Specifically, refer to Fig. 9, go out by lithographic definition the area of second groove 10 in the silicon dioxide layer 17 of semiconductor
Domain directly can also go out the second ditch by lithographic definition in top layer's epitaxial layer in the embodiment of no silicon dioxide layer 17
Then the region of slot 10 carries out deep etching and forms second groove 10, second groove 10 is through all first epitaxial layer 7a and the
Two epitaxial layer 7b extend to substrate 1, and the position of second groove 10 and quantity are corresponding with the position of the second buried layer 5, second groove
10 will connect with the second buried layer 5 in substrate 1, then carry out deep etching and form second groove 10, it is preferred that second groove 10
Groove depth be equally greater than 32 μm, later second groove 10 carry out N+ polysilicon filling deposit, etching formed the second polysilicon
Layer 11, N+ polysilicon doping source is phosphine (PH3) or phosphorus oxychloride (POCL3), and the square resistance of N+ polysilicon is 4~6ohm/
□。
P+ polysilicon and P- epitaxial layer inject hole to N- epitaxial layer simultaneously, and N+ polysilicon and N- epitaxial layer are simultaneously to P-
Epitaxial layer injects electronics, is then filled with a large amount of nonequilibrium carriers in P- epitaxial layer and N- epitaxial layer, generates conductance modulation effect
It answers, so that having lower forward voltage drop after diode current flow.Due to the P+ polysilicon and N+ polysilicon energy in structure of the invention
It is enough to generate carriers more more than the common area P+ and the area N+, therefore this structure has positive pressure more lower than traditional diode
Drop.
S109: the anode metal connecting with the first polysilicon layer and the cathodic metal connecting with the second polysilicon layer are formed.
Specifically, referring to Figure 1, carrying out metal sputtering processes to semiconductor front, then by photoetching, etching, formed
Anode metal 13 and cathodic metal 15, anode metal 13 and the first polysilicon layer 9 are connected to anode, the quantity of anode metal 13
Corresponding with the position of the first polysilicon layer 9 and quantity with position, cathodic metal 15 is connect with the second polysilicon layer 11, as yin
Pole, the quantity of cathodic metal 15 and position are corresponding with the position of the second polysilicon layer 11 and quantity.Preferably, metal thickness
Usually at 4 μm or more, to guarantee enough current capacities.
Diode of the present invention is connected by the first polysilicon layer 9 with the first buried layer 3, and the second polysilicon layer 11 is buried with second
Layer 5 is connected, and the PIN diode that together form one in parallel of substrate 1, since PIN diode is in reverse recovery, yin
A certain amount of carrier can be retained between the extreme area N+N-, i.e. N+ polysilicon, N+ buried layer and N- substrate, thus be provided with compared with
Soft reverse recovery characteristic.And use traditional structure and the diode of technique that often there is harder reverse recovery characteristic,
Electric current and voltage will undergo bad oscillation, or even generate destructive voltage spike, these hazardous noises most probably cause
The premature failure of component in circuit, and the present invention can avoid these disadvantages.
Further, anode metal 13 is formed by photoetching, etching after semiconductor front carries out metal sputtering processes
Can also form suspended metal field plate 19 while with cathodic metal 15, suspended metal field plate 19 not with anode metal 13 and cathode
Metal 15 connects, and effect is can internally to elapse transverse electric field, reduces surface field intensity, keeps field distribution more equal
It is even, be conducive to play one's part to the full when each epitaxial layer exhausts, therefore be able to bear higher breakdown reverse voltage, have more stable
Electrology characteristic.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Mind and principle within, any modification, equivalent replacement, combination, improvement for being made etc., should be included in the scope of protection of the invention it
It is interior.
Claims (10)
1. a kind of diode characterized by comprising
The substrate of first conduction type；
Buried layer, the second buried layer of the first buried layer and the first conduction type including the second conduction type, the buried layer pass through injection
It is formed in the substrate；
Epitaxial layer, the epitaxial layer include the first epitaxial layer of the second conduction type and the second epitaxial layer of the first conduction type,
When first epitaxial layer or more than one second epitaxial layer, first epitaxial layer and the second epitaxial layer are alternate with each other
Stacking is grown on the substrate；
First groove and second groove run through first epitaxial layer and second epitaxial layer, extend respectively to described first
Buried layer and second buried layer；
First polysilicon layer of the second conduction type and the second polysilicon layer of the first conduction type, filling is formed in described respectively
First groove and second groove；
The anode metal being connect with first polysilicon layer；
The cathodic metal being connect with second polysilicon layer.
2. diode according to claim 1, which is characterized in that further include:
Silicon dioxide layer is formed on the epitaxial layer, and the first groove and the second groove run through the titanium dioxide
Silicon layer.
3. diode according to claim 2, which is characterized in that further include:
Suspended metal field plate, the anode metal, the cathodic metal and the suspended metal field plate are formed in the titanium dioxide
On silicon layer.
4. diode according to claim 1, which is characterized in that the epitaxy layer thickness of the first time epitaxial growth is 6
± 0.3 μm, the epitaxy layer thickness in addition to the epitaxial layer of first time epitaxial growth is 4 ± 0.3 μm.
5. diode according to claim 1, which is characterized in that the epitaxy layer thickness of the last time epitaxial growth is
2±0.2μm。
6. a kind of preparation method of diode, which is characterized in that the described method includes:
The substrate of first conduction type is provided；
It injects to form buried layer in the upper surface of the substrate, the buried layer includes that the first buried layer of the second conduction type and first are led
Second buried layer of electric type；
In the substrate grown epitaxial layer, the epitaxial layer includes the first epitaxial layer and the first conduction of the second conduction type
Second epitaxial layer of type, when first epitaxial layer or more than one second epitaxial layer, first epitaxial layer and
The stacking growth alternate with each other of second epitaxial layer；
Through first epitaxial layer and second epitaxial layer, first buried layer and second buried layer are extended to, respectively
First groove and second groove are formed, fills the first polysilicon layer of the second conduction type in the first groove, described the
Second polysilicon layer of two the first conduction types of trench fill；
Form the anode metal connecting with first polysilicon layer and the cathodic metal connecting with second polysilicon layer.
7. preparation method according to claim 6, which is characterized in that also wrapped after the substrate grown epitaxial layer
It includes:
Growth forms silicon dioxide layer on the epitaxial layer, and the first groove and the second groove run through the dioxy
SiClx layer.
8. preparation method according to claim 7, which is characterized in that form the anode connecting with first polysilicon layer
Metal and the cathodic metal connecting with second polysilicon layer specifically include:
Metal sputtering processes are carried out on the silicon dioxide layer, then by photoetching, etching, form anode metal, cathode
Metal and suspended metal field plate.
9. preparation method according to claim 6, which is characterized in that the epitaxial layer uses low-temperature epitaxy growth technique shape
At temperature is within the scope of 800 DEG C~950 DEG C.
10. preparation method according to claim 6, which is characterized in that the polysilicon doping source of first conduction type
For phosphine or phosphorus oxychloride, the polysilicon doping source of second conduction type is diborane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810823535.7A CN108987460A (en) | 2018-07-25 | 2018-07-25 | A kind of diode and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810823535.7A CN108987460A (en) | 2018-07-25 | 2018-07-25 | A kind of diode and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108987460A true CN108987460A (en) | 2018-12-11 |
Family
ID=64550497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810823535.7A Withdrawn CN108987460A (en) | 2018-07-25 | 2018-07-25 | A kind of diode and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108987460A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113675277A (en) * | 2021-10-21 | 2021-11-19 | 浙江大学杭州国际科创中心 | Diode and manufacturing method thereof |
| CN114023737A (en) * | 2021-11-05 | 2022-02-08 | 深圳市鑫飞宏电子有限公司 | Electrostatic protection chip based on power management and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4754310A (en) * | 1980-12-10 | 1988-06-28 | U.S. Philips Corp. | High voltage semiconductor device |
| US6049109A (en) * | 1994-09-14 | 2000-04-11 | Kabushiki Kaisha Toshiba | Silicon on Insulator semiconductor device with increased withstand voltage |
| CN107359116A (en) * | 2017-07-12 | 2017-11-17 | 张正宇 | A kind of buried regions extension superjunction diode and preparation method thereof |
-
2018
- 2018-07-25 CN CN201810823535.7A patent/CN108987460A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4754310A (en) * | 1980-12-10 | 1988-06-28 | U.S. Philips Corp. | High voltage semiconductor device |
| US6049109A (en) * | 1994-09-14 | 2000-04-11 | Kabushiki Kaisha Toshiba | Silicon on Insulator semiconductor device with increased withstand voltage |
| CN107359116A (en) * | 2017-07-12 | 2017-11-17 | 张正宇 | A kind of buried regions extension superjunction diode and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113675277A (en) * | 2021-10-21 | 2021-11-19 | 浙江大学杭州国际科创中心 | Diode and manufacturing method thereof |
| CN114023737A (en) * | 2021-11-05 | 2022-02-08 | 深圳市鑫飞宏电子有限公司 | Electrostatic protection chip based on power management and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6919610B2 (en) | Power semiconductor device having RESURF layer | |
| CN102903633B (en) | For the method for the field stop igbt for preparing anode in short circuit | |
| JP4564510B2 (en) | Power semiconductor device | |
| CN105448738B (en) | Semiconductor devices containing the super-junction structures using angled implantation process preparation | |
| CN104051540B (en) | Super-junction device and its manufacturing method | |
| CN106575654B (en) | simple charge balance in semiconductor device | |
| JP2004214511A (en) | Power semiconductor device | |
| CN110459598A (en) | A kind of superjunction MOS type power semiconductor and preparation method thereof | |
| CN108987460A (en) | A kind of diode and preparation method thereof | |
| CN109004022B (en) | A kind of diode and its manufacturing method | |
| JP2007243092A (en) | Semiconductor device and manufacturing method thereof | |
| US20240105783A1 (en) | Method for manufacturing a grid | |
| CN115064446B (en) | Super junction semiconductor device and preparation method thereof | |
| CN116487445A (en) | Silicon carbide power device with P+ gradual change ring surrounded by N-region and preparation method thereof | |
| CN104576730B (en) | Super-junction device and its manufacture method | |
| CN109119341A (en) | A kind of VDMOS device terminal structure and preparation method thereof | |
| CN108336129A (en) | Super junction Schottky diode and manufacturing method thereof | |
| CN114883383A (en) | SIMS-JTE terminal structure of novel floating junction silicon carbide power device and preparation method thereof | |
| CN114883387A (en) | SM-JTE terminal structure of novel floating junction silicon carbide power device and preparation method thereof | |
| CN107768371A (en) | Super node MOSFET structure of integrated schottky knot and preparation method thereof | |
| CN108987486A (en) | A kind of power diode and preparation method thereof | |
| CN108598153A (en) | Soft recovery power semiconductor diode and preparation method thereof | |
| CN110071042A (en) | A kind of Zener diode and preparation method thereof | |
| CN109585533A (en) | A kind of power device terminal structure and preparation method thereof | |
| CN219513112U (en) | Diode device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20181211 |
|
| WW01 | Invention patent application withdrawn after publication |