CN114883383A - SIMS-JTE terminal structure of novel floating junction silicon carbide power device and preparation method thereof - Google Patents
SIMS-JTE terminal structure of novel floating junction silicon carbide power device and preparation method thereof Download PDFInfo
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 28
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 26
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 25
- 230000007423 decrease Effects 0.000 claims abstract description 4
- 238000005468 ion implantation Methods 0.000 claims description 13
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 7
- 230000005684 electric field Effects 0.000 abstract description 13
- 238000009826 distribution Methods 0.000 abstract description 8
- 230000035945 sensitivity Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 49
- 238000010586 diagram Methods 0.000 description 9
- 230000001808 coupling effect Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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Abstract
The invention discloses a SIMS-JTE terminal structure of a novel floating junction silicon carbide power device and a preparation method thereof, wherein the method comprises the following steps: providing an N + substrate; manufacturing at least one layer of epitaxial structure on the surface of one side of the N + substrate; the epitaxial structure includes: a first N-epitaxial layer, a floating junction p region and JTE; growing a second N-epitaxial layer on the surface and the inside of one side of the at least one layer of epitaxial structure far away from the N + substrate, and manufacturing a surface terminal in the second N-epitaxial layer; growing an oxide layer on the surface of one side of the second N-epitaxial layer far away from the substrate; and manufacturing a first electrode on the surface of one side of the second N-epitaxial layer far away from the substrate, and manufacturing a second electrode on the surface of one side of the N + substrate far away from the epitaxial structure, wherein the first electrode is contacted with the oxide layer. As the JTE is in a ladder structure at one side close to the N + substrate, the JTE charge quantity forms gradient decrease in a transverse subarea way on the whole, the maximum peak electric field of the JTE can be effectively reduced, the whole electric field distribution becomes uniform, and the sensitivity of a power device to the JTE dose is further improved.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a SIMS-JTE terminal structure of a novel floating junction silicon carbide power device and a preparation method thereof.
Background
In order to improve the performance of the 4H-SiC power device, a 'super junction' structure represented by a floating junction is applied to the relevant power device. The floating junction structure is formed by adding one or more discontinuous P + structures into an epitaxial layer of a traditional 4H-SiC power device, and is similar to a PN junction structure formed in the epitaxial layer. When the device works in a reverse state, the floating junction structure is added to change the originally triangular or trapezoidal electric field distribution in the epitaxial layer into an upper triangular distribution and a lower triangular distribution by taking the floating junction as a dividing line, so that the reverse breakdown voltage of the device is improved under the condition that the thickness and the concentration of the epitaxial layer are unchanged.
However, because the floating junction structure is added to the conventional device, the influence of various factors such as the epitaxial layer structure, the source region floating junction structure, the terminal region floating junction structure and the terminal structure on the device performance needs to be comprehensively considered when designing the device structure, and the design is complex. Therefore, it is necessary to perform design optimization research on the termination structure of the floating junction device in the related art to ensure the performance of the floating junction structure.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a novel SIMS-JTE terminal structure of a floating junction silicon carbide power device and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
in a first aspect, the present invention provides a method for preparing a SIMS-JTE termination structure of a novel floating junction silicon carbide power device, comprising:
providing an N + substrate;
manufacturing at least one layer of epitaxial structure on one side surface of the N + substrate; the epitaxial structure includes: the first N-epitaxial layer, and a floating junction p region and a JTE which are formed after ion implantation is carried out on the surface of one side of the first N-epitaxial layer, which is far away from the N + substrate; the floating junction p region is positioned in an active region, the JTE is positioned in a termination region, and one side of the JTE, which is close to the N + substrate, is of a stepped structure;
growing a second N-epitaxial layer on the surface and the inside of one side, far away from the N + substrate, of the at least one epitaxial structure, and manufacturing a surface terminal in the second N-epitaxial layer;
growing an oxide layer on the surface of one side, far away from the substrate, of the second N-epitaxial layer;
and manufacturing a first electrode on the surface of one side of the second N-epitaxial layer, which is far away from the substrate, and manufacturing a second electrode on the surface of one side of the N + substrate, which is far away from the epitaxial structure, wherein the first electrode is in contact with the oxide layer.
In one embodiment of the present invention, the epitaxial structure is prepared by the following steps:
growing a first N-epitaxial layer on the surface of one side of the N + substrate by utilizing a Chemical Vapor Deposition (CVD) process;
performing active region Al ion implantation on the surface of one side of the first N-epitaxial layer, which is far away from the substrate, to form a floating junction p region;
and performing Al ion implantation in a terminal region to form JTE after a step-shaped mask layer is formed on the surface of one side of the first N-epitaxial layer, which is far away from the substrate.
In one embodiment of the present invention, the JTEs gradually decrease in thickness along a first direction along a direction perpendicular to a plane of the N + substrate, wherein the first direction is a direction in which the active region points toward the termination region.
In one embodiment of the present invention, the gradient of the step structure on the side of the JTE near the N + substrate is 10 ° to 80 °.
In one embodiment of the present invention, the JTE has a width in the first direction of 5 to 500 μm.
In one embodiment of the present invention, the doping concentration of JTE is 1 × 10 16 ～1×10 18 cm -3 。
In one embodiment of the invention, the doping concentration of the floating junction p region is 1 multiplied by 10 16 ～1×10 20 cm -3 。
In one embodiment of the present invention, the floating junction p-region includes a plurality of floating junctions arranged in a first direction;
in the first direction, the width of the floating knot is 1-5 mu m, and the distance between two adjacent floating knots is 1-5 mu m.
In one embodiment of the invention, the doping concentration of the N + substrate is 1 × 10 18 ～1×10 20 cm -3 And the thickness of the N + substrate is 50-400 mu m along the direction vertical to the plane of the N + substrate.
In a second aspect, the invention provides a SIMS-JTE terminal structure of a novel floating junction silicon carbide power device, which is prepared by the above-mentioned method for preparing the SIMS-JTE terminal structure of the novel floating junction silicon carbide power device.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a SIMS-JTE terminal structure of a novel floating junction silicon carbide power device and a preparation method thereof, wherein one side of JTE close to an N + substrate is of a stepped structure, so that the JTE electric charge quantity forms a gradient descending in a transverse subarea on the whole, the peak position of an electric field is changed into a plurality of JTE in a single area, and the coupling action established between the JTE electric charge quantity and the JTE electric charge quantity can effectively reduce the maximum peak electric field of the JTE and enable the distribution of the whole electric field to be uniform, thereby improving the sensitivity of the power device to the JTE dosage and enabling the power device to have stronger dosage deviation resistance.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic flow chart of a method for fabricating a SIMS-JTE termination structure of a novel floating junction silicon carbide power device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a method for fabricating a SIMS-JTE termination structure of a novel floating junction silicon carbide power device according to an embodiment of the present invention;
FIG. 3 is another schematic diagram of a SIMS-JTE termination structure fabrication method for a novel floating junction silicon carbide power device according to an embodiment of the present invention;
FIG. 4 is another schematic diagram of a SIMS-JTE termination structure fabrication method for a novel floating junction silicon carbide power device according to an embodiment of the present invention;
FIG. 5 is another schematic diagram of a SIMS-JTE termination structure fabrication method for a novel floating junction silicon carbide power device according to an embodiment of the present invention;
FIG. 6 is another schematic diagram of a SIMS-JTE termination structure fabrication method for a novel floating junction silicon carbide power device according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a JTE preparation process provided by an embodiment of the present invention;
FIG. 8 is a schematic diagram of a JTE structure provided by an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Fig. 1 is a schematic flow chart of a method for manufacturing an SIMS-JTE terminal structure of a novel floating junction silicon carbide power device according to an embodiment of the present invention, and fig. 2 is a schematic diagram of a method for manufacturing an SIMS-JTE terminal structure of a novel floating junction silicon carbide power device according to an embodiment of the present invention. Referring to fig. 1 to 6, an embodiment of the present invention provides a method for preparing a SIMS-JTE termination structure of a floating junction silicon carbide power device, including:
s1, providing an N + substrate 1;
s2, manufacturing at least one epitaxial structure 2 on one side surface of the N + substrate 1; the epitaxial structure 2 includes: a first N-epitaxial layer 201, and a floating junction p region 202 and a JTE formed after ion implantation is carried out on the surface of one side of the first N-epitaxial layer 201 far away from the N + substrate 1; the floating junction p region 202 is located in the active region, the JTE is located in the termination region, and one side of the JTE, which is close to the N + substrate 1, is of a stepped structure;
s3, growing a second N-epitaxial layer 3 on the surface and the inside of one side, far away from the N + substrate 1, of the at least one epitaxial structure 2, and manufacturing a surface terminal in the second N-epitaxial layer 3;
s4, growing an oxide layer 4 on the surface of one side of the second N-epitaxial layer 3 away from the substrate;
s5, manufacturing a first electrode 5 on the surface of one side of the second N-epitaxial layer 3 far away from the substrate, and manufacturing a second electrode 6 on the surface of one side of the N + substrate 1 far away from the epitaxial structure 2, wherein the first electrode 5 is in contact with the oxide layer 4.
Specifically, in the method for preparing the SIMS-JTE termination structure of the novel floating junction silicon carbide power device according to the embodiment of the present invention, first, an N + substrate 1 shown in fig. 2 is provided, and an epitaxial structure 2 is formed on a side surface of the N + substrate 1, referring to fig. 3, where the epitaxial structure 2 may include: a first N-epitaxial layer 201, a floating junction p region 202 located in an active region and JTE located in a termination region; the floating junction p region 202 and the JTE are formed by performing ion implantation on the surface of the first N-epitaxial layer 201 on the side away from the N + substrate 1, and a stepped structure is below the JTE. It should be understood that this design makes the JTE charge amount form a gradient decreasing in the lateral direction, the peak electric field is changed from two JTEs to multiple JTEs in a single JTE region, and the coupling effect established between them can effectively reduce the maximum peak electric field of JTE and make the overall electric field distribution uniform, thereby improving the sensitivity of the power device to JTE dose and making it have stronger anti-dose-shift characteristics.
In step S2, the epitaxial structure 2 located above the N + substrate 1 may be a single layer or multiple layers, which is not limited in the present application.
Further, as shown in fig. 4-6, after the epitaxial structure 2 is manufactured, a second N-epitaxial layer 3 is grown on the surface of one side of at least one layer of the epitaxial structure 2 away from the N + substrate 1, a surface termination is manufactured in the second N-epitaxial layer 3, and then an oxide layer 4 is grown on the surface of one side of the second N-epitaxial layer 3 away from the substrate by using a thermal oxidation process, wherein the oxidation temperature is 1100 ℃ to 1400 ℃. Finally, depositing metal layers on the surface of one side, away from the substrate, of the second N-epitaxial layer 3 and the surface of one side, away from the epitaxial structure 2, of the N + substrate 1, and respectively forming a first electrode 5 positioned on the upper surface of the second N-epitaxial layer 3 and a second electrode 6 positioned on the lower surface of the N + substrate 1 through an annealing process; illustratively, the metal deposited in step S5 may be Ti, Ni, etc., and the annealing temperature is 400-1000 ℃.
In this embodiment, the first electrode 5 may be an ohmic contact or a schottky contact, and the second electrode 6 may be an ohmic contact.
FIG. 7 is a schematic diagram of a JTE preparation process provided by an embodiment of the present invention. Referring to fig. 3 and 7, the epitaxial structure 2 is manufactured by the following steps:
growing a first N-epitaxial layer 201 on the surface of one side of the N + substrate 1 by using a Chemical Vapor Deposition (CVD) process;
performing active region Al ion implantation on the surface of one side of the first N-epitaxial layer 201, which is far away from the substrate, to form a floating junction p region 202;
and after a step-shaped mask layer is formed on the surface of one side of the first N-epitaxial layer 201 far away from the substrate by photoetching, carrying out Al ion implantation in a terminal region to form JTE.
Specifically, in the process of manufacturing the epitaxial structure 2, firstly, a first N-epitaxial layer 201 is grown on one side surface of the N + substrate 1 by using a CVD (Chemical Vapor Deposition) process, wherein the growth temperature is 1600 ℃ to 1900 ℃; then, performing active region ion implantation on the surface of the first N-epitaxial layer 201, which is far away from the N + substrate 1, wherein the implanted ions are Al and the implantation energy is 10 keV-800 keV, and forming a floating junction p region 202.
Further, a step-shaped mask layer is formed on the surface of one side of the first N-epitaxial layer 201, which is far away from the N + substrate 1, and ion implantation is performed on the surface of the mask layer once, so that JTE located in the terminal region is formed; optionally, the implanted ions are Al, and the implantation energy is 10keV to 800 keV.
Obviously, by repeating the above steps, an epitaxial structure 2 of an arbitrary layer can be formed on the upper surface of the N + substrate 1; in addition, the manufacturing process of the second N-epitaxial layer 3 on the surface of the side of the epitaxial structure 2 away from the N + substrate 1 is the same as that of the first N-epitaxial layer 201, and therefore, the details are not repeated here.
Optionally, the thickness of the JTE gradually decreases along a first direction along a direction perpendicular to a plane of the N + substrate 1, where the first direction is a direction in which the active region points to the termination region.
Specifically, the JTEs are formed by one ion implantation, so the concentration in the JTEs is kept consistent, the width of the JTEs is the same for each layer of epitaxial structure 2, and the thickness of each JTE is gradually reduced along the direction from the active region to the termination region.
Illustratively, the JTEs have a width in the first direction of 5-500 μm, and the step structure of each JTE may include 3-10 steps, each step having a width of 10-200 μm and a thickness of 0.5-1.5 μm.
As shown in fig. 8, in this embodiment, the gradient θ of the step structure is 10 ° to 80 ° on the side of JTE near the N + substrate 1.
In this embodiment, the floating junction p-region 202 includes a plurality of floating junctions arranged in a first direction;
wherein, in the first direction, the width of the floating knot is 1-5 μm, and the distance between two adjacent floating knots is 1-5 μm.
Specifically, the floating junction p region 202 includes a plurality of floating junctions arranged along a first direction, a pitch between two adjacent floating junctions is 1 to 5 μm, a width of each floating junction in the first direction is 1 to 5 μm, and a thickness of each floating junction in a direction perpendicular to a plane of the N + substrate 1 is 0.5 to 2.0 μm. In the embodiment, the floating junction is introduced to enable the electric field distribution of the active region to be uniform, and further the breakdown voltage of the device is improved.
It should be noted that the shape of each floating junction in the floating junction p region 202 may be rectangular, bar-shaped, or polygonal, which is not limited in this application.
Alternatively, the doping concentration of JTE is 1 × 10 16 ～1×10 18 cm -3 The doping concentration of the floating junction p region 202 is 1 × 10 16 ～1×10 20 cm -3 。
Optionally, the doping concentration of the N + substrate 1 is 1 × 10 18 ～1×10 20 cm -3 In a direction perpendicular to the plane of the N + substrate 1The thickness of the N + substrate 1 is 50 to 400 μm.
As shown in FIG. 6, the embodiment of the present invention further provides a SIMS-JTE terminal structure of a novel floating junction silicon carbide power device, which is prepared by the above preparation method of the SIMS-JTE terminal structure of the novel floating junction silicon carbide power device.
The beneficial effects of the invention are that:
the invention provides a SIMS-JTE terminal structure of a novel floating junction silicon carbide power device and a preparation method thereof, wherein one side of JTE close to an N + substrate is of a stepped structure, so that the JTE electric charge quantity forms a gradient descending in a transverse subarea on the whole, the peak position of an electric field is changed into a plurality of JTE in a single area, and the coupling action established between the JTE electric charge quantity and the JTE electric charge quantity can effectively reduce the maximum peak electric field of the JTE and enable the distribution of the whole electric field to be uniform, thereby improving the sensitivity of the power device to the JTE dosage and enabling the power device to have stronger dosage deviation resistance.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In the description of the specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A preparation method of a novel SIMS-JTE terminal structure of a floating junction silicon carbide power device is characterized by comprising the following steps:
providing an N + substrate;
manufacturing at least one layer of epitaxial structure on one side surface of the N + substrate; the epitaxial structure includes: the first N-epitaxial layer, and a floating junction p region and a JTE which are formed after ion implantation is carried out on the surface of one side of the first N-epitaxial layer, which is far away from the N + substrate; the floating junction p region is positioned in an active region, the JTE is positioned in a termination region, and one side of the JTE, which is close to the N + substrate, is of a stepped structure;
growing a second N-epitaxial layer on the surface and the inside of one side, far away from the N + substrate, of the at least one epitaxial structure, and manufacturing a surface terminal in the second N-epitaxial layer;
growing an oxide layer on the surface of one side, far away from the substrate, of the second N-epitaxial layer;
and manufacturing a first electrode on the surface of one side of the second N-epitaxial layer, which is far away from the substrate, and manufacturing a second electrode on the surface of one side of the N + substrate, which is far away from the epitaxial structure, wherein the first electrode is in contact with the oxide layer.
2. The method of claim 1, wherein the epitaxial structure is formed by:
growing a first N-epitaxial layer on the surface of one side of the N + substrate by utilizing a Chemical Vapor Deposition (CVD) process;
performing active region Al ion implantation on the surface of one side of the first N-epitaxial layer, which is far away from the substrate, to form a floating junction p region;
and performing Al ion implantation in a terminal region to form JTE after a step-shaped mask layer is formed on the surface of one side of the first N-epitaxial layer, which is far away from the substrate.
3. The method of claim 1, wherein the JTE thickness decreases in a first direction along a direction perpendicular to the plane of the N + substrate, wherein the first direction is a direction from the active region to the termination region.
4. The method of claim 3, wherein the gradient of the step structure at the JTE side near the N + substrate is 10 ° to 80 °.
5. The method for preparing the SIMS-JTE terminal structure of the novel floating junction silicon carbide power device according to claim 4, wherein the JTE has a width of 5 to 500 μm in the first direction.
6. The method of claim 5, wherein the JTE has a doping concentration of 1 x 10 16 ～1×10 18 cm -3 。
7. The method of claim 1, wherein the floating junction p-region has a doping concentration of 1 x 10 16 ～1×10 20 cm -3 。
8. The method of claim 7, wherein the floating junction p-region comprises a plurality of floating junctions arranged along a first direction;
in the first direction, the width of the floating knot is 1-5 mu m, and the distance between two adjacent floating knots is 1-5 mu m.
9. The method of claim 1, wherein the N + substrate has a doping concentration of 1 x 10 18 ～1×10 20 cm -3 And the thickness of the N + substrate is 50-400 mu m along the direction vertical to the plane of the N + substrate.
10. A SIMS-JTE termination structure for a new floating junction silicon carbide power device, characterized by the fact that it is made by the method of manufacturing the SIMS-JTE termination structure for the new floating junction silicon carbide power device as claimed in any of the above claims 1-9.
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| CN115579382A (en) * | 2022-12-12 | 2023-01-06 | 深圳市森国科科技股份有限公司 | Terminal structure of semiconductor device and semiconductor device thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115579382A (en) * | 2022-12-12 | 2023-01-06 | 深圳市森国科科技股份有限公司 | Terminal structure of semiconductor device and semiconductor device thereof |
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