CN110459598A - A kind of superjunction MOS type power semiconductor and preparation method thereof - Google Patents
A kind of superjunction MOS type power semiconductor and preparation method thereof Download PDFInfo
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Abstract
A kind of superjunction MOS type power semiconductor and preparation method thereof, belongs to power semiconductor technologies field.The present invention provides a kind of power semiconductor including multilayer the first conductive type semiconductor column area and by hetero-junctions as nonequilibrium carrier potential barrier, it realizes charge balance effect and reduces the high injection efficiency of source electrode side, it solves the problems, such as that breakdown voltage reduction and body diode reverse recovery characteristics is caused to deteriorate by actual process bring charge unbalance, improves the breakdown voltage of device and improve the reverse recovery characteristic of body diode.In addition, manufacture craft is simply controllable the present invention also provides a kind of preparation method of superjunction MOS type power semiconductor, it is strong with prior art compatibility.
Description
Technical field
The invention belongs to power semiconductor technologies fields, and in particular to a kind of superjunction MOS type power semiconductor and its
Preparation method.
Background technique
Fig. 1 shows a kind of traditional super-junction metal oxide semiconductor field effect transistor (Super Junction
Metal Oxide Semiconductor Field Effect Transistor, abbreviation SJ-MOSFET) half structure cell,
More subtype devices of the SJ-MOSFET as insulation gate control, due to the area PXing Zhu and N for having doping type opposite in drift region
The breakdown voltage of device can be improved in the area Xing Zhu, bring charge balance effect, but in actual technical process, etching
The process in the area PXing Zhu can show certain angle, so that the area the PXing Zhu groove etched is trapezoidal, this trapezoidal groove can be made
At the charge unbalance in the area PXing Zhu and the area NXing Zhu both sides, to reduce the breakdown voltage of device.Further, since superjunction
The architectural characteristic of MOSFET and the high injection efficiency of source electrode side, will cause in drift region during reverse-conducting and are stored with
A large amount of nonequilibrium carrier, a large amount of nonequilibrium carrier will increase body diode reverse recovery time, and then increase shutdown
Loss, so that body diode reverse recovery characteristics deteriorate in MOSFET.Therefore a kind of new superjunction MOS type power semiconductor is needed
Device causes breakdown voltage reduction and body diode reverse recovery characteristics to dislike to solve actual process bring charge unbalance
The problem of change.
Summary of the invention
The technical problem to be solved by the present invention is in view of the problems of the existing technology, provide a kind of superjunction MOS type function
Rate semiconductor devices and preparation method thereof.
In order to solve the above technical problems, the present invention provides a kind of superjunction MOS type power semiconductor, comprising: metallization
Drain electrode, the first conductive type semiconductor drain region, the first conductive type semiconductor field stop layer, the second conductive type semiconductor column
Area, first the first column of conductive type semiconductor area, first the second column of conductive type semiconductor area, the first conductive type semiconductor
Three column areas, second conductive type semiconductor layer, the first conductive type semiconductor source region, are put down at the second conductive type semiconductor base area
Face grid structure and source metal；
The metalized drain is located at the lower section in first conductive type semiconductor drain region；First conduction type half
Conductor field stop layer is located at the top in first conductive type semiconductor drain region；
The second conductive type semiconductor column area and the first conductive type semiconductor the first column area are located at described the
On one conductive type semiconductor field stop layer, the first conductive type semiconductor the second column area and first conduction type half
Conductor third column area is sequentially located in first column of the first conductive type semiconductor area；The second conductive type semiconductor column
The side in area and first the first column of conductive type semiconductor area, first conductive type semiconductor the second column area and the first conduction type
The side in semiconductor third column area contacts；
Second conductive type semiconductor base area is located at upper surface and the institute in the second conductive type semiconductor column area
State the side in the first conductive type semiconductor third column area；The second conductive type semiconductor layer and first conduction type
Semiconductor source region is located side by side at the side of the second conductive type semiconductor base area upper surface, and side contacts with each other, and described first
There is the second conductive type semiconductor between conductive type semiconductor source region and the first conductive type semiconductor third column area
Base area；
Planar gate structure be located at the first conductive type semiconductor third column area, the second conductive type semiconductor base area and
In the first part of first conductive type semiconductor source region；Source metal is located at the second conductive type semiconductor layer and described
On the second part of first conductive type semiconductor source region；
The forbidden bandwidth of semiconductor material used in second conductive type semiconductor layer is less than the second conductive type semiconductor base
The forbidden bandwidth of semiconductor material used in area and the first conductive type semiconductor source region；First the first column of conductive type semiconductor area
Doping concentration of the doping concentration less than first the second column of conductive type semiconductor area, first the second column of conductive type semiconductor area
Doping concentration less than the first conductive type semiconductor third column area doping concentration.
In order to solve the above technical problems, the present invention also provides a kind of superjunction MOS type power semiconductors, comprising: metal
Change collector, the first conductive type semiconductor collecting zone, the second conductive type semiconductor collecting zone, the first conductive type semiconductor
Field stop layer, the second conductive type semiconductor column area, first the first column of conductive type semiconductor area, the first conductive type semiconductor
Second column area, the first conductive type semiconductor third column area, the second conductive type semiconductor base area, the second conductive type semiconductor
Layer, the first conductive type semiconductor emitter region, planar gate structure and emitter metal；
First conductive type semiconductor collecting zone and the second conductive type semiconductor collecting zone are arranged side by side and side is mutual
Contact；Metallization collector is located under the first conductive type semiconductor collecting zone and the second conductive type semiconductor collecting zone
Side；First conductive type semiconductor field stop layer is located at the first conductive type semiconductor collecting zone and the second conductive type semiconductor
The top of collecting zone；
The second conductive type semiconductor column area and the first conductive type semiconductor the first column area are located at described the
On one conductive type semiconductor field stop layer, the first conductive type semiconductor the second column area and first conduction type half
Conductor third column area is sequentially located in first column of the first conductive type semiconductor area；The second conductive type semiconductor column
The side in area and first the first column of conductive type semiconductor area, first conductive type semiconductor the second column area and the first conduction type
The side in semiconductor third column area contacts；
Second conductive type semiconductor base area is located at upper surface and the institute in the second conductive type semiconductor column area
State the side in the first conductive type semiconductor third column area；The second conductive type semiconductor layer and first conduction type
Semiconductor emission area is located side by side at the side of the second conductive type semiconductor base area upper surface, and side contacts with each other, and described
There is the second conduction type half between one conductive type semiconductor emitter region and the first conductive type semiconductor third column area
Conductor base area；
Planar gate structure be located at the first conductive type semiconductor third column area, the second conductive type semiconductor base area and
In the first part of first conductive type semiconductor emitter region；Emitter metal be located at the second conductive type semiconductor layer and
On the second part of the first conductive type semiconductor emitter region；
The forbidden bandwidth of semiconductor material used in second conductive type semiconductor layer is less than the second conductive type semiconductor base
The forbidden bandwidth of semiconductor material used in area and the first conductive type semiconductor emitter region；First the first column of conductive type semiconductor
Doping concentration of the doping concentration in area less than first the second column of conductive type semiconductor area, first the second column of conductive type semiconductor
Doping concentration of the doping concentration in area less than the first conductive type semiconductor third column area.
Based on the above technical solution, the present invention can also be improved as follows.
Further, the second conductive type semiconductor column area is by being repeatedly epitaxially formed, and second conductive-type
The doping concentration on type semiconductor column area top is less than the doping concentration of lower part.
Beneficial effect using above-mentioned further scheme is: better charge balance is realized, to improve breakdown voltage.
Further, the second conductive type semiconductor column area refills impurity by multiple etching and is formed, and latter
The impurity doping concentration of secondary filling is less than the preceding impurity doping concentration once filled.
Beneficial effect using above-mentioned further scheme is: better charge balance is realized, to improve breakdown voltage.
Further, the planar gate structure includes gate dielectric layer and the gate electrode that is arranged on gate dielectric layer, gate electrode
For metal gate electrode or polygate electrodes.
Further, first column of the first conductive type semiconductor area, first conductive type semiconductor the second column area and
First conductive type semiconductor third column area is formed by epitaxy technique.
Further, the first conduction type is N-type, and the second conduction type is p-type or the second conduction type is p-type, the
One conduction type is N-type.
Further, semiconductor material used in device is silicon, germanium silicon, GaAs, silicon carbide, gallium nitride, three oxidations
Two galliums or diamond.
In order to solve the above technical problems, the embodiment of the present invention also provides a kind of system of superjunction MOS type power semiconductor
Preparation Method, comprising steps of
First conductive type semiconductor drain region of the first conductive type semiconductor substrate as device is chosen, in the first conduction
The first conductive type semiconductor field stop layer is formed on type semiconductor substrate；
Side above the first conductive type semiconductor field stop layer forms first the first column of conductive type semiconductor area,
First conductive type semiconductor the second column area and the first conductive-type are sequentially formed in first the first column of conductive type semiconductor area
Type semiconductor third column area, the doping concentration in first the first column of conductive type semiconductor area is less than the first conductive type semiconductor
The doping concentration in two column areas, the doping concentration in first the second column of conductive type semiconductor area is less than the first conductive type semiconductor
The doping concentration in three column areas；
The other side above the first conductive type semiconductor field stop layer forms the second conductive type semiconductor column area, institute
State the side and first the first column of conductive type semiconductor area, the first conductive type semiconductor in the second conductive type semiconductor column area
The contact of the side in the second column area and the first conductive type semiconductor third column area；On the top in the second conductive type semiconductor column area
The second conductive type semiconductor base area of middle formation, the side of the second conductive type semiconductor base area and the first conductive type semiconductor
The side in third column area contacts；
The first conductive type semiconductor source region and second is formed in the top side of the second conductive type semiconductor base area to lead
Electric type semiconductor layer；The side of the first conductive type semiconductor source region and the side of the second conductive type semiconductor layer
Face contact, and have the between the first conductive type semiconductor source region and the first conductive type semiconductor third column area
Two conductive type semiconductor base areas；The forbidden bandwidth of semiconductor material used in second conductive type semiconductor layer is less than the second conduction
The forbidden bandwidth of semiconductor material used in type semiconductor base area and the first conductive type semiconductor source region；
In the first conductive type semiconductor third column area, on the second conductive type semiconductor base area and first is conductive
Planar gate structure is formed in the first part of type semiconductor source region；On the second conductive type semiconductor layer and described the
Source metal is formed on the second part of one conductive type semiconductor source region；
Metalized drain is formed in the lower section of the first conductive type semiconductor substrate.
In order to solve the above technical problems, the embodiment of the present invention also provides a kind of system of superjunction MOS type power semiconductor
Preparation Method, comprising steps of
Second conductive type semiconductor collecting zone of the second conductive type semiconductor substrate as device is chosen, described
The top of two conductive type semiconductor substrates forms the first conductive type semiconductor field stop layer；
Side above the first conductive type semiconductor field stop layer forms first the first column of conductive type semiconductor area,
First conductive type semiconductor the second column area and the first conductive-type are sequentially formed in first the first column of conductive type semiconductor area
Type semiconductor third column area, the doping concentration in first the first column of conductive type semiconductor area is less than the first conductive type semiconductor
The doping concentration in two column areas, the doping concentration in first the second column of conductive type semiconductor area is less than the first conductive type semiconductor
The doping concentration in three column areas；
The other side above the first conductive type semiconductor field stop layer forms the second conductive type semiconductor column area, institute
State the side and first the first column of conductive type semiconductor area, the first conductive type semiconductor in the second conductive type semiconductor column area
The contact of the side in the second column area and the first conductive type semiconductor third column area；On the top in the second conductive type semiconductor column area
The second conductive type semiconductor base area of middle formation, the side of the second conductive type semiconductor base area and the first conductive type semiconductor
The side in third column area contacts；
The first conductive type semiconductor emitter region and second is formed in the top side of the second conductive type semiconductor base area
Conductive type semiconductor layer；The side of the first conductive type semiconductor emitter region and the second conductive type semiconductor layer
Side contact, and between the first conductive type semiconductor emitter region and the first conductive type semiconductor third column area
With the second conductive type semiconductor base area；The forbidden bandwidth of semiconductor material used in second conductive type semiconductor layer is less than
The forbidden bandwidth of semiconductor material used in two conductive type semiconductor base areas and the first conductive type semiconductor emitter region；
In the first conductive type semiconductor third column area, on the second conductive type semiconductor base area and first is conductive
Planar gate structure is formed in the first part of type semiconductor emitter region；It is on the second conductive type semiconductor layer and described
Emitter metal is formed on the second part of first conductive type semiconductor emitter region；
The first conductive type semiconductor collecting zone is formed in the side of the second conductive type semiconductor collecting zone；
It is formed and is metallized in the lower section of the second conductive type semiconductor collecting zone and the first conductive type semiconductor collecting zone
Collector.
Include multilayer the first conductive type semiconductor column area and lead to the beneficial effects of the present invention are: the present invention provides one kind
Superjunction MOS type power semiconductor and preparation method thereof of the hetero-junctions as nonequilibrium carrier potential barrier is crossed, charge is realized
Balancing effect and the high injection efficiency for reducing source electrode side, solve and cause to hit by actual process bring charge unbalance
The problem of wearing voltage reduction and the deterioration of body diode reverse recovery characteristics, improves the breakdown voltage of device and improves body
The reverse recovery characteristic of diode.
Detailed description of the invention
Fig. 1 is half cellular structural schematic diagram of traditional super node MOSFET；
Fig. 2 is half cellular structural schematic diagram of the superjunction MOS type power semiconductor of first embodiment of the invention；
Fig. 3 is half cellular structural schematic diagram of the superjunction MOS type power semiconductor of second embodiment of the invention；
Fig. 4 is half cellular structural schematic diagram of the superjunction MOS type power semiconductor of third embodiment of the invention；
Fig. 5 is half cellular structural schematic diagram of the superjunction MOS type power semiconductor of fourth embodiment of the invention；
Fig. 6 is half cellular structural schematic diagram of the superjunction MOS type power semiconductor of fifth embodiment of the invention；
Fig. 7 is half cellular structural schematic diagram of the superjunction MOS type power semiconductor of sixth embodiment of the invention；
Fig. 8 is the energy band diagram after forming hetero-junctions.
In attached drawing, parts list represented by the reference numerals are as follows:
1, gate electrode, 2, gate dielectric layer, 3-1, the first conductive type semiconductor source region, 3-2, the first conductive type semiconductor
Emitter region, 4-1, source metal, 4-2, emitter metal, 5, second conductive type semiconductor layer, the 6, second conduction type are partly led
Body base area, 7-1, second the first column of conductive type semiconductor area, 7-2, second the second column of conductive type semiconductor area, 7-3, second
Conductive type semiconductor third column area, the 8, first conductive type semiconductor field stop layer, the 9, first conductive type semiconductor drain region,
10-1, metalized drain, 10-2, metallization collector, the 11, first conductive type semiconductor column area, 11-1, the first conduction type
The first column of semiconductor area, 11-2, first the second column of conductive type semiconductor area, 11-3, the first conductive type semiconductor third column
Area, the 12, first conductive type semiconductor collecting zone, the 13, second conductive type semiconductor collecting zone.
Specific embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the invention.
As shown in Fig. 2, a kind of superjunction MOS type power semiconductor that first embodiment of the invention provides, comprising: metal
Change drain electrode 10-1, the first conductive type semiconductor drain region 9, the first conductive type semiconductor field stop layer 8, the second conduction type half
Conductor pin area 7, first the first column of conductive type semiconductor area 11-1, first the second column of conductive type semiconductor area 11-2, first
Conductive type semiconductor third column area 11-3, the second conductive type semiconductor base area 6, second conductive type semiconductor layer 5, first
Conductive type semiconductor source region 3-1, planar gate structure and source metal 4-1；
The metalized drain 10-1 is located at the lower section in first conductive type semiconductor drain region 9；Described first is conductive
Type semiconductor field stop layer 8 is located at the top in first conductive type semiconductor drain region 9；
The second conductive type semiconductor column area 7 and the first column of the first conductive type semiconductor area 11-1 are located at institute
It states on the first conductive type semiconductor field stop layer 8, the second column of the first conductive type semiconductor area 11-2 and described first
Conductive type semiconductor third column area 11-3 is sequentially located on the first column of the first conductive type semiconductor area 11-1；Described
It is partly led with first the first column of conductive type semiconductor area 11-1, the first conduction type the side in two conductive type semiconductor column areas 7
The contact of the side of the second column of body area 11-2 and the first conductive type semiconductor third column area 11-3；
Second conductive type semiconductor base area 6 be located at the second conductive type semiconductor column area 7 upper surface and
The side of the first conductive type semiconductor third column area 11-3；The second conductive type semiconductor layer 5 and described first
Conductive type semiconductor source region 3-1 is located side by side at the side of 6 upper surface of the second conductive type semiconductor base area, and side phase mutual connection
Touching, has between the first conductive type semiconductor source region 3-1 and the first conductive type semiconductor third column area 11-3
Second conductive type semiconductor base area 6；
Planar gate structure is located at the first conductive type semiconductor third column area 11-3, the second conductive type semiconductor base
In area 6 and the first part of the first conductive type semiconductor source region 3-1；Source metal 4-1 is located at second conduction type half
On the second part of conductor layer 5 and the first conductive type semiconductor source region 3-1；
The forbidden bandwidth of semiconductor material used in second conductive type semiconductor layer 5 is less than the second conductive type semiconductor base
The forbidden bandwidth of semiconductor material used in area 6 and the first conductive type semiconductor source region 3-1；First conductive type semiconductor first
Doping concentration of the doping concentration of column area 11-1 less than first the second column of conductive type semiconductor area 11-2, the first conduction type half
Doping concentration of the doping concentration of the second column of conductor area 11-2 less than the first conductive type semiconductor third column area 11-3.
In above-described embodiment, the superjunction MOS type power semiconductor is super-junction metal oxide semiconductor field
The depth of transistor, second conductive type semiconductor layer 5 can be identical as the first conductive type semiconductor source region 3-1, can also be with
Difference, but its depth is less than 6 junction depth of the second conductive type semiconductor base area；The doping concentration of second conductive type semiconductor layer 5
Can be identical or different with the doping concentration of the second conductive type semiconductor base area 6, when there are can introduce when doping concentration difference for the two
Nonequilibrium carrier potential barrier, and the adjusting to nonequilibrium carrier barrier height can be realized by adjusting the two doping concentration.The
One conductive type semiconductor column area 11-1, first the second column of conductive type semiconductor area 11-2 and the first conductive type semiconductor
The thickness of three column area 11-3 may be the same or different.First conductive type semiconductor source region 3-1 can be N+ source region.Institute
The gate electrode 1 that planar gate structure includes gate dielectric layer 2 He is arranged on gate dielectric layer 2 is stated, gate dielectric layer 2 can be gate oxidation
Layer.
In the present embodiment, the doping concentration of the second conductive type semiconductor base area 6 is 5 × 1016cm-3~2 × 1017cm-3,
Depth is 0.5~3 μm, and the doping concentration of second conductive type semiconductor layer 5 is 5 × 1016cm-3~2 × 1018cm-3, with a thickness of
0.5~1 μm；The doping concentration of first conductive type semiconductor source region 3 is 5 × 1018cm-3~1 × 1020cm-3, depth be 0.2~
0.5μm；Gate oxide thickness is 20~100nm；Polygate electrodes 1 with a thickness of 0.5~1.5 μm；Second conduction type half
The doping concentration in conductor pin area 7 is 7 × 1013cm-3~2 × 1016cm-3, with a thickness of 10~120 μm；First conductive type semiconductor
The doping concentration of field stop layer 8 is 5 × 1015cm-3~1 × 1017cm-3, with a thickness of 1~5 μm；The leakage of first conductive type semiconductor
The doping concentration in area 9 is 5 × 1017cm-3~1 × 1019cm-3, with a thickness of 0.5~5 μm, the first conductive type semiconductor column area 11-
1 doping concentration is 5 × 1015cm-3~1 × 1016cm-3, with a thickness of 3~40 μm, first the second column of conductive type semiconductor area
The doping concentration of 11-2 is 1 × 1016cm-3~5 × 1016cm-3, with a thickness of 3~40 μm, the first conductive type semiconductor third column
The doping concentration of area 11-3 is 5 × 1016cm-3~2 × 1017cm-3, with a thickness of 3~40 μm.
It is in principle explanation that forbidden band is wide below by the principle that the present invention will be described in detail for N-channel super node MOSFET
It spends a lesser side and is known as low-gap semiconductor (for opposite another party), be similarly known as the biggish side of forbidden bandwidth
(for opposite another party) wide bandgap semiconductor.Concrete principle is as follows:
The first conductive type semiconductor column area 11 is the area NXing Zhu, and the second conductive type semiconductor column area 7 is P
The area Xing Zhu, the first conductive type semiconductor column area 11 are led including first the first column of conductive type semiconductor area 11-1, first
Electric the second column of type semiconductor area 11-2 and the first conductive type semiconductor third column area 11-3, the first conductive type semiconductor
Doping concentration of the doping concentration of one column area 11-1 less than first the second column of conductive type semiconductor area 11-2, the first conduction type
Doping concentration of the doping concentration of the second column of semiconductor area 11-2 less than the first conductive type semiconductor third column area 11-3, so that
The drift region area NeiPXing Zhu and the area NXing Zhu realize charge balance during forward blocking, to improve the breakdown of device
Voltage.
The forbidden bandwidth of semiconductor material used in second conductive type semiconductor layer 5 is less than the second conductive type semiconductor base
The forbidden bandwidth of semiconductor material used in area 6 and the first conductive type semiconductor source region 3-1, makes second conductive type semiconductor layer
5 and second conductive type semiconductor base area 6 and the first conductive type semiconductor source region 3-1 in its contact interface form hetero-junctions；
The second conductive type semiconductor layer 5 is, for example, p-type germanium silicon layer, and the second conductive type semiconductor base area 6 is, for example, P-type silicon
Layer, due to the presence of p-type low-gap semiconductor, forms hetero-junctions with p-type wide bandgap semiconductor, when two kinds of semiconductor materials
When close contact forms hetero-junctions, due to the fermi level of the small semiconductor material of the forbidden bandwidth semiconductor bigger than forbidden bandwidth
The fermi level of material is high, so electronics will flow to the latter from the former, its energy band of the semiconductor for causing forbidden bandwidth small is bent up
Song, its energy band of the big semiconductor of forbidden bandwidth are then bent downwardly, as shown in Figure 8.The discontinuity of energy band makes device reversed
There is a hole barrier under conduction mode, this potential barrier reduces the injection efficiency of source electrode side, reduces non-inside drift region
Equilbrium carrier number, reduces the turn-off time, reduces turn-off power loss, improves the reverse recovery characteristic of body diode.
As shown in figure 3, second embodiment of the invention provides a kind of superjunction MOS type power semiconductor, the present embodiment is
On the basis of first embodiment, by being repeatedly epitaxially formed the second conductive type semiconductor column area 7, multiple extension composition
Second the first column of conductive type semiconductor area 7-1, second the second column of conductive type semiconductor area 7-2 and the second conduction type half
Conductor third column area 7-3 doping concentration is controllable, and concentration is gradual change, and second conductive type semiconductor the first column area 7-1's mixes
Miscellaneous concentration is greater than the doping concentration of second the second column of conductive type semiconductor area 7-2, second the second column of conductive type semiconductor area
The doping concentration of 7-2 is greater than the doping concentration of the second conductive type semiconductor third column area 7-3, so as to realize better electricity
Lotus balance, to improve breakdown voltage.
As shown in figure 4, third embodiment of the invention provides a kind of superjunction MOS type power semiconductor, the present embodiment is
On the basis of first embodiment, impurity is refilled by multiple etching and forms the second conductive type semiconductor column area 7, is repeatedly carved
Erosion refills second the first column of conductive type semiconductor area 7-1, second the second column of the conductive type semiconductor area 7- of impurity composition
2, the doping concentration of the second conductive type semiconductor third column area 7-3 is gradual change, second the first column of conductive type semiconductor area
The doping concentration of 7-1 is greater than the doping concentration of second the second column of conductive type semiconductor area 7-2, the second conductive type semiconductor the
The doping concentration of two column area 7-2 is greater than the doping concentration of the second conductive type semiconductor third column area 7-3, so as to realize more
Good charge balance, to improve breakdown voltage.
As shown in figure 5, fourth embodiment of the invention provides a kind of superjunction MOS type power semiconductor, metallize current collection
Pole 10-2, the first conductive type semiconductor collecting zone 12, the second conductive type semiconductor collecting zone 13, the first conduction type are partly led
Body field stop layer 8, the second conductive type semiconductor column area 7, first the first column of conductive type semiconductor area 11-1, the first conductive-type
The second column of type semiconductor area 11-2, the first conductive type semiconductor third column area 11-3, the second conductive type semiconductor base area 6,
Second conductive type semiconductor layer 5, the first conductive type semiconductor emitter region 3-2, planar gate structure and emitter metal 4-2；
First conductive type semiconductor collecting zone 12 and the second conductive type semiconductor collecting zone 13 are arranged side by side and side
It contacts with each other；Metallization collector 10-2 is located at the first conductive type semiconductor collecting zone 12 and the second conductive type semiconductor collection
The lower section in electric area 13；First conductive type semiconductor field stop layer 8 is located at the first conductive type semiconductor collecting zone 12 and second
The top of conductive type semiconductor collecting zone 13；
The second conductive type semiconductor column area 7 and the first column of the first conductive type semiconductor area 11-1 are located at institute
It states on the first conductive type semiconductor field stop layer 8, the second column of the first conductive type semiconductor area 11-2 and described first
Conductive type semiconductor third column area 11-3 is sequentially located on the first column of the first conductive type semiconductor area 11-1；Described
It is partly led with first the first column of conductive type semiconductor area 11-1, the first conduction type the side in two conductive type semiconductor column areas 7
The contact of the side of the second column of body area 11-2 and the first conductive type semiconductor third column area 11-3；
Second conductive type semiconductor base area 6 be located at the second conductive type semiconductor column area 7 upper surface and
The side of the first conductive type semiconductor third column area 11-3；The second conductive type semiconductor layer 5 and described first
Conductive type semiconductor emitter region 3-2 is located side by side at the side of 6 upper surface of the second conductive type semiconductor base area, and side is mutual
Contact, between the first conductive type semiconductor emitter region 3-2 and the first conductive type semiconductor third column area 11-3
With the second conductive type semiconductor base area 6；
Planar gate structure is located at the first conductive type semiconductor third column area 11-3, the second conductive type semiconductor base
In area 6 and the first part of the first conductive type semiconductor emitter region 3-2；Emitter metal 4-2 is located at second conductive-type
On the second part of type semiconductor layer 5 and the first conductive type semiconductor emitter region 3-2；
The forbidden bandwidth of semiconductor material used in second conductive type semiconductor layer 5 is less than the second conductive type semiconductor base
The forbidden bandwidth of semiconductor material used in area 6 and the first conductive type semiconductor emitter region 3-2；First conductive type semiconductor
Doping concentration of the doping concentration of one column area 11-1 less than first the second column of conductive type semiconductor area 11-2, the first conduction type
Doping concentration of the doping concentration of the second column of semiconductor area 11-2 less than the first conductive type semiconductor third column area 11-3.
In above-described embodiment, the superjunction MOS type power semiconductor is superjunction reverse-conducting insulated gate bipolar crystal
Pipe, the present embodiment are that on the basis of embodiment 1, it is conductive that back introduces the second conductive type semiconductor collecting zone 13 and first
Type semiconductor collecting zone 12 constitutes RC-IGBT structure, is used as bipolar device, has conductance modulation in forward conduction
Effect reduces conduction voltage drop, while also having reverse-conducting ability.The first conductive type semiconductor emitter region 3-2 can
Think N+ emitter region.
As shown in fig. 6, fifth embodiment of the invention provides a kind of superjunction MOS type power semiconductor, the present embodiment is
On the basis of fourth embodiment, by being repeatedly epitaxially formed the second conductive type semiconductor column area 7, multiple extension composition
Second the first column of conductive type semiconductor area 7-1, second the second column of conductive type semiconductor area 7-2 and the second conduction type half
Conductor third column area 7-3 doping concentration is controllable, and concentration is gradual change, and second conductive type semiconductor the first column area 7-1's mixes
Miscellaneous concentration is greater than the doping concentration of second the second column of conductive type semiconductor area 7-2, second the second column of conductive type semiconductor area
The doping concentration of 7-2 is greater than the doping concentration of the second conductive type semiconductor third column area 7-3, so as to realize better electricity
Lotus balance, to improve breakdown voltage.
As shown in fig. 7, sixth embodiment of the invention provides a kind of superjunction MOS type power semiconductor, the present embodiment is
On the basis of fourth embodiment, impurity is refilled by multiple etching and forms the second conductive type semiconductor column area 7, is repeatedly carved
Erosion refills second the first column of conductive type semiconductor area 7-1, second the second column of the conductive type semiconductor area 7- of impurity composition
2, the doping concentration of the second conductive type semiconductor third column area 7-3 is gradual change, second the first column of conductive type semiconductor area
The doping concentration of 7-1 is greater than the doping concentration of second the second column of conductive type semiconductor area 7-2, the second conductive type semiconductor the
The doping concentration of two column area 7-2 is greater than the doping concentration of the second conductive type semiconductor third column area 7-3, so as to realize more
Good charge balance, to improve breakdown voltage.
Optionally, the planar gate structure includes gate dielectric layer 2 and the gate electrode 1 that is arranged on gate dielectric layer 2, gate electrode
1 is metal gate electrode or polygate electrodes.Wherein gate dielectric layer 2 with a thickness of 20~100nm；Gate electrode 1 with a thickness of
0.5~1.5 μm.
Optionally, the first column of the first conductive type semiconductor area 11-1, first the second column of conductive type semiconductor area
11-2 and the first conductive type semiconductor third column area 11-3 are formed by epitaxy technique.
Optionally, the first conduction type is N-type, and the second conduction type is p-type or the second conduction type is p-type, first
Conduction type is N-type.
Optionally, semiconductor material used in device is silicon, germanium silicon, GaAs, silicon carbide, gallium nitride, three oxidations two
Gallium or diamond.
Seventh embodiment of the invention provides a kind of preparation method of superjunction MOS type power semiconductor, comprising steps of
First conductive type semiconductor drain region 9 of the first conductive type semiconductor substrate as device is chosen, is led first
The first conductive type semiconductor field stop layer 8 is formed on electric type semiconductor substrate；
Side above the first conductive type semiconductor field stop layer 8 forms first the first column of conductive type semiconductor area
11-1 sequentially forms first the second column of conductive type semiconductor area 11-2 on first the first column of conductive type semiconductor area 11-1
With the first conductive type semiconductor third column area 11-3, the doping concentration of first the first column of conductive type semiconductor area 11-1 is less than
The doping concentration of first the second column of conductive type semiconductor area 11-2, the doping of first the second column of conductive type semiconductor area 11-2
Doping concentration of the concentration less than the first conductive type semiconductor third column area 11-3；
The other side above the first conductive type semiconductor field stop layer 8 forms the second conductive type semiconductor column area 7,
The side in the second conductive type semiconductor column area 7 and first the first column of conductive type semiconductor area 11-1, the first conductive-type
The contact of the side of the second column of type semiconductor area 11-2 and the first conductive type semiconductor third column area 11-3；In the second conduction type
The second conductive type semiconductor base area 6, the side of the second conductive type semiconductor base area 6 are formed in the top in semiconductor column area 7
It is contacted with the side of the first conductive type semiconductor third column area 11-3；
The first conductive type semiconductor source region 3-1 and the is formed in the top side of the second conductive type semiconductor base area 6
Two conductive type semiconductor layers 5；The side of the first conductive type semiconductor source region 3-1 and second conduction type are partly led
The side of body layer 5 contacts, and the first conductive type semiconductor source region 3-1 and the first conductive type semiconductor third column
There is the second conductive type semiconductor base area 6 between area 11-3；The taboo of semiconductor material used in second conductive type semiconductor layer 5
Bandwidth is less than semiconductor material used in the second conductive type semiconductor base area 6 and the first conductive type semiconductor source region 3-1
Forbidden bandwidth；
On the first conductive type semiconductor third column area 11-3, on the second conductive type semiconductor base area 6 and
Planar gate structure is formed in the first part of one conductive type semiconductor source region 3-1；In the second conductive type semiconductor layer 5
Source metal 4-1 is formed on upper and the first conductive type semiconductor source region 3-1 second part；
Metalized drain 10-1 is formed in the lower section of the first conductive type semiconductor substrate.
In above-described embodiment, the superjunction MOS type power semiconductor is super-junction metal oxide semiconductor field
Transistor, first the first column of conductive type semiconductor area 11-1 are made by epitaxy technique；By etching first conductive-type
The first column of type semiconductor area 11-1, the second column of the first conductive type semiconductor area 11-2 and first conduction type are partly led
The side of body third column area 11-3 forms first groove, and fills impurity to first groove, to partly lead in the first conduction type
The other side of 8 top of body field stop layer forms the second conductive type semiconductor column area 7；By partly being led to second conduction type
The surface ion in scapus area 7 injects the second conductive type semiconductor type impurity, and is made annealing treatment, and the second conduction type is formed
Semi-conductor type base area 6；By miscellaneous to 6 ion implanting the first conductive type semiconductor type of the second conductive type semiconductor type base area
Matter, and made annealing treatment, form the first conductive type semiconductor source region 3-1；It is partly led by etching first conduction type
The second conductive type semiconductor type base area 6 in the left side of body source region 3 forms second groove, and by depositing and returning carving technology, the
Second conductive type semiconductor layer 5 is formed in two grooves；Gate medium is obtained by surface thermal oxidation technology, and deposits polycrystalline, so
Planar gate structure is formed by etching technics afterwards；Metal layer is obtained by evaporation or sputtering technology, then passes through etching technics shape
At source metal 4-1 and metalized drain 10-1, thickness of detector is thinned before forming metalized drain 10-1.
Eighth embodiment of the invention provides a kind of preparation method of superjunction MOS type power semiconductor, comprising steps of
Second conductive type semiconductor collecting zone 13 of the second conductive type semiconductor substrate as device is chosen, described
The top of second conductive type semiconductor substrate forms the first conductive type semiconductor field stop layer 8；
Side above the first conductive type semiconductor field stop layer 8 forms first the first column of conductive type semiconductor area
11-1 sequentially forms first the second column of conductive type semiconductor area 11-2 on first the first column of conductive type semiconductor area 11-1
With the first conductive type semiconductor third column area 11-3, the doping concentration of first the first column of conductive type semiconductor area 11-1 is less than
The doping concentration of first the second column of conductive type semiconductor area 11-2, the doping of first the second column of conductive type semiconductor area 11-2
Doping concentration of the concentration less than the first conductive type semiconductor third column area 11-3；
The other side above the first conductive type semiconductor field stop layer 8 forms the second conductive type semiconductor column area 7,
The side in the second conductive type semiconductor column area 7 and first the first column of conductive type semiconductor area 11-1, the first conductive-type
The contact of the side of the second column of type semiconductor area 11-2 and the first conductive type semiconductor third column area 11-3；In the second conduction type
The second conductive type semiconductor base area 6, the side of the second conductive type semiconductor base area 6 are formed in the top in semiconductor column area 7
It is contacted with the side of the first conductive type semiconductor third column area 11-3；
The second conductive type semiconductor base area 6 top side formed the first conductive type semiconductor emitter region 3-2 and
Second conductive type semiconductor layer 5；The side of the first conductive type semiconductor emitter region 3-2 and second conduction type
The side of semiconductor layer 5 contacts, and the first conductive type semiconductor emitter region 3-2 and first conductive type semiconductor
There is the second conductive type semiconductor base area 6 between third column area 11-3；Semiconductor material used in second conductive type semiconductor layer 5
The forbidden bandwidth of material is partly led less than used in the second conductive type semiconductor base area 6 and the first conductive type semiconductor emitter region 3-2
The forbidden bandwidth of body material；
On the first conductive type semiconductor third column area 11-3, on the second conductive type semiconductor base area 6 and
Planar gate structure is formed in the first part of one conductive type semiconductor emitter region 3-2；In second conductive type semiconductor
Emitter metal 4-2 is formed on layer 5 and on the second part of the first conductive type semiconductor emitter region 3-2；
The first conductive type semiconductor collecting zone 12 is formed in the side of the second conductive type semiconductor collecting zone 13；
Gold is formed in the lower section of the second conductive type semiconductor collecting zone 13 and the first conductive type semiconductor collecting zone 12
Categoryization collector 10-2.
In above-described embodiment, the superjunction MOS type power semiconductor is superjunction reverse-conducting insulated gate bipolar crystal
Pipe, the present embodiment is on the basis of embodiment seven, and back introduces the second conductive type semiconductor collecting zone 13 and leads with first
Electric type semiconductor collecting zone 12, constitutes RC-IGBT structure, wherein by ion implanting in the second conductive type semiconductor
The side of collecting zone 13 forms the first conductive type semiconductor collecting zone 12；By to the second conductive type semiconductor type base area 6
Ion implanting the first conductive type semiconductor type impurity, and made annealing treatment, form the first conductive type semiconductor emitter region
3-2；Metal layer is obtained by evaporation or sputtering technology, emitter metal 4-2 is then formed by etching technics and metallization collects
Thickness of detector is thinned before forming metallization collector 10-2 in electrode 10-2.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include at least one this feature.In the description of the present invention, the meaning of " plurality " is at least two, such as two, three
It is a etc., unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, fisrt feature in the second feature " on " or " down " can be with
It is that the first and second features directly contact or the first and second features pass through intermediary mediate contact.Moreover, fisrt feature exists
Second feature " on ", " top " and " above " but fisrt feature be directly above or diagonally above the second feature, or be merely representative of
First feature horizontal height is higher than second feature.Fisrt feature can be under the second feature " below ", " below " and " below "
One feature is directly under or diagonally below the second feature, or is merely representative of first feature horizontal height less than second feature.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office
It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field
Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples
It closes and combines.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of superjunction MOS type power semiconductor, comprising: metalized drain (10-1), the leakage of the first conductive type semiconductor
Area (9), the first conductive type semiconductor field stop layer (8), the second conductive type semiconductor column area (7), the first conduction type half
The first column of conductor area (11-1), first the second column of conductive type semiconductor area (11-2), the first conductive type semiconductor third column
Area (11-3), the second conductive type semiconductor base area (6), second conductive type semiconductor layer (5), the first conductive type semiconductor
Source region (3-1), planar gate structure and source metal (4-1)；
The metalized drain (10-1) is located at the lower section in first conductive type semiconductor drain region (9)；Described first is conductive
Type semiconductor field stop layer (8) is located at the top in first conductive type semiconductor drain region (9)；
The second conductive type semiconductor column area (7) and first column of the first conductive type semiconductor area (11-1) are located at institute
It states on the first conductive type semiconductor field stop layer (8), second column of the first conductive type semiconductor area (11-2) and described
First conductive type semiconductor third column area (11-3) is sequentially located at first column of the first conductive type semiconductor area (11-1)
On；The side of the second conductive type semiconductor column area (7) and first the first column of conductive type semiconductor area (11-1), first
The contact of the side in the second column of conductive type semiconductor area (11-2) and the first conductive type semiconductor third column area (11-3)；
Second conductive type semiconductor base area (6) be located at the second conductive type semiconductor column area (7) upper surface and
The side in the first conductive type semiconductor third column area (11-3)；The second conductive type semiconductor layer (5) and described
First conductive type semiconductor source region (3-1) is located side by side at the side of second conductive type semiconductor base area (6) upper surface, and side
Face contacts with each other, the first conductive type semiconductor source region (3-1) and the first conductive type semiconductor third column area
There is the second conductive type semiconductor base area (6) between (11-3)；
Planar gate structure is located at the first conductive type semiconductor third column area (11-3), the second conductive type semiconductor base area
(6) and in the first part of the first conductive type semiconductor source region (3-1)；Source metal (4-1) is located at second conductive-type
On the second part of type semiconductor layer (5) and the first conductive type semiconductor source region (3-1)；
It is characterized in that, the forbidden bandwidth of semiconductor material used in second conductive type semiconductor layer (5) is less than the second conductive-type
The forbidden bandwidth of semiconductor material used in type semiconductor base area (6) and the first conductive type semiconductor source region (3-1)；First is conductive
Doping of the doping concentration in the first column of type semiconductor area (11-1) less than first the second column of conductive type semiconductor area (11-2)
Concentration, the doping concentration in first the second column of conductive type semiconductor area (11-2) is less than the first conductive type semiconductor third column area
The doping concentration of (11-3).
2. a kind of superjunction MOS type power semiconductor, comprising: metallization collector (10-2), the first conductive type semiconductor
Collecting zone (12), the second conductive type semiconductor collecting zone (13), the first conductive type semiconductor field stop layer (8), second are led
Electric type semiconductor column area (7), first the first column of conductive type semiconductor area (11-1), first the second column of conductive type semiconductor
Area (11-2), the first conductive type semiconductor third column area (11-3), the second conductive type semiconductor base area (6), the second conduction
Type semiconductor layer (5), the first conductive type semiconductor emitter region (3-2), planar gate structure and emitter metal (4-2)；
First conductive type semiconductor collecting zone (12) and the second conductive type semiconductor collecting zone (13) are arranged side by side and side
It contacts with each other；Metallization collector (10-2) is located at the first conductive type semiconductor collecting zone (12) and the second conduction type is partly led
The lower section of body collecting zone (13)；First conductive type semiconductor field stop layer (8) is located at the first conductive type semiconductor collecting zone
(12) and the top of the second conductive type semiconductor collecting zone (13)；
The second conductive type semiconductor column area (7) and first column of the first conductive type semiconductor area (11-1) are located at institute
It states on the first conductive type semiconductor field stop layer (8), second column of the first conductive type semiconductor area (11-2) and described
First conductive type semiconductor third column area (11-3) is sequentially located at first column of the first conductive type semiconductor area (11-1)
On；The side of the second conductive type semiconductor column area (7) and first the first column of conductive type semiconductor area (11-1), first
The contact of the side in the second column of conductive type semiconductor area (11-2) and the first conductive type semiconductor third column area (11-3)；
Second conductive type semiconductor base area (6) be located at the second conductive type semiconductor column area (7) upper surface and
The side in the first conductive type semiconductor third column area (11-3)；The second conductive type semiconductor layer (5) and described
First conductive type semiconductor emitter region (3-2) is located side by side at the side of second conductive type semiconductor base area (6) upper surface, and
Side contacts with each other, the first conductive type semiconductor emitter region (3-2) and the first conductive type semiconductor third column
There is the second conductive type semiconductor base area (6) between area (11-3)；
Planar gate structure is located at the first conductive type semiconductor third column area (11-3), the second conductive type semiconductor base area
(6) and in the first part of the first conductive type semiconductor emitter region (3-2)；Emitter metal (4-2) is located at described second and leads
On the second part of electric type semiconductor layer (5) and the first conductive type semiconductor emitter region (3-2)；
It is characterized in that, the forbidden bandwidth of semiconductor material used in second conductive type semiconductor layer (5) is less than the second conductive-type
The forbidden bandwidth of semiconductor material used in type semiconductor base area (6) and the first conductive type semiconductor emitter region (3-2)；First leads
The doping concentration in electric the first column of type semiconductor area (11-1) is mixed less than first conductive type semiconductor the second column area (11-2's)
Miscellaneous concentration, the doping concentration in first the second column of conductive type semiconductor area (11-2) is less than the first conductive type semiconductor third column
The doping concentration in area (11-3).
3. according to claim 1 or a kind of superjunction MOS type power semiconductor as claimed in claim 2, it is characterised in that: institute
The second conductive type semiconductor column area (7) is stated by being repeatedly epitaxially formed, and on the second conductive type semiconductor column area (7)
The doping concentration in portion is less than the doping concentration of lower part.
4. according to claim 1 or a kind of superjunction MOS type power semiconductor as claimed in claim 2, it is characterised in that: institute
The impurity doping stated the second conductive type semiconductor column area (7) impurity is refilled by multiple etching and formed, and once fill afterwards
Concentration is less than the preceding impurity doping concentration once filled.
5. according to claim 1 or a kind of superjunction MOS type power semiconductor as claimed in claim 2, it is characterised in that: institute
The gate electrode (1) that planar gate structure includes gate dielectric layer (2) and is arranged on gate dielectric layer (2) is stated, gate electrode (1) is metal gate
Electrode or polygate electrodes.
6. according to claim 1 or a kind of superjunction MOS type power semiconductor as claimed in claim 2, it is characterised in that: institute
It is conductive to state first the first column of conductive type semiconductor area (11-1), first the second column of conductive type semiconductor area (11-2) and first
Type semiconductor third column area (11-3) is formed by epitaxy technique.
7. according to claim 1 or a kind of superjunction MOS type power semiconductor as claimed in claim 2, it is characterised in that:
One conduction type is N-type, and the second conduction type is p-type or the second conduction type is p-type, and the first conduction type is N-type.
8. according to claim 1 or a kind of superjunction MOS type power semiconductor as claimed in claim 2, it is characterised in that: device
Semiconductor material used in part is silicon, germanium silicon, GaAs, silicon carbide, gallium nitride, gallic oxide or diamond.
9. a kind of preparation method of superjunction MOS type power semiconductor, which is characterized in that comprising steps of
First conductive type semiconductor drain region (9) of the first conductive type semiconductor substrate as device is chosen, in the first conduction
The first conductive type semiconductor field stop layer (8) is formed on type semiconductor substrate；
Side above the first conductive type semiconductor field stop layer (8) forms first the first column of conductive type semiconductor area
(11-1) sequentially forms first the second column of conductive type semiconductor area in first the first column of conductive type semiconductor area (11-1)
(11-2) and the first conductive type semiconductor third column area (11-3), first conductive type semiconductor the first column area (11-1's) mixes
Doping concentration of the miscellaneous concentration less than first the second column of conductive type semiconductor area (11-2), first the second column of conductive type semiconductor
Doping concentration of the doping concentration in area (11-2) less than the first conductive type semiconductor third column area (11-3)；
The other side above the first conductive type semiconductor field stop layer (8) forms the second conductive type semiconductor column area (7),
It is led with first the first column of conductive type semiconductor area (11-1), first side of the second conductive type semiconductor column area (7)
The contact of the side in electric the second column of type semiconductor area (11-2) and the first conductive type semiconductor third column area (11-3)；Second
The second conductive type semiconductor base area (6), the second conductive type semiconductor are formed in the top in conductive type semiconductor column area (7)
The side of base area (6) is contacted with the side in the first conductive type semiconductor third column area (11-3)；
The first conductive type semiconductor source region (3-1) and the are formed in the top side of the second conductive type semiconductor base area (6)
Two conductive type semiconductor layers (5)；The side of the first conductive type semiconductor source region (3-1) and second conduction type
The side of semiconductor layer (5) contacts, and the first conductive type semiconductor source region (3-1) and first conduction type are partly led
There is the second conductive type semiconductor base area (6) between body third column area (11-3)；Second conductive type semiconductor layer (5) is used
The forbidden bandwidth of semiconductor material is less than the second conductive type semiconductor base area (6) and the first conductive type semiconductor source region (3-
1) forbidden bandwidth of semiconductor material used in；
In the first conductive type semiconductor third column area (11-3), on the second conductive type semiconductor base area (6) and the
Planar gate structure is formed in the first part of one conductive type semiconductor source region (3-1)；In second conductive type semiconductor
Source metal (4-1) is formed on layer (5) and on the second part of the first conductive type semiconductor source region (3-1)；
Metalized drain (10-1) is formed in the lower section of the first conductive type semiconductor substrate.
10. a kind of preparation method of superjunction MOS type power semiconductor, which comprises the following steps:
Second conductive type semiconductor collecting zone (13) of the second conductive type semiconductor substrate as device is chosen, described
The top of two conductive type semiconductor substrates forms the first conductive type semiconductor field stop layer (8)；
Side above the first conductive type semiconductor field stop layer (8) forms first the first column of conductive type semiconductor area
(11-1) sequentially forms first the second column of conductive type semiconductor area in first the first column of conductive type semiconductor area (11-1)
(11-2) and the first conductive type semiconductor third column area (11-3), first conductive type semiconductor the first column area (11-1's) mixes
Doping concentration of the miscellaneous concentration less than first the second column of conductive type semiconductor area (11-2), first the second column of conductive type semiconductor
Doping concentration of the doping concentration in area (11-2) less than the first conductive type semiconductor third column area (11-3)；
The other side above the first conductive type semiconductor field stop layer (8) forms the second conductive type semiconductor column area (7),
It is led with first the first column of conductive type semiconductor area (11-1), first side of the second conductive type semiconductor column area (7)
The contact of the side in electric the second column of type semiconductor area (11-2) and the first conductive type semiconductor third column area (11-3)；Second
The second conductive type semiconductor base area (6), the second conductive type semiconductor are formed in the top in conductive type semiconductor column area (7)
The side of base area (6) is contacted with the side in the first conductive type semiconductor third column area (11-3)；
The second conductive type semiconductor base area (6) top side formed the first conductive type semiconductor emitter region (3-2) and
Second conductive type semiconductor layer (5)；The side of the first conductive type semiconductor emitter region (3-2) and second conduction
The side of type semiconductor layer (5) contacts, and the first conductive type semiconductor emitter region (3-2) and first conductive-type
There is the second conductive type semiconductor base area (6) between type semiconductor third column area (11-3)；Second conductive type semiconductor layer
(5) forbidden bandwidth of semiconductor material used in is less than the second conductive type semiconductor base area (6) and the first conductive type semiconductor
The forbidden bandwidth of semiconductor material used in emitter region (3-2)；
In the first conductive type semiconductor third column area (11-3), on the second conductive type semiconductor base area (6) and the
Planar gate structure is formed in the first part of one conductive type semiconductor emitter region (3-2)；It is partly led in second conduction type
Emitter metal (4-2) is formed on body layer (5) and on the second part of the first conductive type semiconductor emitter region (3-2)；
The first conductive type semiconductor collecting zone (12) is formed in the side of the second conductive type semiconductor collecting zone (13)；
Gold is formed in the lower section of the second conductive type semiconductor collecting zone (13) and the first conductive type semiconductor collecting zone (12)
Categoryization collector (10-2).
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| CN112635544A (en) * | 2020-12-18 | 2021-04-09 | 华南师范大学 | Enhanced AlGaN-GaN vertical super-junction HEMT with dipole layer and preparation method thereof |
| CN113540204A (en) * | 2020-04-13 | 2021-10-22 | 上海新微技术研发中心有限公司 | Preparation method of semiconductor device structure |
| CN113540205A (en) * | 2020-04-13 | 2021-10-22 | 上海新微技术研发中心有限公司 | Semiconductor device structure |
| CN114256331A (en) * | 2021-12-22 | 2022-03-29 | 电子科技大学 | Super-junction reverse-conducting IGBT with heterojunction |
| CN114823531A (en) * | 2022-06-24 | 2022-07-29 | 北京芯可鉴科技有限公司 | Super junction device manufacturing method, super junction device, chip and circuit |
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