CN108881754A - A kind of interior desampling fir filter for realizing correlated-double-sampling of numeric field - Google Patents
A kind of interior desampling fir filter for realizing correlated-double-sampling of numeric field Download PDFInfo
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- CN108881754A CN108881754A CN201810796416.7A CN201810796416A CN108881754A CN 108881754 A CN108881754 A CN 108881754A CN 201810796416 A CN201810796416 A CN 201810796416A CN 108881754 A CN108881754 A CN 108881754A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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- Transforming Light Signals Into Electric Signals (AREA)
- Studio Devices (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention discloses the desampling fir filters that correlated-double-sampling is realized in a kind of numeric field；Including accumulator, adder, register, the buffer area of array, subtracter；Wherein, the input terminal of accumulator accesses BWI signal, and BWI signal is an enable signal, and control is structure that a step-by-step negates, this signal can control BS signal and directly input this structure or input after a phase inverter；The output end of accumulator connects adder, and adder connects register, and the buffer area of register output connection array, the buffer area of array connects subtracter, compensates to signal；Accumulator and register export respectively resets enable signal RST1 and RST2.The structure that step-by-step is negated shifts to an earlier date, and using less metal-oxide-semiconductor, lower power reaches same filter effect.When realization, low frequency noise can be effectively reduced for the structure for the correlated-double-sampling desampling fir filter that the demand of imaging sensor is proposed, reduce circuit area, reduce power consumption.
Description
Technical field
The present invention relates to image sensing areas, are especially a kind of interior down-sampled filtering for realizing correlated-double-sampling of numeric field
Device.
Background technique
With the raising of the pixel resolution of modern cmos image sensor, reading circuit needs analog-digital converter (ADC)
With higher data throughout.Use correlated-double-sampling (CDS) technology, it is possible to reduce low frequency noise.Correlated-double-sampling
Principle：Correlated-double-sampling (Correlated Double Sample, CDS) is used for imaging sensor.If in the product of photosignal
Divide start time t1 and integral finish time t2, output signal sampling (is exported in the period, generation two in a signal respectively
Sampling pulse, two level of sampled output signal, i.e., sampled to reset level respectively, and another time is to signal
Level is sampled), and make between the double sampling time spaced far less than time constant CRon, (Ron is reset transistor
Conducting resistance), the noise voltage of such double sampling is very nearly the same, and the time of double sampling is relevant again, if will adopt twice
Sample value is subtracted each other, and the interference of reset noise is just essentially eliminated, and obtains the actually active amplitude of signal level.
It is found by retrieval, a kind of desampling fir filter of the disclosure of the invention of patent No. CN200710118783.3, at least
Including the down-sampled filter module of the first order and second level anti-interference filtration module, the down-sampled filter module of the first order for pair
Input data carries out down-sampled processing, and the second level anti-interference filtration module is used for the down-sampled filter module of the first order
The down-sampled data generated carry out interference filter.Because the input data of second level anti-interference filtration module is dropped by the first order
The down-sampled processing of sampling filter module, data entry rate is far smaller than NCO and provides the defeated of data for desampling fir filter
Enter rate, in this way for the anti-interference filtration module of the second level, is able to carry out within a clock cycle of input data
Algorithm steps will greatly increase, to reduce the number of multipliers of second level anti-interference filtration inside modules, therefore effectively
Ground reduces the area of chip, reduces the power consumption of chip.
A kind of multiphase digital desampling fir filter of the disclosure of the invention of patent No. CN201310395866.2, shape filter
Input terminal is connected with the down-sampled rate controller of multiple, and output end connects adder；The next group of cascade integral comb filter
On the down-sampled rate controller of multiple and upper one group of cascade integral comb filter on the down-sampled controller of multiple between be arranged
There is delayer.This multiphase digital sampling filter can combine the lower cascade integral comb filter of the identical order of multiple groups
Into multiphase filter entirety, realize close to high-order cascade integral comb filter effect.
The analysis found that not there is the desampling fir filter for realizing correlated-double-sampling also at present.
Summary of the invention
Therefore, in order to solve above-mentioned deficiency, the drop that the present invention provides a kind of interior realization correlated-double-sampling of numeric field herein is adopted
Sample filter.The structure that step-by-step is negated shifts to an earlier date, and using less metal-oxide-semiconductor, lower power reaches same filter effect.
The invention is realized in this way a kind of interior desampling fir filter for realizing correlated-double-sampling of numeric field is constructed, it is special
Sign is：Including accumulator, adder, register, the buffer area of array, subtracter；
Wherein, the input terminal of accumulator accesses BWI signal, and BWI signal is an enable signal, and control is a step-by-step
The structure negated, this signal can control BS signal and directly input this structure or input after a phase inverter；
The output end of accumulator connects adder, and adder connects register, the buffer area of register output connection array, and array delays
Area's connection subtracter is rushed, signal is compensated；Accumulator and register export respectively resets enable signal RST1 and RST2.
As an improvement of the above technical solution, the desampling fir filter of correlated-double-sampling is realized in a kind of numeric field,
It is characterized in that：Accumulator is the accumulator of a 7bit, and adder is the adder of a 13bit, and register is one
The register of 13bit；Wherein, signal transmission is divided into two stages, is enabled by BWI, is divided into two stages of dec and inc.
The invention has the advantages that：The present invention provides a kind of interior down-sampled filter for realizing correlated-double-sampling of numeric field herein
Wave device.The structure that step-by-step is negated shifts to an earlier date, and using less metal-oxide-semiconductor, lower power reaches same filter effect.It realizes
When, low frequency can be effectively reduced for the structure for the correlated-double-sampling desampling fir filter that the demand of imaging sensor is proposed
Rate noise reduces circuit area, reduces power consumption.
Detailed description of the invention
Fig. 1 is the system block diagram of correlated-double-sampling desampling fir filter；
Fig. 2 is artificial circuit schematic diagram of the present invention；
Fig. 3 is signal output of the present invention and timing diagram.
Specific embodiment
Below in conjunction with attached drawing 1- Fig. 3, the present invention is described in detail, technical solution in the embodiment of the present invention into
Row clearly and completely describes, it is clear that described embodiments are only a part of the embodiments of the present invention, rather than whole realities
Apply example.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without making creative work
Every other embodiment, shall fall within the protection scope of the present invention.
The present invention provides a kind of interior desampling fir filter for realizing correlated-double-sampling of numeric field, such as Fig. 1 by improving herein
It is shown, it can be practiced as follows；Including accumulator, adder, register, the buffer area of array, subtracter；
Wherein, the input terminal of accumulator accesses BWI signal, and BWI signal is an enable signal, and control is a step-by-step
The structure negated, this signal can control BS signal and directly input this structure or input after a phase inverter；
The output end of accumulator connects adder, and adder connects register, the buffer area of register output connection array, and array delays
Area's connection subtracter is rushed, signal is compensated；Accumulator and register export respectively resets enable signal RST1 and RST2.
The system block diagram of correlated-double-sampling desampling fir filter is as shown in Figure 1：In Fig. 1, BWI signal is an enabled letter
Number, control is structure that a step-by-step negates, this signal can control BS signal and directly input this structure or process
It is inputted after one phase inverter.Ripple counter is the accumulator of a 7bit, and Adder is the adder of a 13bit,
Register is the register of a 13bit, and Scan Buffer is the buffer area of array.Subtractor is a subtracter,
Signal is compensated.RST1 and RST2 is to reset enable signal.
The derivation of equation of the present invention is as follows：
BSdec(k1)=Ddec(k1)
BSinc(k3)=1-Dinc(k3)
OSR=97,
Sfinal_conv=Sfinal-4753
Signal transmission is divided into two stages, is enabled by BWI, is divided into dec (BWI is 0 enabled) and inc (BWI is 1 enabled) two
A stage.
Circuit simulation：Signal output and timing diagram such as Fig. 3,
The present invention provides a kind of interior desampling fir filter for realizing correlated-double-sampling of numeric field herein.The knot that step-by-step is negated
Structure shifts to an earlier date, and using less metal-oxide-semiconductor, lower power reaches same filter effect.When realization, for the need of imaging sensor
It asks the structure of proposed correlated-double-sampling desampling fir filter that low frequency noise can be effectively reduced, reduces circuit area,
Reduce power consumption.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (2)
1. realizing the desampling fir filter of correlated-double-sampling in a kind of numeric field, it is characterised in that：Including, accumulator, adder,
Register, the buffer area of array, subtracter；
Wherein, the input terminal of accumulator accesses BWI signal, and BWI signal is an enable signal, and control is that a step-by-step negates
Structure, this signal can control BS signal and directly inputs this structure or by inputting after phase inverter；It is cumulative
The output end of device connects adder, and adder connects register, the buffer area of register output connection array, the buffer area of array
Subtracter is connected, signal is compensated；Accumulator and register export respectively resets enable signal RST1 and RST2.
2. the desampling fir filter of correlated-double-sampling is realized in a kind of numeric field according to claim 1, it is characterised in that：It is tired
Adding device is the accumulator of a 7bit, and adder is the adder of a 13bit, and register is the register of a 13bit；Its
In, signal transmission is divided into two stages, is enabled by BWI, is divided into two stages of dec and inc.
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| CN201810796416.7A CN108881754B (en) | 2018-07-19 | 2018-07-19 | Down-sampling filter for realizing correlated double sampling in digital domain |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024050718A1 (en) * | 2022-09-07 | 2024-03-14 | Huawei Technologies Co., Ltd. | Logical circuit and operation method in digital correlated double sampling |
| CN117714907A (en) * | 2024-02-06 | 2024-03-15 | 安徽大学 | FIR filter and ADC module for CMOS image sensor |
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| US5438532A (en) * | 1993-01-20 | 1995-08-01 | Sanyo Electric Co., Ltd. | Digital filter for use in synthesizing filter or a separation filter |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024050718A1 (en) * | 2022-09-07 | 2024-03-14 | Huawei Technologies Co., Ltd. | Logical circuit and operation method in digital correlated double sampling |
| CN117714907A (en) * | 2024-02-06 | 2024-03-15 | 安徽大学 | FIR filter and ADC module for CMOS image sensor |
| CN117714907B (en) * | 2024-02-06 | 2024-04-19 | 安徽大学 | FIR filter and ADC module for CMOS image sensor |
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| CN108881754B (en) | 2020-07-31 |
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