CN108807352A - 一种新型led灯丝制作技术 - Google Patents

一种新型led灯丝制作技术 Download PDF

Info

Publication number
CN108807352A
CN108807352A CN201710333795.1A CN201710333795A CN108807352A CN 108807352 A CN108807352 A CN 108807352A CN 201710333795 A CN201710333795 A CN 201710333795A CN 108807352 A CN108807352 A CN 108807352A
Authority
CN
China
Prior art keywords
substrate
chip
electrode
hole
tin cream
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710333795.1A
Other languages
English (en)
Other versions
CN108807352B (zh
Inventor
申凤仪
王秀瑜
申广
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Rewo Micro Semiconductor Technology Co ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN201710333795.1A priority Critical patent/CN108807352B/zh
Publication of CN108807352A publication Critical patent/CN108807352A/zh
Application granted granted Critical
Publication of CN108807352B publication Critical patent/CN108807352B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483Containers
    • H01L33/486Containers adapted for surface mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52Encapsulations
    • H01L33/56Materials, e.g. epoxy or silicone resin
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64Heat extraction or cooling elements
    • H01L33/647Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0033Processes relating to semiconductor body packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0033Processes relating to semiconductor body packages
    • H01L2933/005Processes relating to semiconductor body packages relating to encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0033Processes relating to semiconductor body packages
    • H01L2933/0066Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Led Device Packages (AREA)

Abstract

本发明提供了一种新型LED灯丝制作技术,尤其是采用预处理特制基板结合漏印锡膏技术,将基板接触LED芯片面首先涂覆绝缘胶,然后将基板对应芯片的P/N电极位置采用激光打通孔,将芯片电极面朝向涂覆绝缘胶的基板面,将芯片电极对应通孔安放,利用基板上的通孔采用漏印方法将锡膏漏印到到芯片电极面,加热焊接芯片电极与基板导通,最后再通过化学腐蚀或激光切割将基板对应芯片P/N电极中间绝缘河道部分的金属腐蚀掉,芯片电极面与基板形成锡膏焊接通路,在产品性能提升的同时,生产效率大幅提高,生产成本大幅降低。

Description

一种新型LED灯丝制作技术
技术领域
本发明涉及一种新型LED灯丝制作技术,特别涉及一种采用预处理特制基板结合漏印锡膏技术,将基板对应芯片的P/N电极位置采用激光打通孔,将芯片电极面朝向涂覆绝缘胶的基板面,将芯片电极对应通孔安放,使用常规正装芯片不需要打线,高效率低成本制作LED灯丝。
LED灯丝最近几年发展迅速,市场容量高速增长,目前LED灯丝主要制作技术主要分为两个大类,一类是采用LED正装芯片配合基板(玻璃、蓝宝石基板、陶瓷基板、金属基板)固晶、打线、模压封胶技术,一类是采用倒装LED芯片配合基板(PCB、FPC、印制电路的陶瓷基板、玻璃基板等)固晶、锡膏回流焊、模压封胶技术。
采用正装芯片制作的灯丝技术是目前LED灯丝行业的主流技术,由于LED固晶机、焊线机的价格比较昂贵,造成设备折旧成本较高,正装芯片采用LED芯片的蓝宝石面贴装结合基板,由于LED芯片的蓝宝石衬底的低导热系数,致使芯片散热性能较差。
倒装芯片制作LED灯丝,以PCB、FPC、印制电路的陶瓷基板、玻璃基板等为基板,在基板上印刷需要的连接线路和焊接装倒装LED芯片的焊接点,並进行蚀刻。在蚀刻好电路的基板上粘贴倒装LED芯片,过回流焊固化。模压封胶、涂覆荧光粉,然后加温固化。优点是可以节省打线机设备投资,同时由于LED芯片的 P/N电极面通过锡膏焊接与基板电路连接导通,芯片散热较好,缺点是倒装芯片价格高于正装芯片15%以上,另外对于10*30mil以下芯片由于芯片尺寸太小,在进行锡膏焊接时,容易造成芯片P/N电极间焊接短路。
发明内容总述
本发明提供了一种新型LED灯丝制作技术,尤其是采用预处理特制基板结合漏印锡膏技术,将基板接触LED芯片面首先涂覆绝缘胶,然后将基板采用激光对应芯片的P/N电极打通孔,将芯片电极面安装到对应位置后,利用基板上的通孔采用漏印方法将锡膏漏印到到芯片电极面,同时锡膏完全填充基板通孔,加热焊接芯片电极与基板导通,最后再通过化学腐蚀或激光切割将基板对应芯片P/N电极中间绝缘河道部分的金属腐蚀掉。包括以下步骤:
步骤一、基板预处理:将金属基板⑥(铜、铝、铁、锡、铅等导电金属或其他导电材料)等的一种作为灯丝封装的基板,基板厚度10--1000微米,将基板的一面涂覆1--1000微米厚的绝缘透明胶④(PTFE、环氧固晶胶、透明硅胶等);
步骤二、激光打孔:将预处理后的基板使用激光打孔机,按照芯片电极(P极)①、芯片电极(N极) ⑤对应位置进行激光打孔⑦、⑧(贯穿孔),孔径范围为微米,激光从基板涂覆绝缘透明胶④一面射入;
步骤三、芯片固晶:将芯片电极面对应基板涂覆绝缘透明胶④一面,按照芯片的两个电极①、⑤分别对位两个贯穿孔⑦、⑧,整个基板在相应位置安放好芯片,芯片摆放完毕后,将基板涂覆绝缘透明胶一面朝下平置于平整的工作台上并固定;
步骤四、锡膏漏印:在基板未涂覆绝缘透明胶一面用刮刀,将锡膏进行漏印,通过基板上的通孔⑦、⑧漏印到基板涂覆绝缘透明胶面的芯片对应电极①、⑤上;
步骤五、电极焊接:漏印完成后在基板未涂覆绝缘透明胶一面上覆盖电加热板,通电加热到230度正负5度,或者将漏印完成的基板放入电热箱中加热到230度正负5度;
步骤六、绝缘带制作:将电极焊接完成的基板两面涂覆一层基板腐蚀保护层(11)(1-1000微米的环氧固晶胶、PTFE胶、环氧或硅胶或者其他绝缘透明树脂),干燥固化后,在基板未安放芯片一面沿着通孔⑦、⑧之间,对应芯片电极间绝缘河道②的中心位置,采用激光切割或机械刀切划开绝缘层,划道宽度为30-50 微米,将基板置入酸槽中,使用硫酸、硝酸或其他腐蚀溶液将划道的基板金属层腐蚀贯穿彻底形成片电极 (P极)①、芯片电极(N极)⑤绝缘断裂道(12);
步骤七、清洗:将完成步骤六的部件进行清洗干燥;
步骤八:将完成步骤七的部件涂覆硅胶或环氧胶以及荧光胶,固胶、切割分离灯条。
本发明的有益效果:这种方法采用市场通用的正装芯片,节省了打线机设备投资,采用普通的金属基板降低材料成本,由于芯片与基板的结合面涂覆有透明胶,芯片P/N电极间形成物理阻隔,有效的杜绝了芯片P/N电极在锡膏焊接时的短路问题。芯片电极面与基板形成锡膏焊接通路,提高了芯片的导热散热性能,最后由于腐蚀掉了芯片的P/N电极中间的绝缘河道,芯片电极面没有不透光基板阻挡,使得芯片可以全周发光,在产品性能提升的同时,生产效率大幅提高,生产成本大幅降低。
图表说明
图1 本发明的结构示意图
图2 现有市场主流的灯丝结构示意图
图3 切割、分离后灯丝背视图
图4 切割、分离后灯丝俯视图
图5 基板腐蚀成型电路结构示意图
其中:1、芯片电极(P极) 2、芯片电极间绝缘河道 3、芯片蓝宝石衬底 4、透明绝缘胶 5、芯片电极(N 极) 6、基板 7、芯片电极(P极)通孔 8、芯片电极(N极)通孔 9、固晶胶10、金线 11、基板腐蚀保护层 12、基板绝缘断裂道
具体发明内容及实施方式
本发明提供了一种新型LED灯丝制作技术,尤其是采用预处理特制基板结合漏印锡膏技术,将基板接触LED芯片面首先涂覆绝缘胶,然后将基板采用激光对应芯片的P/N电极打通孔,将芯片电极面安装到对应位置后,利用基板上的通孔采用漏印方法将锡膏漏印到到芯片电极面,同时锡膏完全填充基板通孔,加热焊接芯片电极与基板导通,最后再通过化学腐蚀或激光切割将基板对应芯片P/N电极中间绝缘河道部分的金属腐蚀掉。这种方法采用市场通用的正装芯片,节省了固晶机、打线机设备投资,采用普通的金属基板降低材料成本,由于芯片与基板的结合面涂覆有透明胶,芯片P/N电极间形成物理阻隔,有效的杜绝了芯片P/N电极在锡膏焊接时的短路问题。由于芯片电极面与基板形成锡膏焊接通路,提高了芯片的导热散热性能,最后由于腐蚀掉了芯片的P/N电极中间的绝缘河道,芯片电极面没有不透光基板阻挡,使得芯片可以全周发光,在产品性能提升的同时,生产效率大幅提高,生产成本大幅降低。包括以下步骤:
以下附图和实施案例对本发明进行具体说明。
附图及具体实施方式或实施例都仅是示例性的,而非用于限制本发明。
实施例1:
选用LED芯片类型:正装蓝光芯片,芯片尺寸8*15mil,产品结构如图1所示.
步骤一、基板预处理:将金属基板⑥(铁板,基板厚度100-150微米)等的一种作为灯丝封装的基板,基板厚度200±50微米,将基板的一面涂覆50--100微米厚的绝缘透明胶④(环氧固晶胶);
步骤二、激光打孔:将预处理后的基板使用激光打孔机,按照芯片电极(P极)①、芯片电极(N极) ⑤对应位置进行激光打孔⑦、⑧(贯穿孔),孔径范围为微米,激光从基板涂覆绝缘透明胶④一面射入,步骤二完成部件如图3所示;
步骤三、芯片固晶:将芯片电极面对应基板涂覆绝缘透明胶④一面,按照芯片的两个电极①、⑤分别对位两个贯穿孔⑦、⑧,整个基板在相应位置安放好芯片,芯片摆放完毕后,将基板涂覆绝缘透明胶一面朝下平置于平整的工作台上并固定;
步骤四、锡膏漏印:在基板未涂覆绝缘透明胶一面用刮刀,将锡膏进行漏印,通过基板上的通孔⑦、⑧漏印到基板涂覆绝缘透明胶面的芯片对应电极①、⑤上;
步骤五、电极焊接:漏印完成后在基板未涂覆绝缘透明胶一面上覆盖电加热板,通电加热到230度正负5度,保温3分钟(或者将漏印完成的基板放入电热箱中加热到230度正负5度),然后自然降温到室温;
步骤六、绝缘带制作:将电极焊接完成的基板两面涂覆一层基板腐蚀保护层(11)(100±50微米的环氧固晶胶),干燥固化后,如图5所示在基板未安放芯片一面沿着通孔⑦、⑧之间,对应芯片电极间绝缘河道②的中心位置,采用激光切割或机械刀切划开绝缘层(将基板金属裸露),划道宽度为50±20微米,将基板置入酸槽中,使用硫酸、硝酸或其他腐蚀溶液将划道的基板金属层腐蚀贯穿彻底形成片电极(P极)①、芯片电极(N极)⑤绝缘断裂道(12);
步骤七、清洗:将完成步骤六的部件进行清洗干燥,步骤七完成部件如图4所示;
步骤八:将完成步骤七的部件涂覆硅胶或环氧胶以及荧光胶,固胶、切割分离灯条。

Claims (7)

1.一种新型LED灯丝制作技术,尤其是采用预处理预处理基板结合漏印锡膏技术,将基板对应芯片的P/N电极位置采用激光打通孔,将芯片电极面朝向涂覆绝缘胶的基板面,对应通孔位置安放,包括以下步骤:
步骤一、基板预处理:将金属基板⑥(铜、铝、铁、锡、铅等导电金属或其他导电材料)等的一种作为灯丝封装的基板,基板厚度10--1000微米,将基板的一面涂覆1--1000微米厚的绝缘透明胶④(PTFE、环氧固晶胶、透明硅胶等);
步骤二、激光打孔:将预处理后的基板使用激光打孔机,按照芯片电极(P极)①、芯片电极(N极)⑤对应位置进行激光打孔⑦、⑧(贯穿孔),孔径范围为微米,激光从基板涂覆绝缘透明胶④一面射入;
步骤三、芯片固晶:将芯片电极面对应基板涂覆绝缘透明胶④一面,按照芯片的两个电极①、⑤分别对位两个贯穿孔⑦、⑧,整个基板在相应位置安放好芯片,芯片摆放完毕后,将基板涂覆绝缘透明胶一面朝下平置于平整的工作台上并固定;
步骤四、锡膏漏印:在基板未涂覆绝缘透明胶一面用刮刀,将锡膏进行漏印,通过基板上的通孔⑦、⑧漏印到基板涂覆绝缘透明胶面的芯片对应电极①、⑤上;
步骤五、电极焊接:漏印完成后在基板未涂覆绝缘透明胶一面上覆盖电加热板,通电加热到230度正负5度,或者将漏印完成的基板放入电热箱中加热到230度正负5度;
步骤六、绝缘带制作:将电极焊接完成的基板两面涂覆一层基板腐蚀保护层(11)(1-1000微米的环氧固晶胶、PTFE胶、环氧或硅胶或者其他绝缘透明树脂),干燥固化后,在基板未安放芯片一面沿着通孔⑦、⑧之间,对应芯片电极间绝缘河道②的中心位置,采用激光切割或机械刀切划开绝缘层,划道宽度为30-50微米,将基板置入酸槽中,使用硫酸、硝酸或其他腐蚀溶液将划道的基板金属层腐蚀贯穿彻底形成片电极(P极)①、芯片电极(N极)⑤绝缘断裂道(12);
步骤七、清洗:将完成步骤六的部件进行清洗干燥;
步骤八:将完成步骤七的部件涂覆硅胶或环氧胶以及荧光胶,固胶、切割分离灯条。
2.根据权利要求1所述的新型LED灯丝制作技术,其特征在于,选用10-1000微米金属基板⑥并采用两面或单面涂绝缘胶⑧,涂胶厚度为1-1000微米。
3.根据权利要求1所述的新型LED灯丝制作技术,其特征在于,将预处理后的基板使用激光打孔机,按照芯片电极(P极)①、芯片电极(N极)⑤对应位置进行激光打孔⑦、⑧(贯穿孔),孔径范围为微米,激光从基板涂覆绝缘透明胶④一面射入,贯穿孔用来将芯片电极漏印锡膏并形成芯片电极与基板的导电连接。
4.根据权利要求1所述的新型LED灯丝制作技术,其特征在于,芯片电极(P极)①、芯片电极(N极)⑤对应基板基板涂覆绝缘透明胶④一面固晶安放,芯片的两个电极①、⑤分别对位两个贯穿孔⑦、⑧,整个基板在相应位置摆放好芯片,芯片摆放完毕后,芯片电极中心对应基板贯通孔的中心点。
5.根据权利要求1所述的新型LED灯丝制作技术,其特征在于,采用细粒径锡膏,使用漏印技术,将锡膏通过基板通孔漏印到芯片电极①、⑤上,锡膏填满基板通孔⑦、⑧。
6.根据权利要求1所述的新型LED灯丝制作技术,其特征在于采用电热板或电热箱进行电极焊接。
7.根据权利要求1所述的新型LED灯丝制作技术,其特征在于采用硫酸、硝酸或其他化学腐蚀液将基板进行腐蚀以形成相应的电路。
CN201710333795.1A 2017-05-03 2017-05-03 一种新型led灯丝制作方法 Active CN108807352B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710333795.1A CN108807352B (zh) 2017-05-03 2017-05-03 一种新型led灯丝制作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710333795.1A CN108807352B (zh) 2017-05-03 2017-05-03 一种新型led灯丝制作方法

Publications (2)

Publication Number Publication Date
CN108807352A true CN108807352A (zh) 2018-11-13
CN108807352B CN108807352B (zh) 2020-07-14

Family

ID=64094485

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710333795.1A Active CN108807352B (zh) 2017-05-03 2017-05-03 一种新型led灯丝制作方法

Country Status (1)

Country Link
CN (1) CN108807352B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109817769A (zh) * 2019-01-15 2019-05-28 申广 一种新型led芯片封装制作方法
CN109817796A (zh) * 2019-01-24 2019-05-28 南通沃特光电科技有限公司 一种具有双层荧光层的led封装结构及其封装方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102222667A (zh) * 2011-07-14 2011-10-19 东莞市邦臣光电有限公司 一种led光源模块及其封装工艺
CN103828076A (zh) * 2011-08-01 2014-05-28 株式会社Steq 半导体装置及其制造方法
CN204011418U (zh) * 2014-07-25 2014-12-10 胡溢文 一种设有正装倒置芯片的led灯丝
CN104900535A (zh) * 2015-04-07 2015-09-09 北京理工大学 太赫兹芯片倒桩焊背景下陶瓷薄膜导电过孔的焊料填充工艺
US20160300821A1 (en) * 2015-02-25 2016-10-13 Lextar Electronics Corporation Light-emitting diode chip package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102222667A (zh) * 2011-07-14 2011-10-19 东莞市邦臣光电有限公司 一种led光源模块及其封装工艺
CN103828076A (zh) * 2011-08-01 2014-05-28 株式会社Steq 半导体装置及其制造方法
CN204011418U (zh) * 2014-07-25 2014-12-10 胡溢文 一种设有正装倒置芯片的led灯丝
US20160300821A1 (en) * 2015-02-25 2016-10-13 Lextar Electronics Corporation Light-emitting diode chip package
CN104900535A (zh) * 2015-04-07 2015-09-09 北京理工大学 太赫兹芯片倒桩焊背景下陶瓷薄膜导电过孔的焊料填充工艺

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109817769A (zh) * 2019-01-15 2019-05-28 申广 一种新型led芯片封装制作方法
CN109817796A (zh) * 2019-01-24 2019-05-28 南通沃特光电科技有限公司 一种具有双层荧光层的led封装结构及其封装方法

Also Published As

Publication number Publication date
CN108807352B (zh) 2020-07-14

Similar Documents

Publication Publication Date Title
CN105185752B (zh) 半导体器件及其制造方法
CN114068734A (zh) 一种光伏电池组件的制造方法
CN100492632C (zh) 电路装置及其制造方法
US20140230878A1 (en) Method for electrically connecting several solar cells and photovoltaic module
CN203367260U (zh) 一种功率陶瓷外壳和功率芯片封装结构
CN107275463A (zh) 一种新型led封装制作技术
KR20170126469A (ko) 칩 배열 및 접촉 연결을 형성하는 방법
CN108807352A (zh) 一种新型led灯丝制作技术
CN110473853A (zh) 一种dfn器件的封装结构、无引线框架载体及dfn器件的封装方法
CN207781646U (zh) 一种led芯片倒装焊接结构和led灯珠
TWI697058B (zh) 具堅實導電及導熱性銅質線路之電路元件封裝方法及其封裝體
CN103314453B (zh) 太阳能电池模块及太阳能电池模块的制造方法
CN111403296B (zh) 一种半导体封装件及其制作方法
CN111933784A (zh) 一种激光芯片的陶瓷封装方法及陶瓷封装芯片结构
CN103151430B (zh) 纳米金属粒实现led的低温金属界面连接的制备方法
CN106340581A (zh) 一种csp灯珠封装的方法
CN211656532U (zh) 一种d2pak封装mos管的pcb贴片结构
CN105355567B (zh) 双面蚀刻水滴凸点式封装结构及其工艺方法
CN105206594B (zh) 单面蚀刻水滴凸点式封装结构及其工艺方法
CN209496814U (zh) 一种封装载板、封装体
CN209544338U (zh) 一种封装载板及封装体
CN206370416U (zh) 一种二极管封装结构
CN105428514A (zh) 一种集成led光源导热结构及其实现方法
CN206877993U (zh) 一种led基于正面焊盘可共晶的封装结构
CN206789535U (zh) 一种电力电子器件的扇出型封装结构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20220829

Address after: 1104-E21, 11th Floor, Life Insurance Building, No. 1001, Fuzhong 1st Road, Fuzhong Community, Lianhua Street, Futian District, Shenzhen, Guangdong 518000

Patentee after: Shenzhen Rewo Micro Semiconductor Technology Co.,Ltd.

Address before: Building 3, Penghui Plaza, No. 48, Heishijiao Street, Shahekou District, Dalian City, Liaoning Province 116023

Patentee before: Shen Guang