CN108807194A - 使用低温过程的高温半导体器件封装和结构的方法及装置 - Google Patents

使用低温过程的高温半导体器件封装和结构的方法及装置 Download PDF

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Publication number
CN108807194A
CN108807194A CN201810722489.1A CN201810722489A CN108807194A CN 108807194 A CN108807194 A CN 108807194A CN 201810722489 A CN201810722489 A CN 201810722489A CN 108807194 A CN108807194 A CN 108807194A
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silver
sintering
material part
semiconductor packages
hole
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CN108807194B (zh
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拉克希米纳拉扬.维斯瓦纳坦
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NXP USA Inc
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NXP USA Inc
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Abstract

一种使用低温过程的高温半导体器件封装和结构的方法及装置。提供了包含陶瓷、有机和金属材料的组合的半导体器件封装，其中这些材料通过使用银而耦合。在压力和低温下，银以细颗粒的形式被应用。应用之后，银形成了具有银的典型熔点的固体，因此，成品封装能承受比制造温度显著高的温度。此外，因为银是各种组合材料之间的接口材料，由于接合的低温度和银的延展性，陶瓷、有机和金属组件之间的不同材料特性的效果例如热膨胀系数被降低。

Description

使用低温过程的高温半导体器件封装和结构的方法及装置
本申请是2014年10月31日提交的、申请号为201410601839.0、发明名称为“使用低温过程的高温半导体器件封装和结构的方法及装置”的专利申请的分案申请。
技术领域
本发明一般地涉及半导体器件封装，更具体地说，涉及用于制作高温和高性能半导体器件封装的低温过程。
背景技术
各种半导体器件封装包括陶瓷、有机和金属材料的组合。为了形成半导体器件封装的可用结构，这些不同的材料彼此接触。这些不同的材料通常具有显著不同的材料性能，这就会导致包含这些材料的半导体器件封装的故障。因此，期望具有包含具有不同的材料性能但不受到由于不同的材料性能(例如热膨胀系数)引起的故障的材料的半导体器件封装。
发明内容
在一种实施方式中，一种半导体器件封装包括：
所述半导体器件封装的第一材料部分，其中第一材料包括陶瓷或有机材料中的一个；
所述半导体器件封装的第二材料部分，其中第二材料包括金属材料；以及
被放置为耦合所述半导体器件封装的所述第一和第二材料部分的烧结银区域；其中：
所述第一材料部分包括印刷电路板，以及
所述烧结银区域被放置在形成于所述印刷电路板内的孔内。
示例地，所述第二材料部分是被放置在所述烧结银区域内的金属块。
示例地，所述半导体器件封装还包括热耦合于所述金属块的半导体器件管芯，其中所述金属块包括铜。
示例地，所述半导体器件封装还包括被放置在所述烧结银内的第二金属块，所述烧结银热电耦合所述金属块和所述第二金属块。
示例地，所述第二材料部分包括被放置在所述烧结银区域内的无源电子器件，其中所述烧结银将所述无源电子器件电耦合于形成于所述印刷电路板上的互连处。
示例地，所述无源电子器件包括高电容材料。
在一种实施方式中，一种形成半导体器件封装的方法包括：
由第一材料形成半导体器件封装的第一材料部分，其中第一材料包括陶瓷或有机材料中的一个；
提供半导体器件封装的第二材料部分，其中第二材料部分包括陶瓷或金属材料；以及
使用烧结银区域来粘性地将半导体器件封装的第一材料部分和第二材料部分相耦合。
示例地：
半导体器件封装包括气腔封装；
形成第一材料部分进一步包括形成陶瓷窗框；以及
第二材料部分包括导电金属底板。
示例地：
半导体器件封装包括气腔封装；
形成第一材料部分进一步包括形成陶瓷窗框；以及
第二材料部分包括导电金属引线。
示例地：
形成第一材料部分进一步包括形成印刷电路板和在印刷电路板内形成孔；
所述粘性地耦合包括在印刷电路板内的孔中形成烧结银区域。
示例地，所述方法进一步包括：将第二材料部分置于烧结银区域，其中第二金属部分为金属块。
在一种实施方式中，一种形成半导体器件封装的方法包括：
在封装基板内形成孔；
将包括颗粒银的材料置于孔内；
在孔内放置金属币；以及
执行烧结过程以将包括颗粒银的材料转换为烧结银，其中烧结银将金属币耦合到封装基板。
示例地，封装基板是印刷电路板。
示例地，将包括颗粒银的材料置于孔内包括：在孔内施加细颗粒银或纳米银浆。
示例地，所述执行烧结过程包括：将半导体器件封装提供于低于银的熔点的形成温度下，形成温度在200℃和300℃之间。
示例地，所述方法进一步包括：以烧结银将半导体管芯附装到金属币。
示例地，金属币由选自铜、铝、A1SiC、Ag金刚石以及Cu石墨的一种材料形成。
示例地，所述方法进一步包括：沿着孔的边缘施加镀层金属。
在一种实施方式中，一种形成半导体器件封装的方法包括：
在底板的顶面和绝缘框架的底面之间施加包括颗粒银的材料；以及
执行烧结过程以将包括颗粒银的材料转换为烧结银，其中烧结银将绝缘框架的底面耦合到底板的顶面。
示例地，施加包括颗粒银的材料包括：在底板的顶面和绝缘框架的底面之间施加细颗粒银或纳米银浆。
示例地，所述执行烧结过程包括：将半导体器件封装提供于低于银的熔点的形成温度下，形成温度在200℃和300℃之间。
示例地，绝缘框架由陶瓷材料形成，底板包括固体铜。
示例地，所述方法进一步包括：在绝缘框架的顶面上形成金属化层。
示例地，底板包括选自CuMoCu压层、Cu(CuMo)Cu压层、CuW中的至少一种材料。
示例地，所述方法进一步包括：
在绝缘框架的顶面和导电金属引线之间施加包括颗粒银的材料；以及
执行烧结过程以将包括颗粒银的材料转换为烧结银，其中烧结银将导电金属引线耦合到绝缘框架的顶面。
示例地，导电金属引线包括固体铜。
在一种实施方式中，一种半导体器件包括：
具有顶面和底面的绝缘框架；
具有顶面的基板，其具有接口区域；以及
在绝缘框架的底面和基板的顶面的接口区域之间的烧结银，其中烧结银将绝缘框架的底面直接耦合到基板的顶面。
示例地，绝缘框架由陶瓷材料形成。
示例地，绝缘框架在底面上包括金属化层。
示例地，绝缘框架通过选自铜、镍/金、TiNiAu、TiW、金中的一种材料而被金属化。
示例地，基板包括固体铜。
示例地，基板包括选自CuMoCu压层、Cu(CuMo)Cu压层、CuW中的至少一种材料。
示例地，所述半导体器件进一步包括：通过烧结银而耦合到绝缘框架的顶面的导电金属引线。
示例地，导电金属引线包括固体铜。
示例地，所述半导体器件进一步包括：
通过烧结银而耦合到基板的管芯连接区域的半导体器件管芯；
在半导体器件管芯和导电金属引线之间的电接触；以及
气腔盖，其中气腔盖耦合到绝缘框架的顶面和导电金属引线。
示例地，所述半导体器件进一步包括：通过烧结银而耦合到基板的管芯连接区域的半导体器件管芯。
附图说明
通过参考附图，本发明或可被更好的理解，并且其多个目的、特征，以及优点对本领域技术人员来说会非常清楚。
图1是图示了气腔封装的截面图的简化框图。
图2是图示了气腔封装的平面图的简化框图。
图3是***在其中器件管芯耦合于嵌入在PCB或其它封装衬底的金属币或金属块的处理阶段的截面图的简化框图。
图4是***在其中器件管芯耦合于PCB或其它封装衬底中的烧结银通孔的处理阶段的截面图的简化框图。
图5是***在其中铜块包含在烧结银大通孔内的处理阶段的截面图的简化框图。
图6是***在其中一对金属块包含在烧结银大通孔内的处理阶段的截面图的简化框图。
图7是***在其中无源组件包含在烧结银大通孔内的处理阶段的截面图的简化框图。
除非另有说明，不同附图中使用的相同参考符号表示相同的元素。附图不一定按比例绘制。
具体实施方式
本发明的实施例提供了包含陶瓷、有机、金属材料的组合的半导体器件封装，其中这些材料通过使用银来耦合。在压力和低温下(例如在250℃烧结)，银以细颗粒(例如，纳米颗粒银)的形式被应用。应用之后，银形成了具有银的典型熔点(即，大约962℃)的固体，因此，成品封装能承受比制造温度显著更高的温度。此外，因为银是各种组合材料之间的接口材料，由于接合的低温度和银的延展性，陶瓷、有机和金属组件之间的不同材料特性的效果例如热膨胀系数被降低。在其它实施例中，银可以用于代替或连同印刷电路板内的铜块用于附着散热器或大通孔。这样的实施例提供了比典型用于所包括的铜块更薄的PCB。
不同类型的高性能半导体器件封装包含陶瓷、有机和金属材料的组合。但是，这些材料的不同性能特性会导致合成封装的故障。例如，陶瓷和铜之间的广泛不同的热膨胀系数会导致封装中的高应力，从而在这些材料之间的连接附近导致封装的翘曲和破裂。
这样的封装的一个例子是气腔封装，其通常包括一个或多个被附接到底板和围绕管芯的绝缘窗框的半导体器件。盖被放置在窗框上，从而封装了气腔内的管芯。气腔封装可以被用于容纳高频器件，例如射频(RF)管芯。如与具有比空气高的介电常数的模塑化合物中的封装相比，在封装的空气中封装高频半导体器件可以提高模具管芯和电引线的高频性能。
图1是图示了气腔封装100的截面图的简化框图。图2是图示了气腔封装100的平面图的简化框图。气腔封装使用可以包含管芯连接区域120的导电金属底板110。由陶瓷材料做成的窗框130被附接到导电金属底板。在管芯附接过程之前，窗框130通常被附接到导电金属底板。导线140被放置在窗框的顶面上并用于制作到包括在封装内的管芯150的电接触142和144。沿着窗框130的顶部，导线140可以被***到凹口。盖160被附接到引线和窗框的顶部，其封装了腔170。
如图1所示的，用于形成气腔封装的常规方法包括使用高温钎焊工艺(例如，850℃)将窗框130附接到导电金属底板110。这样高的加工温度排除了使用具有陶瓷窗框的铜底板，因为在铜和陶瓷材料之间的热膨胀系数(CTE)不匹配在钎焊温度下引起陶瓷窗框的破裂。因此，当陶瓷窗框被使用时，导电金属底板110通常由CuMoCu或Cu(CuMo)铜压层板或CuW制成。但是CuMoCu和Cu(CuMo)铜压层板以及CuW具有比纯铜显著低的热导率，从而降低了封装的整体散热性能。
虽然在管芯附接之前，环氧树脂可以被用于将陶瓷窗框附接到金属底板，环氧树脂在后续高温管芯连接工艺期间可以被损坏，从而具有较低的可靠性。虽然一些常规气腔技术可以包括在管芯附接之后附接窗框，那些窗框通常由塑料制成，其中该塑料具有比陶瓷窗框低的热导率和电容。这可以将具有塑料窗框的气腔封装的使用限制到较低功率应用。
本发明的实施例提供了将银用作陶瓷窗框130和导电金属底板110和导线140之间的接口材料(例如，在接口区域175和180)。通过使用低温烧结技术，银被应用，其中在该技术中，细颗粒银浆、粉末或薄膜在热和压力下被应用于感兴趣的区域。银颗粒是纳米规模，因此形成了颗粒的分子表面能量可以支配颗粒之间的相互作用，包括表面张力，从而允许在显著低于银的熔点的温度形成固体银。一旦形成固体银区域，典型的银熔点将适用(即，大约960℃)。
在图1和图2所示的气腔封装中，银烧结过程可以通过将细颗粒银应用于接口区域175处的导电金属基片110被执行。陶瓷窗框130然后在足以使银颗粒彼此接合的温度和压力下被应用于细颗粒银并且被应用于陶瓷窗框和导电金属底板的材料。为了增强银和陶瓷窗框之间的接合，陶瓷窗框可以通过使用本领域已知的多种金属技术而被金属化(金属化层135)。例如，陶瓷窗框可以通过使用直接电镀铜工艺、直接接合铜工艺、难熔金属火加镍/金电镀或使用TiNiAu、TiW、金等等的薄膜工艺而被金属化。
在一个实施例中，在烧结过程中所用的温度大约在200-300℃之间，并且通常大约在250℃，远低于现有技术气腔封装所用的钎焊温度。同样，细颗粒银可以在接口区域180应用于陶瓷窗框130，并且导线140可以在温度和压力下被应用以使银粒子接合。接口处的烧结银提供了双重效果，将不同的材料粘接在一起的耦合和电/热耦合。
细颗粒银可以通过使用各种技术被应用。含有细颗粒银的浆可以被使用。这种浆可以被喷上、印上或以其它方式被应用。细颗粒银的粉末形式也可以被使用，并且使用类似的方法被应用。或者，包含细颗粒银和有机材料的预先形成的薄膜可以通过将薄膜放置在需要在低温(例如，250℃)和附加压力下被接合的部件之间而被使用。薄膜的有机材料在这种工艺调节下被移除并且固体银被形成。
由于接合工艺在比现有技术钎焊技术显著低的温度下被执行，由于陶瓷和金属的不同CTE造成的影响被避免(例如，陶瓷破裂和翘曲)。而且，更便宜和更有效的材料可以被用于导电金属底板110。例如，固体铜法兰而不是层压法兰可以被用作导电金属底板。此外，导线140可以由固体铜而不是合金来形成。在这两种情况下，使用固体铜，而非层压材料或合金，提高了导电性，并且在导电金属底板的情况下，提高了热导率。固体铜还提供了比层压材料和合金更优的显著成本效益。法兰的管芯附接区域可以包括例如AuSi、AuSn或烧结银等等。此外，根据应用的需要，封装***可以被电镀以覆盖烧结银，例如在封装堆积的不同阶段(例如，在管芯附接之前和封装封盖之后)使用NiAu或NiPdAu。
可以将从使用烧结银获得的优点的另一半导体器件封装结构用于高功率器件，其中该器件采用封装衬底或PCB中的金属币。传统上，功率组件被提供给***，该***使用耦合于***PCB的单独封装组件。散热器耦合于功率组件封装。因此，组件封装和散热器中的功率器件管芯之间可以有多个连接。这将导致热量从功率器件管芯低效率传递到散热器。此外，功率组件封装以及所有各种连接将占用***封装中的显著空间。而且，由于只限于提供封装组件的几何形状，使用这些封装组件限制了***几何形状的灵活性。
图3是***300在其中功率器件管芯耦合于嵌入在PCB或其它封装衬底的金属币或金属块(或者，功率器件管芯或无源器件管芯可以耦合于金属币或块以提高接地)的处理阶段的截面图的简化框图。***300包括封装衬底310，例如PCB。封装衬底310具有嵌入的金属币320和330。金属币具有高热和电导电性，这取决于应用。对于许多热应用，铜币被应用，这是因为铜的高电和热性能。此外，铜可很容易地合并到电路板设计。在下面的例子中，金属币具体被讨论为铜，但具有高热和电导电性的其它金属(例如，铝)和复合材料(例如，AlSiC、Ag金刚石以及Cu石墨)可以被使用，如应用所允许的。
如将在下面更充分讨论的，嵌入式铜币320和330可以使用本领域已知的方法被嵌入，这将根据应用而定。功率器件管芯340和350分别耦合于嵌入式铜币320和330。如将在下面更充分讨论的，用于将功率器件管芯耦合于嵌入式铜币的方法取决于应用。功率器件管芯340和350分别在耦合区域342和352耦合于嵌入式铜币。该耦合区域可以是热或电的或两者，这取决于应用。在与包括耦合区域的主要表面相对的功率器件管芯的主要表面上，功率器件管芯340包括终端垫344和346，而功率器件管芯350包括信号垫354和356。器件管芯360被显示为粘接地耦合于封装衬底310。器件管芯360可以是不需要耦合于例如低功率器件管芯或无源组件的嵌入式铜币的优点的任何组件。器件管芯360包括位于与耦合于封装衬底的主要表面相对的主要表面上的终端垫，例如终端垫362。
功率器件管芯可以以各种方式耦合于嵌入式铜币，这取决于铜币是否被嵌入到预装配PCB或者最初从PCB分离并且随后在附接到功率器件管芯之后，在铜币周围预装配。在铜币被嵌入到预装配PCB的这些情况下，用于将功率器件管芯附接到铜币的方法应该考虑与预制PCB相关联的温度限制。也就是说，如果过高的温度被用于将功率器件管芯耦合于嵌入式铜币，那么可能会损坏预制PCB的其它区域。这种耦合可以利用低温银管芯附接被执行。通过使用大约250℃的温度，在本领域已知的低温银管芯附接方法可以在硅管芯和铜币之间形成可接受的粘结。这种低温管芯附接技术包括使用纳米银浆或烧结银，如上所讨论的，并且通常提供比传统焊锡技术更好的电学、热学和热力学性能。如上所述，使用低温管芯连接技术将功率器件管芯耦合于嵌入式铜币的另一个优点是将避免损坏PCB的剩余部分。
引线接合370、375、380和385被用于将功率器件管芯340和350以及器件管芯360的有源表面上接触垫彼此耦合并且与衬底310(未示出)上的接触垫耦合。衬底(未示出)上的互连和其它电路可以提供各种器件管芯之间的附加连接。在形成由引线接合提供的通信网之后，模制塑料被应用于功率器件管芯、器件管芯、引线接合上及其周围以及衬底上，从而形成密封模制塑料内的结构并且形成面板的封装剂390。
成型材料可以是任何合适的封装剂，包括例如二氧化硅填充的环氧模塑料、塑料封装树脂和其它聚合物材料，例如硅树脂、聚酰亚胺、酚醛树脂和聚氨酯。成型材料可以通过在封装中使用的各种标准处理技术包括例如印刷、压力成型和自旋应用被应用。一旦成型材料被应用，面板可以通过使材料暴露在一定温度下一段时间，或通过应用固化剂，或两者而被固化。在典型的封装过程中，封装剂390的深度可以超过嵌入在模塑料中的结构的最大高度。
在替代实施例中，图3的引线接合结构可以被封装成气腔***。在这种情况下，封装剂不会被用于覆盖***的各种组件。相反，预成型腔封装可以被用于包围各个组件并且盖可以替代封装剂以保护腔封装内的组件。在一些情况下，硅凝胶通过被应用于组件和引线接合上及其周围可以被用于进一步保护组件。在另一个替代实施例中，引线可以被替换为重新分配的管芯级封装***以提供引线接合互连。
如上所讨论的，嵌入式铜币320和330通常使用多种本领域已知的技术被嵌入在衬底310。一种技术包括在铜币周围建立衬底(例如，PCB)。币至少机械地附接到组合衬底，并且随着衬底被建立，根据应用的需要，也可以电耦合于衬底。另一种技术包括将币压拟合在预先建立的衬底。在这种情况下，嵌入式铜币被机械地附接到衬底。合并嵌入式铜币的这两种现有技术方法的缺点是衬底的必要厚度。在典型的应用中，衬底将位于32(例如，建立)和40(例如，压拟合)密耳之间。
图4是***400在其中器件管芯耦合于PCB或其它封装衬底中的烧结银通孔的处理阶段的截面图的简化框图。图4是图3结构的替代，因为图3的嵌入式铜币被大通孔430和440替代。大通孔420和430是由烧结银制成的并粘结到衬底410的有机材料。烧结银材料可以直接粘结到衬底410的有机材料，或者，如图所示，通过中间粘结电镀金属425和435沿着钻孔的边缘分别通过通孔420和430的衬底。如上所讨论的，烧结银通孔420和430可以通过在低温和附加压力下使用应用于大通孔的细颗粒银浆，或在低温和附加压力下使用预成形薄膜被形成。粘结到电镀金属的银进而被粘结到多层印刷电路板。粘结的电镀金属425和435是各种电镀金属，这将根据应用而定，并且通常可以是银、铜、钯或金。
如图4所示，使用由烧结银形成的大通孔的优点就是显著减小了位于包含嵌入式铜币的PCB上的印刷电路板的厚度。通过使用本领域已知的技术，功率器件管芯340和350热和/或电耦合于大通孔以耦合于银(或可，无源半导体器件可以耦合于大通孔)。所说明的用于***400的其它组件对应于图3中***300的相似编号元件。
通过使用烧结银形成大通孔也提供了将其它材料和器件合并到大通孔区域内的机会。这是由于低温形成的银，以及所形成的银的电热耦合性能。
图5是***在其中铜块包含在烧结银大通孔内的处理阶段的截面图的简化框图。衬底510包括大通孔515。通过使用本领域已知的技术，大通孔515可以通过使用电镀金属，例如金、银或铜而沿着边缘被电镀。大通孔515还包括烧结银530和铜块540。在应用用于形成烧结银530的细颗粒银(例如，纳米银浆)之前或之后，铜块540被放入适当位置。随后，烧结过程可以被应用于大通孔区域以形成具有烧结银和铜块的大通孔。这样的大通孔可以包含烧结银的优点(例如，薄、电、并且成本低)和铜的热优点。根据应用的需要，替代金属块可以被用于代替铜块。此外，替选的金刚石或陶瓷，例如具有电介质和导电元件的低温共烧陶瓷(LTCC)，可以被包括在大通孔内以代替铜块540。
图6是***在其中一对金属块包含在烧结银大通孔内的处理阶段的截面图的简化框图。衬底610包括大通孔615。大通孔可以例如通过钻过程或在衬底的积聚期间形成。通孔沿着主要表面的区域可以大于PCB内的区域。大通孔的侧面可以通过使用电镀金属，例如金、银或铜(例如，620)而被金属化。烧结银630和金属块640以及645包含在通孔内，其中银被粘结到金属化620。如同图5的实施例，在低温(例如，250℃)下，银以细颗粒银(例如，纳米银浆)的形式被引入到通孔615，并且在某些应用中，有附加压力以形成烧结银。根据应用，金属块640和645可以是铜块或另一种金属。电镀金属620可以提供到PCB的有机部分的物理连接和到金属化互连的电连接，其中该互联位于PCB的层压内或沿着表面建立。
图7是***在其中无源组件包含在烧结银大通孔内的处理阶段的截面图的简化框图。衬底710包括大通孔715。大通孔可以例如通过钻过程或在衬底的积聚期间形成。通孔沿着主要表面的区域可以大于PCB内的区域。大通孔顶部和底部区域的侧面可以通过使用电镀金属，例如金、银或铜(例如，720)而被金属化。烧结银730连同低成本管芯组件740位于大通孔内。低成本管芯组件740可以例如是位于由烧结银730和电镀金属720定义的电通路内的高电容(HIC)组件。如同图6的实施例，电镀金属720可以提供到PCB的有机部分的物理连接和到金属化互连的电连接，其中该互连位于PCB的层压内或沿着表面建立。
目前应了解，提供了一种半导体器件封装，该封装包括半导体器件封装的第一材料部分，其包括陶瓷或有机材料中的一个；半导体器件封装的第二材料部分，其包括金属材料；以及被放置为耦合所述半导体器件封装的所述第一和第二材料部分的烧结银区域。在上述实施例的一方面，所述半导体器件封装是气腔封装，所述第一材料部分包括金属化陶瓷窗框，以及所述第二材料部分包括导电金属底板。在另一方面，所述第二材料部分包括固体铜金属底板。
在上述实施例的另一方面，所述半导体器件封装是气腔封装，所述第一材料部分包括金属化陶瓷窗框，以及所述第二材料部分包括导电金属引线。另一方面包括气腔盖。所述气腔盖通过使用一层烧结银粘接地耦合于所述金属化陶瓷窗框的表面以及所述导电金属引线的表面。
在上述实施例的另一方面，所述烧结银区域是通过在比银的熔点低的形成温度应用细颗粒银被形成的。在另一方面，所述形成温度位于大约200℃和300℃之间。
在上述实施例的另一方面，所述第一材料部分包括印刷电路板，以及所述烧结银区域被放置在形成于所述印刷电路板内的孔内。在另一方面，所述第二材料部分是被放置在所述烧结银区域内的金属块。另一方面包括热耦合于所述金属块的半导体器件管芯，其中所述金属块包括铜。另一方面包括被放置在所述烧结银内的第二金属块，所述烧结银热电耦合所述金属块和所述第二金属块。在另一方面，所述第二材料部分包括被放置在所述烧结银区域内的无源电子器件，其中所述烧结银将所述无源电子器件电耦合于形成于所述印刷电路板上的互连。在另一方面，所述无源电子器件包括高电容材料。
本发明的另一个实施例提供了一种形成半导体器件封装的方法。所述方法包括：由第一材料形成所述半导体器件的第一材料部分，其中所述第一材料包括陶瓷或有机材料中的一个；提供所述半导体器件封装的第二材料部分，其中所述第二材料包括陶瓷或金属材料中的一个；使用烧结银区域粘接地耦合所述半导体器件封装的所述第一和第二材料部分。
在上述实施例的一方面，所述半导体器件封是气腔***，所述形成所述第一材料部分还包括形成陶瓷窗框，以及所述第二材料部分包括导电金属底板。在另一方面，所述半导体器件封是气腔***，所述形成所述第一材料部分还包括形成陶瓷窗框，以及所述第二材料部分包括导电金属引线。
在上述实施例的另一方面，所述粘接地耦合所述第一和第二材料部分还包括通过在比银的熔点低的形成温度应用细颗粒银形成烧结银区域。在另一方面，所述形成温度位于大约200℃和300℃之间。
在上述实施例的另一方面，所述形成所述第一材料部分还包括形成印刷电路板以及在所述印刷电路板内形成孔，以及所述粘接地耦合包括在所述印刷电路板内的所述孔内形成所述烧结银区域。另一方面包括将所述第二材料部分放置在所述烧结银区域内，其中所述第二材料部分是金属块。
由于实施本发明的装置大部分是由本领域所属技术人员所熟知的电子元件以及电路组成，电路的细节不会在比上述所说明的认为有必要的程度大的任何程度上进行解释。对本发明基本概念的理解以及认识是为了不混淆或偏离本发明所教之内容。
此外，在描述和权利要求中的术语“前面”、“后面”、“顶部”、“底部”、“上面”、“下面”等等，如果有的话，是用于描述性的目的并且不一定用于描述永久性的相对位置。应了解术语的这种用法在适当的情况下是可以互换的以便本发明所描述的实施例例如能够在其它方向而不是本发明所说明的或在其它方面进行操作。
虽然本发明的描述参照具体实施例，正如以下权利要求所记载的，在不脱离本发明范围的情况下，可以进行各种修改以及变化。例如，金属材料不是铜或可被用于各种封装。
因此，说明书以及附图被认为是说明性而不是限制性的，并且所有这些修改旨在包括在本发明范围内。关于具体实施例，本发明所描述的任何好处、优点或解决方案都不旨在被解释为任何或所有权利要求的关键的、必需的、或本质特征或元素。
本发明所用的术语“耦合”不旨在限定为直接耦合或机械耦合。
此外，本发明所用的“一”或“一个”被定义为一个或多个。并且，在权利要求中所用词语如“至少一个”以及“一个或多个”不应该被解释以暗示通过不定冠词“一”或“一个”引入的其它权利要求元素限定任何其它特定权利要求。所述特定权利要求包括这些所介绍的对发明的权利元素，所述权利元素不仅仅包括一个这样的元素。即使当同一权利要求中包括介绍性短语“一个或多个”或“至少一个”以及不定冠词，例如“一”或“一个”。使用定冠词也是如此。
除非另有说明，使用术语如“第一”以及“第二”是用于任意区分这些术语描述的元素的。因此，这些术语不一定表示时间或这些元素的其它优先次序。

Claims (10)

1.一种半导体器件封装，包括：
所述半导体器件封装的第一材料部分，其中第一材料包括陶瓷或有机材料中的一个；
所述半导体器件封装的第二材料部分，其中第二材料包括金属材料；以及
被放置为耦合所述半导体器件封装的所述第一和第二材料部分的烧结银区域；其中：
所述第一材料部分包括印刷电路板，以及
所述烧结银区域被放置在形成于所述印刷电路板内的孔内。
2.一种形成半导体器件封装的方法，其特征在于，包括：
由第一材料形成半导体器件封装的第一材料部分，其中第一材料包括陶瓷或有机材料中的一个；
提供半导体器件封装的第二材料部分，其中第二材料部分包括陶瓷或金属材料；以及
使用烧结银区域来粘性地将半导体器件封装的第一材料部分和第二材料部分相耦合。
3.如权利要求2所述的方法，其特征在于：
半导体器件封装包括气腔封装；
形成第一材料部分进一步包括形成陶瓷窗框；以及
第二材料部分包括导电金属底板或导电金属引线。
4.如权利要求2所述的方法，其特征在于：
形成第一材料部分进一步包括形成印刷电路板和在印刷电路板内形成孔；
所述粘性地耦合包括在印刷电路板内的孔中形成烧结银区域。
5.一种形成半导体器件封装的方法，其特征在于，包括：
在封装基板内形成孔；
将包括颗粒银的材料置于孔内；
在孔内放置金属币；以及
执行烧结过程以将包括颗粒银的材料转换为烧结银，其中烧结银将金属币耦合到封装基板。
6.一种形成半导体器件封装的方法，其特征在于，包括：
在底板的顶面和绝缘框架的底面之间施加包括颗粒银的材料；以及
执行烧结过程以将包括颗粒银的材料转换为烧结银，其中烧结银将绝缘框架的底面耦合到底板的顶面。
7.根据权利要求6所述的方法，其特征在于，进一步包括：
在绝缘框架的顶面和导电金属引线之间施加包括颗粒银的材料；以及
执行烧结过程以将包括颗粒银的材料转换为烧结银，其中烧结银将导电金属引线耦合到绝缘框架的顶面。
8.一种半导体器件，其特征在于，包括：
具有顶面和底面的绝缘框架；
具有顶面的基板，其具有接口区域；以及
在绝缘框架的底面和基板的顶面的接口区域之间的烧结银，其中烧结银将绝缘框架的底面直接耦合到基板的顶面。
9.如权利要求8所述的半导体器件，其特征在于，进一步包括：通过烧结银而耦合到绝缘框架的顶面的导电金属引线。
10.如权利要求9所述的半导体器件，其特征在于，进一步包括：
通过烧结银而耦合到基板的管芯连接区域的半导体器件管芯；
在半导体器件管芯和导电金属引线之间的电接触；以及
气腔盖，其中气腔盖耦合到绝缘框架的顶面和导电金属引线。
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