CN108776403B - 像素结构及触控面板 - Google Patents
像素结构及触控面板 Download PDFInfo
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Abstract
本发明公开了一种像素结构,包括扫描线、数据线、开关元件、平坦层、第一共通电极、共通线、第一绝缘层、像素电极、第二绝缘层以及第二共通电极。开关元件具有源极与漏极。共通线位于平坦层上且与第一共通电极直接接触。平坦层位于扫描线、数据线及开关元件上。像素电极藉由第一接触洞与漏极电性连接,其中第一接触洞贯穿平坦层与第一绝缘层。第二共通电极藉由第二接触洞与第一共通电极电性连接,其中第二接触洞贯穿第一绝缘层与第二绝缘层。一种触控面板亦被提出。
Description
技术领域
本发明是有关于一种像素结构及触控面板,且特别是有关于一种包括第一共通电极与第二共通电极的像素结构及触控面板。
背景技术
随着科技的进步,液晶显示面板的功率消耗被广泛地探讨。研究结果显示,当液晶显示面板降频操作时,以较低频的信号输出可以达到节能的效果。
然而,液晶显示面板于低频(例如小于60Hz)操作时,容易因像素结构的漏电,使一个画面(frame)中出现人眼可辨的亮度下降,而在下一个画面进行充电时,亮度又会明显提升,进而产生画面闪烁(flicker)现象。因此,目前急需一种能解决上述问题的方案。
发明内容
本发明的一实施例提供一种像素结构,能改善显示画面在低频时出现画面闪烁的问题。
本发明的一实施例提供一种触控面板,能改善显示画面在低频时出现画面闪烁的问题。
本发明的至少一实施例提供一种像素结构,包括扫描线、数据线、开关元件、平坦层、第一共通电极、共通线、第一绝缘层、像素电极、第二绝缘层以及第二共通电极。开关元件电性连接至扫描线及数据线。开关元件具有源极与漏极。平坦层位于扫描线、数据线及开关元件上。第一共通电极位于平坦层上。共通线位于平坦层上,且与第一共通电极直接接触。像素电极位于第一绝缘层上。像素电极藉由第一接触洞与漏极电性连接。第一接触洞贯穿平坦层与第一绝缘层。第二绝缘层位于像素电极上。第二共通电极位于该第二绝缘层上。第二共通电极藉由第二接触洞与第一共通电极电性连接。第二接触洞贯穿第一绝缘层与第二绝缘层。
本发明的至少一实施例提供一种触控面板,包括第一像素结构以及第二像素结构。第一像素结构以及第二像素结构分别包括扫描线、数据线、开关元件、平坦层、第一共通电极、共通线、第一绝缘层、像素电极、第二绝缘层以及第二共通电极。开关元件电性连接至扫描线及数据线。开关元件具有源极与漏极。平坦层位于扫描线、数据线及开关元件上。第一共通电极位于平坦层上。共通线位于平坦层上,且与第一共通电极直接接触。像素电极位于第一绝缘层上。像素电极藉由第一接触洞与漏极电性连接。第一接触洞贯穿平坦层与第一绝缘层。第二绝缘层位于像素电极上。第二共通电极位于该第二绝缘层上。第二共通电极藉由第二接触洞与第一共通电极电性连接。第二接触洞贯穿第一绝缘层与第二绝缘层。第一像素结构的共通线与第二像素结构的共通线彼此分离。
本发明的目的之一为改善像素结构在低频操作时出现画面闪烁的问题。
本发明的目的之一为提升像素结构的开口率。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附图式作详细说明如下。
附图说明
图1A是依照本发明一实施例的一种像素结构及其周围构件的上视示意图。
图1B是根据图1A的剖面线AA’绘示的像素结构的剖面示意图。
图1C是根据图1A的剖面线BB’绘示的像素结构的剖面示意图。
图2A是依照本发明一实施例的一种触控面板的部分元件的上视示意图。
图2B是依照本发明一实施例的一种触控面板的部分元件的上视示意图。
其中,附图标记:
10、P1、P2、P3、P4、P5、P6、P7、P8:像素结构
100:基底
110:缓冲层
120:栅极绝缘层
130:层间介电层
140:平坦层
150:第一绝缘层
160:第二绝缘层
AA’、BB’:剖面线
CE1、CE1’:第一共通电极
CE2:第二共通电极
CH:通道
CL、CL1、CL2:共通线
CP:连接部
D:漏极
DL:数据线
G:栅极
H:狭缝
N1、N2、N3、N4:角落
PE、PE’:像素电极
S:源极
SL:扫描线
SM:遮光层
T:开关元件
V1:第一接触洞
V2:第二接触洞
Vd、Vs:通孔
W、W1:宽度
具体实施方式
以下结合附图和具体实施例对本发明进行详细描述,但不作为对本发明的限定。
图1A是依照本发明一实施例的一种像素结构及其周围构件的上视示意图。图1B是根据图1A的剖面线AA’绘示的像素结构的剖面示意图。图1C是根据图1A的剖面线BB’绘示的像素结构的剖面示意图。
请参考图1A至图1C,像素结构10包括扫描线SL、数据线DL、开关元件T、平坦层140、第一共通电极CE1、共通线CL、第一绝缘层150、像素电极PE、第二绝缘层160以及第二共通电极CE2。在本实施例中,像素结构10还包括基板100、遮光层SM、缓冲层110、栅极绝缘层120、层间介电层130,但本发明不以此为限。在图1A中还绘示了三个第一共通电极CE1’以及三个像素电极PE’,其中第一共通电极CE1’以及像素电极PE’是属于相邻于像素结构10的其他像素结构的构件。缓冲层110位于基板100上,缓冲层110的材质举例包含绝缘材料。
开关元件T具有源极S、漏极D、栅极G以及通道CH。通道CH位于缓冲层110上。栅极G重叠于通道CH,且与通道CH之间夹有栅极绝缘层120。栅极G电性连接至扫描线SL。栅极G的材质为导电材料。举例而言,栅极G的材质例如包括铜(Copper,Cu)、钼(Molybdenum,Mo)、钛(Titanium,Ti)、铝(Aluminum,Al)、钨(Tungsten,W)、银(Silver,Ag)、金(Gold,Au)或上述金属的合金或上述材料的组合。栅极G可为单层结构或多层结构。在本实施例中,开关元件T为双栅极开关元件,即开关元件T包括两个栅极G,藉此能够减少漏电流的产生。然,本发明不限于此,根据其他实施例,开关元件T也可以是单栅极开关元件。
层间介电层130同时覆盖栅极绝缘层120以及栅极G。也就是说,栅极G位于层间介电层130与栅极绝缘层120之间。
漏极D与源极S位于层间介电层130上。通孔Vd位于层间介电层130与栅极绝缘层120中,且通孔Vs位于层间介电层130与栅极绝缘层120中。漏极D通过通孔Vd电性连接至通道CH,而源极S通过通孔Vs电性连接至通道CH。源极S与数据线DL电性连接。漏极D与像素电极PE电性连接。在一些实施例中,开关元件T与像素电极PE之间还包括其他驱动元件(未绘示),但本发明不以此为限。在本实施例中,开关元件T是以顶部栅极型薄膜晶体管为例来说明,但本发明不限于此。根据其他实施例,上述的开关元件T也可是以底部栅极型薄膜晶体管。
在本实施例中,开关元件T与基板100之间夹有遮光层SM。遮光层SM用于避免光线照射于开关元件T的通道CH而影响开关元件T中载子的正常运作,藉此防止漏电流的产生。遮光层SM的材料可以选自具有遮光效果的材料,例如包括金属、金属化合物(例如卤化银)、树脂或其他合适的材料。
扫描线SL与数据线DL彼此交错设置,且扫描线SL与数据线DL之间夹有层间介电层130。在本实施例中,是以扫描线SL的延伸方向与数据线DL的延伸方向不平行为例。扫描线SL与数据线DL一般是使用金属材料,然而本发明不限于此。在其他实施例中,扫描线SL与数据线DL也可以使用其他导电材料(例如:金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物或其它合适的材料)或是金属材料与其它导材料的堆叠层。
平坦层140位于扫描线SL、数据线DL及开关元件T上。平坦层140的材料包含无机材料(例如:氧化硅、氮化硅、氮氧化硅、其它合适的材料或上述至少二种材料的堆叠层)、有机材料(例如:聚酯类(PET)、聚烯类、聚丙酰类、聚碳酸酯类、聚环氧烷类、聚苯烯类、聚醚类、聚酮类、聚醇类、聚醛类或其它合适的材料、或上述的组合)或其它合适的材料或上述的组合。
第一共通电极CE1位于平坦层140上。第一共通电极CE1接触连接部CP的一角落N1。像素结构10周围的其他像素结构的第一共通电极CE1’则接触连接部CP的其他角落。连接部CP重叠于数据线DL的一部分。连接部CP例如是与第一共通电极CE1一体成形,例如由相同膜层图案化而成,连接部CP的角落接触第一共通电极CE1。
共通线CL位于平坦层140上,第一绝缘层150位于第一共通电极CE1与共通线CL上。共通线CL与第一共通电极CE1直接接触,举例来说,形成共通线CL于平坦层140上后,形成第一共通电极CE1于共通线CL上并与其直接接触,之后,再形成第一绝缘层150覆盖第一共通电极CE1以及共通线CL。在本实施例中,由于共通线CL与第一共通电极CE1并非藉由例如接触凸块或另外的通孔而使两者电性连接,因此能够避免像素结构10的开口率降低并提升像素结构10的制程良率。共通线CL藉由第一共通电极CE1电性连接于连接部CP。共通线CL的线宽为W,共通线CL被第一共通电极CE1覆盖的部分的宽度为W1,其中0<W1<W。第一共通电极CE1例如为覆盖共通线CL的侧壁及部分上表面。在本实施例中,共通线CL以及第一共通电极CE1中的至少一者重叠于数据线DL。举例来说,共通线CL以及第一共通电极CE1皆重叠于数据线DL,但本发明不以此为限。
像素电极PE位于第一绝缘层150上。像素电极PE与第一共通电极CE1之间夹有第一绝缘层150。第一接触洞V1贯穿平坦层140与第一绝缘层150。像素电极PE藉由第一接触洞V1与漏极D电性连接。在本实施例中,像素电极PE与数据线DL之间隔有第一共通电极CE1,可以减少像素电极PE与数据线DL之间的寄生电容,以改善像素结构在低频操作时显示装置出现画面闪烁的问题。
第二绝缘层160位于像素电极PE与第一绝缘层150上。
第二共通电极CE2位于第二绝缘层160上。第二共通电极CE2与像素电极PE之间夹有第二绝缘层160。第二接触洞V2贯穿第一绝缘层150与第二绝缘层160。第二共通电极CE2藉由第二接触洞V2与连接部CP电性连接,并藉由连接部CP而与第一共通电极CE1电性连接。在本实施例中,第二共通电极CE2与第二接触洞V2皆重叠于数据线DL,藉此降低第二接触洞V2对像素结构10的开口率的影响,但本发明不以此为限。在本实施例中,第二共通电极CE2不与第一接触洞V1以及通孔Vd重叠,但本发明不以此为限。第二共通电极CE2具有多条狭缝H,且狭缝H重叠于像素电极PE以及第一共通电极CE1。在本实施例中,藉由设置于像素电极PE上方及下方的第二共通电极CE2与第一共通电极CE1,可以使像素结构10具有较大的有效面积,进一步地具有较大的储存电容,以改善像素结构在低频操作时显示装置出现画面闪烁的问题。举例来说,假设以15Hz的低频操作本实施例的像素结构10,显示第N个画面(frame)时,因具有足够大的储存电容,故此画面亮度下降的速度及幅度能控制的较小,而在进行下一个画面,即第N+1个画面进行充电以显示时,在第N+1个画面及第N个画面间的亮度差异便较不明显,藉此以减少或避免人眼感受到的画面闪烁(flicker)现象。
在本发明的至少一实施例中,可以减少像素电极上的寄生电容并提升储存电容,进而改善像素结构在低频操作时显示装置出现画面闪烁的问题。
图2A是依照本发明一实施例的一种触控面板的部分元件的上视示意图。图2B是依照本发明一实施例的一种触控面板的部分元件的上视示意图。在此必须说明的是,图2A与图2B的实施例沿用图1A至图1C的实施例的元件标号与部分内容,其中采用相同或近似的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,下述实施例不再重复赘述。
请参考图2A及图2B,为了方便说明,图2A绘示出像素结构P1~P8中的第一共通电极CE1以及第二共通电极CE2、连接部CP、共通线CL1以及共通线CL2,并省略绘示其他构件。图2B绘示出像素结构P1~P8的扫描线SL、数据线DL、像素电极PE以及第二共通电极CE2,并省略绘示其他构件。
请同时参考图2A及图2B,本实施例的触控面板至少包括像素结构P7以及像素结构P1。在一些实施例中,触控面板还包括像素结构P2~P6、P8。多条扫描线SL与多条数据线DL彼此交错,像素结构P1~P8的结构相似于图1A~图1C的实施例中的像素结构10。
像素结构P1~P6的第一共通电极CE1藉由连接部CP彼此电性连接。像素结构P7~P8的第一共通电极CE1藉由连接部CP彼此电性连接。请同时参考图1A,连接部CP具有角落N1、N2、N3、N4。连接部CP的角落N1、N2、N3、N4分别连接相邻近的四个像素结构中的第一共通电极CE1。在本实施例中,连接部CP的两个角落N2、N1分别连接同一列的像素结构P1的第一共通电极CE1以及像素结构P4的第一共通电极CE1,另外两个角落N3、N4分别连接另一列的像素结构P2的第一共通电极CE1以及像素结构P5的第一共通电极CE1。在本实施例中,多个连接部CP被设置,单一个连接部CP对应4个相邻近的四个像素结构且以其4个角落N1、N2、N3、N4分别电性连接于此4个相邻近的四个像素结构,但不以此为限。在本实施例中,单一个第一共通电极CE1对应4个连接部CP,举例来说,单一个第一共通电极CE1接触于4个连接部CP的角落,但不以此为限。在本实施例中,连接部CP举例分别重叠于扫描线SL和数据线DL的相交处,但不以此为限。
在本实施例中,像素结构P1、P4包括共通线CL1,像素结构P7、P8包括共通线CL2。在本实施例中,像素结构P2、P3、P5、P6不包括共通线,且像素结构P2、P3、P5、P6通过像素结构P1、P4的第一共通电极CE1而电性连接至共通线CL1,但本发明不以此为限。在一些实施例中,像素结构P2、P3、P5、P6包括其他条共通线CL1。像素结构P7、P8的第一共通电极CE1电性连接至共通线CL2。
在本实施例中,像素结构P7中的共通线CL2与像素结构P1中的共通线CL1彼此分离。
在本实施例中,像素结构P4相邻于像素结构P1。像素结构P4的共通线CL1与像素结构P1的共通线CL1直接连接。
在本实施例中,由于共通线CL1与共通线CL2之间互相分离,像素结构P1~P6中的第一共通电极CE1与第二共通电极CE2以及像素结构P7~P8中的第一共通电极CE1与第二共通电极CE2可做为触控电极。在本实施例中,共通线CL1或共通线CL2可选用不易因受热而变质的导电材料,例如:铝、钛、钼、镁、钕、银、其他适当材料或上述至少二者的组合。此外,共通线CL1或共通线CL2亦可以选择低反射金属(例如:黑化金属层)来提升光学表现。在各实施例中,第一共通电极CE1、第二共通电极CE2、连接部CP及像素电极PE的材质举例为透明导电材料,例如氧化铟锡或氧化铟锌。
本发明的至少一实施例中,可以减少像素电极上的寄生电容并能提升储存电容,进而改善触控面板在低频操作时出现画面闪烁的问题。
综上所述,本发明的像素结构及触控面板,藉由第一共通电极与共通线直接接触、像素电极与数据线之间隔有第一共通电极以及第二共通电极与像素电极为不同层的结构,可以减少寄生电容以及提升储存电容,进而改善像素结构及触控面板在低频操作时出现画面闪烁的问题。
虽然本发明已以实施例揭露如上,然其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,故本发明的保护范围当视后附的申请专利范围所界定者为准。
Claims (10)
1.一种像素结构,其特征在于,包括:
一扫描线及一数据线;
一开关元件,电性连接至该扫描线及该数据线,该开关元件具有一源极与一漏极;
一平坦层,位于该扫描线、该数据线及该开关元件上;
一第一共通电极,位于该平坦层上;
一共通线,位于该平坦层上,且与该第一共通电极直接接触;
一第一绝缘层,位于该第一共通电极与该共通线上;
一像素电极,位于该第一绝缘层上,且藉由一第一接触洞与该漏极电性连接,其中该第一接触洞贯穿该平坦层与该第一绝缘层;
一第二绝缘层,位于该像素电极上;以及
一第二共通电极,位于该第二绝缘层上,且藉由一第二接触洞与该第一共通电极电性连接,其中该第二接触洞贯穿该第一绝缘层与该第二绝缘层;
该第二共通电极具有多条狭缝,该些狭缝重叠于该像素电极以及该第一共通电极,该第一共通电极接触一连接部的一角落,且该连接部重叠于该数据线的一部分,其中该第二共通电极藉由该第二接触洞与该连接部电性连接,该连接部被4个像素结构包围并位于两相邻共通线之间,其中该连接部的4角落分别对应该4个像素结构的不同角落。
2.如权利要求1所述的像素结构,其特征在于,该共通线的线宽为W,该共通线被该第一共通电极覆盖的部分的宽度为W1,其中0<W1<W。
3.如权利要求1所述的像素结构,其特征在于,该第二共通电极重叠于该数据线。
4.如权利要求1所述的像素结构,其特征在于,该第二接触洞重叠于该数据线。
5.如权利要求1所述的像素结构,其特征在于,该共通线以及该第一共通电极中的至少一者重叠于该数据线。
6.如权利要求1所述的像素结构,其特征在于,该共通线藉由该第一共通电极电性连接该连接部。
7.如权利要求1所述的像素结构,其特征在于,该第二共通电极不与该第一接触洞重叠。
8.一种触控面板,其特征在于,包括:
一第一像素结构如权利要求1所述;以及
一第二像素结构如权利要求1所述,其中该第一像素结构的共通线与该第二像素结构的共通线彼此分离。
9.如权利要求8所述的触控面板,其特征在于,更包括一第三像素结构如权利要1所述,其中该第三像素结构相邻于该第二像素结构,且该第三像素结构的共通线与该第二像素结构的共通线直接连接。
10.如权利要求9所述的触控面板,其特征在于,
其中该连接部的两个角落分别连接该第二像素结构的第一共通电极以及该第三像素结构的第一共通电极。
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