CN108768395A - A kind of gain mismatch errors for multichannel ADC calibrate circuit - Google Patents
A kind of gain mismatch errors for multichannel ADC calibrate circuit Download PDFInfo
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- CN108768395A CN108768395A CN201810585157.3A CN201810585157A CN108768395A CN 108768395 A CN108768395 A CN 108768395A CN 201810585157 A CN201810585157 A CN 201810585157A CN 108768395 A CN108768395 A CN 108768395A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/1019—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error by storing a corrected or correction value in a digital look-up table
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Abstract
The present invention provides a kind of gain mismatch errors for multichannel ADC to calibrate circuit, belongs to technical field of integrated circuits.The gain mismatch errors calibration circuit for multichannel ADC includes reference voltage generating circuit, reference voltage remote driver circuit, M reference voltage regulating circuit, the positions the N analog-digital converter in the channels M, M N output registers, calibration reference signal generation circuit, N bit digitals subtraction circuit and control circuit.The gain mismatch errors calibration circuit for being used for multichannel ADC can be according to system accuracy and the automatic compromise selection calibration accuracy of hardware spending, and has the characteristics that low-power consumption.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of gain mismatch errors school for multichannel ADC
Quasi- circuit.
Background technology
Precision 14, sampling rate are more than the pipeline ADC of 100MSPS（Analog-digital converter）, it is always that all kinds of intermediate frequencies are adopted
The main selection of sample system, thus applied to the electronic applications such as multi-carrier broadband wireless communication and radar reception on a large scale
In.To reduce cost and improving reliability, all kinds of electronic systems become increasingly conspicuous for the demand of low-power consumption and miniaturization, to institute
It is increasingly strict using the power consumption and area requirements of adc circuit.To improve the integrated level of pipeline ADC, generally use single-chip collection
At the mode of multichannel adc circuit come occupied space when reducing board level system design.To realize the more of pipeline ADC circuit
Channel is integrated, and used single channel pipeline ADC kernel circuitry must have some special requirement：First, the ADC kernels
Must have low-power consumption and small area characteristic, otherwise, the power consumption and integrity problem that multichannel integrated belt comes are by very big restriction plate
Grade system application；Secondly, which must use output port number as few as possible, and otherwise, the encapsulation brought after integrated is asked
The wiring problem of the HW High Way of topic and board level system can bring very big limitation.
In addition to this, when multichannel ADC is when same chips are integrated, due to the device parameters between different chip areas
There are mismatches, and the gain between multichannel ADC is caused matching error occur.Especially for High Speed High Precision ADC, different channels
Gain between ADC, which mismatches, influences meeting clearly, and this mismatch error is asynchronous to communicate radar and channel wireless radio multi
Etc. system performances have bigger influence.Therefore certain bearing calibration is needed to be removed such gain mismatch errors.Therefore
Design can carry out self-alignment circuit to the gain mismatch errors between multichannel ADC realistic meaning very much.
Invention content
The purpose of the present invention is to provide a kind of gain mismatch errors for multichannel ADC to calibrate circuit, existing to solve
The unmatched problem of gain between the different channel ADC having.
In order to solve the above technical problems, the present invention provides a kind of gain mismatch errors calibration circuit for multichannel ADC,
Including：Reference voltage generating circuit, reference voltage remote driver circuit, M reference voltage regulating circuit, the channels M the positions N modulus
Converter, M N output registers, calibration reference signal generation circuit, N bit digitals subtraction circuit and control circuit；It is each
Reference voltage regulating circuit, the N position analog-digital converters in each channel and each N output register are corresponding one by one；
Wherein, reference voltage generating circuit generates a reference voltage and is input to reference voltage remote driver circuit；Reference voltage
The roads the M output reference voltage of remote driver circuit is connected respectively to the reference voltage input of M reference voltage regulating circuit, the
The roads M+1 output reference voltage Vrinref is connected to the reference voltage input of calibration reference signal generation circuit；Control circuit
M control signal of M control signal output output is separately connected the control signal input of M reference voltage regulating circuit
The positions the K 1 ~ M of compensation codes at end, the M K compensation codes output ends output of control circuit is separately connected M reference voltage regulating circuit
Compensation codes input terminal；The reference voltage output end of reference voltage regulating circuit connects corresponding N analog-digital converter, calibration
The positions the N analog-digital converter in the channels calibration voltage signal output end Vr_cal connection M of reference signal generation circuit；N moduluses turn
The N digit numeric codes of parallel operation output obtain quantization code after corresponding N output register；The M+1 of N bit digital subtraction circuits
Group digital code input terminal is connected respectively to M N output register and calibrates the benchmark output quantization of reference signal generation circuit
Code output end Dref；The control signal of calibration reference signal generation circuit is connected to the positions the K option code output end of control circuit
Mouthful；The positions the K quantization code output end of N bit digital subtraction circuits is connected to the error input port of control circuit；The school of control circuit
Quasi- control signal Ctrl_mode output ports are connected to N bit digitals subtraction circuit and calibrate the calibration of reference signal generation circuit
Control signal input mouth；The input of the positions the K global adaptation code output end connection reference voltage remote driver circuit of control circuit
End；
Wherein, N and M is arbitrary positive integer, and K is the positive integer no more than N.
Optionally, the gain mismatch errors calibration circuit for multichannel ADC includes calibration mode and compensation model；
When entering calibration mode, the gain mismatch errors for multichannel ADC calibrate circuit successively to the positions N in the channels M
Analog-digital converter carries out gain mismatch errors calibration, is sequentially generated K compensation codes of M groups；When entering compensation model, K benefits of M groups
It repays code to remain unchanged, the gain mismatch errors calibration circuit N position digital-to-analogue conversions to the channels M simultaneously for multichannel ADC
Device carries out gain mismatch errors compensation, and the calibration reference signal generation circuit and N bit digital subtraction circuits are turned off to reduce
Power consumption.
Optionally, the reference voltage remote driver circuit includes：One reference voltage programming adjustment circuit and M+1 electricity
Press remote driver circuit；The output end of reference voltage programming adjustment circuit connects M+1 voltage remote driver circuit simultaneously；Benchmark
The output voltage of voltage-programming adjustment circuit is controlled by K global adaptation codes.
Optionally, the calibration reference signal generation circuit includes：One programmable calibration voltage generation circuit and benchmark
Output quantization code generation circuit；
The reference voltage input terminal of the programmable calibration voltage generation circuit is connected to the M of reference voltage remote driver circuit
+ 1 road output reference voltage Vrinref, programmable calibration voltage generation circuit export calibration benchmark under the control of K option codes
Voltage；Benchmark output quantization code generation circuit output reference output quantization code under the control of K option codes.
Optionally, the benchmark output quantization code generation circuit only works in the calibration mode, including by Ctrl_mode
ROM look-up tables, ROM module and the benchmark quantization code output circuit of signal control；K option codes enter ROM look-up tables, obtain phase
To ROM module, appropriate address is corresponded to the benchmark quantization code data output stored in memory cell by ROM module for the address answered
Give benchmark quantization code output circuit, benchmark quantization code output circuit output reference output quantization code.
Optionally, the control circuit includes：Core control circuit, option code generation circuit, adjustment code generation circuit, fortune
Calculate circuit, K bit registers group, compensation codes output register 1~compensation codes output register M and channel selection circuit；
Wherein, the input terminal of core control circuit connects calibration activation information, and the first output end connection of core control circuit is logical
The control signal of road selection circuit, second output terminal connect the control signal of computing circuit, the connection selection of third output end
The control signal of code generation circuit, the control signal of the 4th output end connection adjustment code generation circuit, the 5th output end connect
Meet the control signal of K bit register groups, M calibration control signal Ctrl1~Ctrl M that the six~the M+5 output ends generate
It is separately connected compensation codes output register 1~compensation codes output register M；The data input pin of computing circuit receives K deposits
The data that device group output end is sent, and K error codes are generated according to the control instruction of core control circuit；Compensation codes output deposit
The data input pin of device 1~compensation codes output register M is all connected to the positions the K error codes output end of computing circuit, compensation codes
The 1st~the M data that the output end of output register 1~compensation codes output register M is connected respectively to channel selection circuit is defeated
Enter end；Channel selection circuit exports K 1 ~ M of compensation codes according to the control instruction of core control circuit；Option code generation circuit root
K option codes are generated according to the control instruction of core control circuit；Adjustment code generation circuit refers to according to the control of core control circuit
It enables and generates K global adaptation codes；The data input pin of K bit register groups receives the output end hair of the N bit digitals subtraction circuit
The positions the K quantization code sent, and be sent to the data being stored in its internal register according to the control instruction of core control circuit
Computing circuit.
Optionally, calibration control signal Ctrl1~Ctrl M in the calibration mode, any time only one
Signal is effective；During the positions the N analog-digital converter to the channels M is calibrated, the channel selection circuit will be calibrated
The corresponding compensation codes output register of the positions N analog-digital converter output open, the output quilt of remaining compensation codes output register
It closes.
Optionally, the computing circuit generates K error codes using two points of successive approximation algorithms, and each operation only changes K
1 in the error codes of position；The positions the K error codes that final output remains unchanged need loop computation just to can determine that for K times.
A kind of gain mismatch errors calibration circuit for multichannel ADC is provided in the present invention, including：Reference voltage
Generation circuit, reference voltage remote driver circuit, M reference voltage regulating circuit, the positions the N analog-digital converter in the channels M, M N
Output register, calibration reference signal generation circuit, N bit digitals subtraction circuit and control circuit.This is for multichannel ADC's
Gain mismatch errors calibrate circuit can be according to system accuracy and the automatic compromise selection calibration accuracy of hardware spending, and has low
Power consumption feature.
Description of the drawings
Fig. 1 is the structural schematic diagram that circuit is calibrated for the gain mismatch errors of multichannel ADC；
Fig. 2 is the structural schematic diagram of reference voltage remote driver circuit；
Fig. 3 is the structural schematic diagram of reference voltage programming adjustment circuit；
Fig. 4 is the structural schematic diagram for calibrating reference signal generation circuit；
Fig. 5 is the structural schematic diagram of benchmark output quantization code generation circuit；
Fig. 6 is the structural schematic diagram of control circuit.
Specific implementation mode
Below in conjunction with the drawings and specific embodiments to a kind of gain mismatch errors for multichannel ADC proposed by the present invention
Calibration circuit is described in further detail.According to following explanation and claims, advantages and features of the invention will become apparent from.
It should be noted that attached drawing is all made of very simplified form and uses non-accurate ratio, only to it is convenient, lucidly assist
Illustrate the purpose of the embodiment of the present invention.
Embodiment one
The present invention provides a kind of gain mismatch errors for multichannel ADC to calibrate circuit, as shown in Figure 1.It is described for more
The gain mismatch errors of channel ADC calibrate circuit：Reference voltage generating circuit, reference voltage remote driver circuit, M base
Quasi- voltage-regulating circuit, the positions the N analog-digital converter in the channels M, M N output registers, calibration reference signal generation circuit, N
Digital subtraction circuit and control circuit.Wherein, M reference voltage regulating circuit is respectively reference voltage regulating circuit 1, benchmark
Voltage-regulating circuit 2 ..., the positions the N analog-digital converter in the channels reference voltage regulating circuit M, M be respectively N analog-digital converters 1,
N analog-digital converters 2 ..., N analog-digital converter M, M N output registers be respectively N output registers 1, N it is defeated
Go out register 2 ..., N output register M.Each reference voltage regulating circuit, the N position analog-digital converters in each channel and each
A N output register is corresponding one by one.Specifically, reference voltage regulating circuit 1, N analog-digital converter 1 and N outputs are posted
Storage 1 is sequentially connected, reference voltage regulating circuit 2, N analog-digital converter 2 and N output registers 2 are sequentially connected ..., base
Quasi- M and N output register M of voltage-regulating circuit M, N analog-digital converters are sequentially connected.
Wherein, reference voltage generating circuit generates a reference voltage and is input to reference voltage remote driver circuit；Benchmark
The roads the M output reference voltage of voltage remote driver circuit is connected respectively to the reference voltage input of M reference voltage regulating circuit
End：Reference voltage V rin1 connections reference voltage regulating circuit 1, reference voltage V rin2 connections reference voltage regulating circuit 2 ...,
Reference voltage V rin M connection reference voltage regulating circuits M；The roads the M+1 output reference voltage of reference voltage remote driver circuit
Vrinref is connected to the reference voltage input of calibration reference signal generation circuit.M control signal output of control circuit
M control signal Ctrl1 ~ M of output is separately connected the control signal input of M reference voltage regulating circuit：Control signal
The control signal input of Ctrl1 connections reference voltage regulating circuit 1, control signal Ctrl2 connections reference voltage regulating circuit 2
Control signal input ..., control signal Ctrl M connection reference voltage regulating circuits M control signal input.Control
The positions K 1 ~ M of compensation codes of the M K compensation codes output ends output of circuit is separately connected the compensation codes of M reference voltage regulating circuit
Input terminal.The reference voltage output end of each reference voltage regulating circuit connects corresponding N analog-digital converter, calibrates benchmark
The calibration voltage signal Vr_cal of the calibration voltage signal output end output of signal generating circuit is transported to the positions the N modulus in the channels M
Converter；The N digit numeric codes of the positions the N analog-digital converter output in each channel amount of obtaining after corresponding N output register
Change code；The M+1 group digital code input terminals of N bit digital subtraction circuits are connected respectively to M N output register and calibration benchmark letter
The benchmark output quantization code output end of number generation circuit.Specifically, the D1 input terminals of N bit digital subtraction circuits connect N outputs
The benchmark output quantization code output end of register 1, the D1 input terminals of N bit digital subtraction circuits connect the defeated of N output registers 1
The D2 input terminals of outlet D1, N bit digital subtraction circuit connect output end D2 ..., N the bit digital subtraction of N output registers 2
The Dref input terminals that the DM input terminals of circuit connect output end DM, N the bit digital subtraction circuit of N output register M connect school
The output end Dref of quasi- reference signal generation circuit.The control signal of calibration reference signal generation circuit is connected to control circuit
The positions K option code output port；The positions the K quantization code output end of N bit digital subtraction circuits is connected to the error input of control circuit
Port；The calibration control signal Ctrl_mode output ports of control circuit are connected to N bit digitals subtraction circuit and calibration base simultaneously
The calibration control signal input mouth of calibration signal generation circuit；The positions the K global adaptation code output end connection benchmark electricity of control circuit
Press the input terminal of remote driver circuit.Also, N and M are arbitrary positive integer, and K is the positive integer no more than N.
The gain mismatch errors calibration circuit for multichannel ADC includes calibration mode and compensation model；Entering
When calibration mode, the gain mismatch errors for multichannel ADC calibrate circuit successively to the positions the N analog-digital converter in the channels M
Gain mismatch errors calibration is carried out, K compensation codes of M groups are sequentially generated；When entering compensation model, K compensation codes of M groups are kept not
Become, the gain mismatch errors calibration circuit for multichannel ADC carries out gain to the N digit mode converters in the channels M simultaneously
Mismatch error compensates, and the calibration reference signal generation circuit and N bit digital subtraction circuits are turned off to reduce power consumption.
The operation principle of foregoing circuit is：When calibration mode is opened, control circuit is controlled first by Ctrl_mode signals
N bit digitals subtraction circuit processed and calibration reference signal generation circuit enter calibration mode, while the control circuit exports K choosings
Code is selected to the calibration reference signal generation circuit；In addition, first calibration of control circuit output controls signal Ctrl1 to base
Quasi- voltage-regulating circuit 1 controls the reference voltage regulating circuit 1 and enters calibration mode, starts to N analog-digital converter circuits 1
Carry out gain mismatch errors calibration.Then control circuit generates first group of K option code；First group of K option code enters calibration
Reference signal generation circuit simultaneously generates first group of benchmark output quantization code Dref (1) and the first calibration reference voltage V r_cal
(1)；Analog input signals of the first calibration reference voltage V r_cal (1) as N analog-digital converters 1, makes the N modulus turn
Parallel operation 1 carries out normal analog-to-digital conversion work, carries out the gain mismatch errors calibration under the 1st kind of calibration reference voltage first.
Control circuit continues to generate first group of K 1 cali of compensation codes (1), into reference voltage regulating circuit 1 and obtains
The reference data voltage of first passage reference voltage V r1, the first passage reference voltage V r1 as N analog-digital converters 1,
First group of first output quantization code D1 is obtained by the analog-to-digital conversion of N analog-digital converters 1（1）；N bit digitals subtraction circuit is by
One group of first output quantization code D1（1）Subtraction process, which is carried out, with first group of benchmark output quantization code Dref (1) obtains first group K
Quantization code and input control circuit；Control circuit, which will receive, obtains the K bit registers of first group of K quantization codes storage inside it
In group；Control circuit can generate second group of K 1 cali of compensation codes according to first group of K quantization code using binary chop
(2)；
And then, second group of K compensation codes 1cali (2) enters reference voltage regulating circuit 1 and obtains newer reference voltage
Vr1 obtains second group of first output quantization code D1 through N 1 analog-to-digital conversions of analog-digital converter（2）；N bit digitals subtraction circuit will more
Second group of first new output quantization code D1（2）Subtraction process, which is carried out, with first group of benchmark output quantization code Dref (1) obtains the
Two groups of K quantization codes and input control circuit；Control circuit can be generated according to second group of K quantization code using binary chop
K 1 cali of compensation codes (3) of third group.
It recycles successively, N bit digital subtraction circuits will continue to generate K quantization codes of L groups, and control circuit can be looked into using two points
Method is looked for generate K 1 cali of compensation codes (L+1) of L+1 groups.After control circuit generates K compensation codes 1 cali (K) of K groups,
K 1 cali of compensation codes (K) of K groups can be stored in new register and be named as K 1 cali of compensation codes (K) _ R1 by control circuit,
Terminate the gain mismatch errors calibration under the 1st kind of calibration reference voltage.
Then control circuit generates K option codes of Y groups；K option codes of Y groups enter calibration reference signal generation circuit
And generate Y group benchmark output quantization code Dref (Y) and Y calibration reference voltage V r_cal (Y)；Y calibrates reference voltage
Analog input signals of the Vr_cal (Y) as N analog-digital converters 1, the gain mismatch carried out under Y kind calibration reference voltages miss
Difference calibration；The gain mismatch errors calibration circuit for multichannel ADC will use and the 1st kind of calibration reference voltage under
Gain mismatch errors calibrate identical mode and obtain K 1 cali of compensation codes (K) _ RY, terminate under Y kind calibration reference voltages
Gain mismatch errors are calibrated.It recycles successively, when the gain mismatch errors calibration circuit for multichannel ADC obtains last
K 1 cali of compensation codes (K) _ RZ of group, after terminating the gain mismatch errors calibration under Z kind calibration reference voltages, control circuit
In algorithm circuit will carry out operation to obtained K 1 cali of compensation codes (K) of Z groups _ R1~cali (K) _ RZ, obtain final
1 cali_fin of the positions K compensation codes and remain unchanged, the gain mismatch errors calibration circuit for multichannel ADC terminates N
The gain mismatch errors calibration of position analog-digital converter circuit 1.
And then, control circuit output X calibration control signal Ctrl X are electric to reference voltage regulating circuit X control benchmark
Pressure adjustment circuit X enters calibration mode, proceeds by the gain mismatch errors calibration of N analog-digital converter circuit X.It is described to be used for
The gain mismatch errors calibration circuit of multichannel ADC uses and N 1 identical calibration processes of analog-digital converter circuit obtain K
Compensation codes X cali_fin are simultaneously remained unchanged, and terminate the gain mismatch errors calibration of N analog-digital converter circuit X.According to same
Calibrating mode, when control circuit output M calibration control signal Ctrl M to reference voltage regulating circuit M, obtain K compensate
Code M cali_fin are simultaneously remained unchanged, described for more after the gain mismatch errors calibration for terminating N analog-digital converter circuit M
The calibration mode of the gain mismatch errors calibration circuit of channel ADC terminates.
The gain mismatch errors calibration circuit for multichannel ADC initially enters compensation model, and control circuit can be by M
A reference voltage regulating circuit is arranged to compensate for pattern simultaneously, starts the clock reference voltage to the N digit mode converters in the channels M
Mismatch error compensates.Finally, control circuit closes calibration reference signal generation circuit and N bit digital subtraction circuits, with drop
Low-power consumption.
In above description, N and M are arbitrary positive integer, and K is the positive integer no more than N, and X is the positive integer no more than M, L
For the positive integer no more than K, Z is no more than 2K- 1 positive integer, Y are the positive integer no more than Z.
It is illustrated in figure 2 the structural schematic diagram of reference voltage remote driver circuit.The reference voltage remote driver circuit
Including：One reference voltage programming adjustment circuit and M+1 voltage remote driver circuit.Reference voltage programs the defeated of adjustment circuit
Outlet connects M+1 voltage remote driver circuit simultaneously.M+1 voltage remote driver circuit is respectively voltage remote driver circuit
1, voltage remote driver circuit 2 ..., voltage remote driver circuit M and voltage remote driver circuit ref.Voltage remote boot server electricity
Road 1 generates reference voltage V rin1, and voltage remote driver circuit 2 generates reference voltage V rin2 ..., voltage remote driver circuit M
Reference voltage V rin M are generated, voltage remote driver circuit ref generates reference voltage V rinref.Bandgap voltage reference enters institute
Reference voltage programming adjustment circuit is stated, and the output voltage of reference voltage programming adjustment circuit is controlled by K global adaptation codes.
Specifically, on the basis of Fig. 3 voltage-programming adjustment circuit a kind of realization method, structure be digital control type LDO
Circuit.When control signal is set to 0, PMOS tube M31 conductings, due to the negative feedback of operational amplifier, reference voltageV REFIt is adjusting
Under the control of NMOS tube M30 an initial voltage output is obtained through electric resistance partial pressureV R(0), while current mode K-bit DAC can also
Generate one to ground adjustment electric current Ic, adjustment electric current Ic flow through least significant end resistance R32 to, thus can be in resistance R32
Upper Yi ⊿ of superpositionVThe voltage of=Ic × R32 is output to the voltage of reference signal output circuitV Rout=V R(0)+⊿V.Root
According to electric resistance partial pressure relationship, output reference voltage signalV RoutVariation can correspondingly be generated.Therefore, as long as K global adaptations of control
Code can realize the purpose for changing output reference voltage.All reference voltage regulating circuits can be used in the embodiment of the present invention
Circuit structure shown in Fig. 3.For M+1 voltage remote driver circuit, voltage follower realization may be used.
The calibration reference signal generation circuit includes：One programmable calibration voltage generation circuit and benchmark output quantization
Code generation circuit, as shown in Figure 4.The reference voltage input terminal of the programmable calibration voltage generation circuit is connected to reference voltage
The roads the M+1 output reference voltage Vrinref of remote driver circuit may be programmed calibration voltage generation circuit in K option codes
The lower output calibration reference voltage V r_cal of control；Benchmark output quantization code generation circuit exports base under the control of K option codes
Quasi- output quantization code Dref.
The structural schematic diagram of output quantization code generation circuit on the basis of Fig. 5, the benchmark output quantization code generation circuit is only
It works, including is exported by the ROM look-up tables, ROM module and benchmark quantization code of the control of Ctrl_mode signals in the calibration mode
Circuit.K option codes enter ROM look-up tables, obtain corresponding address to ROM module, appropriate address is corresponded to and stored by ROM module
The benchmark quantization code data stored in device unit, which export, gives benchmark quantization code output circuit, the output of benchmark quantization code output circuit
Benchmark output quantization code Dref.
Referring to Fig. 6, the control circuit includes：Core control circuit, option code generation circuit, adjustment code generate electricity
Road, computing circuit, K bit registers group, compensation codes output register 1~compensation codes output register M and channel selection circuit.
Wherein, the input terminal of core control circuit connects calibration activation information, and the first output end of core control circuit connects
The control signal of channel selection circuit is connect, second output terminal connects the control signal of computing circuit, the connection of third output end
The control signal of option code generation circuit, the control signal of the 4th output end connection adjustment code generation circuit, the 5th output
The control signal of end connection K bit register groups, the M calibration control signal Ctrl1 that the six~the M+5 output ends generate~
Ctrl M are separately connected compensation codes output register 1~compensation codes output register M.Specifically, calibration control signal Ctrl1 connects
Connect compensation codes output register 1, calibration control signal Ctrl2 connection compensation codes output register 2 ..., calibration control signal
Ctrl M connection compensation codes output registers M；The data input pin of computing circuit receives the number that K bit register group output ends are sent
According to, and K error codes are generated according to the control instruction of core control circuit；The output of compensation codes 1~compensation codes of output register is posted
The data input pin of storage M is all connected to the positions the K error codes output end of computing circuit, compensation codes output register 1~compensation
The output end of code output register M is connected respectively to the 1st~the M data input terminal of channel selection circuit；Channel selection circuit
According to the control instruction of core control circuit export K compensation codes 1, K compensation codes 2 ... K compensation codes M.Option code generates
Circuit generates K option codes according to the control instruction of core control circuit；Code generation circuit is adjusted according to core control circuit
Control instruction generates K global adaptation codes；The data input pin of K bit register groups receives the defeated of the N bit digitals subtraction circuit
The positions the K quantization code that outlet is sent, and the data in its internal register will be stored according to the control instruction of core control circuit
It is sent to computing circuit.
In the calibration mode, any time, only one signal had calibration control signal Ctrl1~Ctrl M
Effect；During the positions the N analog-digital converter to the channels M is calibrated, the channel selection circuit is by the positions the N calibrated mould
The output of the corresponding compensation codes output register of number converter is opened, and the output of remaining compensation codes output register is closed.
The computing circuit generates K error codes using two points of successive approximation algorithms, and each operation only changes K error codes
In 1；The positions the K error codes that final output remains unchanged need loop computation just to can determine that for K times.Specifically, being calibrated to Y kinds
In gain mismatch errors calibration process under reference voltage, K error codes need loop computation that could generate a K benefits for K times
Repay yard X cali (K) _ RY；To in the gain mismatch errors calibration process of the N analog-digital converter circuit X, due to needing to Z
Kind calibration reference voltage is calibrated, therefore K error codes need loop computation K*Z times just and can obtain K compensation codes X cali_
Fin is simultaneously remained unchanged；To in the gain mismatch errors calibration process of the positions the N analog-digital converter circuit in all channels M, K
Error codes, which need loop computation K*Z*M times just, can obtain K compensation codes X cali_fin of M groups and remain unchanged, to terminate
State the calibration mode that circuit is calibrated for the gain mismatch errors of multichannel ADC.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (8)
1. a kind of gain mismatch errors for multichannel ADC calibrate circuit, which is characterized in that including：Reference voltage generates electricity
Road, reference voltage remote driver circuit, M reference voltage regulating circuit, the positions the N analog-digital converter in the channels M, M N outputs are posted
Storage, calibration reference signal generation circuit, N bit digitals subtraction circuit and control circuit；It is each reference voltage regulating circuit, each
The N position analog-digital converters and each N output register in a channel are corresponding one by one；
Wherein, reference voltage generating circuit generates a reference voltage and is input to reference voltage remote driver circuit；Reference voltage
The roads the M output reference voltage of remote driver circuit is connected respectively to the reference voltage input of M reference voltage regulating circuit, the
The roads M+1 output reference voltage Vrinref is connected to the reference voltage input of calibration reference signal generation circuit；Control circuit
M control signal of M control signal output output is separately connected the control signal input of M reference voltage regulating circuit
The positions the K 1 ~ M of compensation codes at end, the M K compensation codes output ends output of control circuit is separately connected M reference voltage regulating circuit
Compensation codes input terminal；The reference voltage output end of reference voltage regulating circuit connects corresponding N analog-digital converter, calibration
The positions the N analog-digital converter in the channels calibration voltage signal output end Vr_cal connection M of reference signal generation circuit；N moduluses turn
The N digit numeric codes of parallel operation output obtain quantization code after corresponding N output register；The M+1 of N bit digital subtraction circuits
Group digital code input terminal is connected respectively to M N output register and calibrates the benchmark output quantization of reference signal generation circuit
Code output end Dref；The control signal of calibration reference signal generation circuit is connected to the positions the K option code output end of control circuit
Mouthful；The positions the K quantization code output end of N bit digital subtraction circuits is connected to the error input port of control circuit；The school of control circuit
Quasi- control signal Ctrl_mode output ports are connected to N bit digitals subtraction circuit and calibrate the calibration of reference signal generation circuit
Control signal input mouth；The input of the positions the K global adaptation code output end connection reference voltage remote driver circuit of control circuit
End；
Wherein, N and M is arbitrary positive integer, and K is the positive integer no more than N.
2. calibrating circuit for the gain mismatch errors of multichannel ADC as described in claim 1, which is characterized in that the use
It includes calibration mode and compensation model to calibrate circuit in the gain mismatch errors of multichannel ADC；
When entering calibration mode, the gain mismatch errors for multichannel ADC calibrate circuit successively to the positions N in the channels M
Analog-digital converter carries out gain mismatch errors calibration, is sequentially generated K compensation codes of M groups；When entering compensation model, K benefits of M groups
It repays code to remain unchanged, the gain mismatch errors calibration circuit N position digital-to-analogue conversions to the channels M simultaneously for multichannel ADC
Device carries out gain mismatch errors compensation, and the calibration reference signal generation circuit and N bit digital subtraction circuits are turned off to reduce
Power consumption.
3. calibrating circuit for the gain mismatch errors of multichannel ADC as described in claim 1, which is characterized in that the base
Quasi- voltage remote driver circuit includes：One reference voltage programming adjustment circuit and M+1 voltage remote driver circuit；Benchmark electricity
The output end of pressure programming adjustment circuit connects M+1 voltage remote driver circuit simultaneously；Reference voltage programs the defeated of adjustment circuit
Go out voltage to be controlled by K global adaptation codes.
4. calibrating circuit for the gain mismatch errors of multichannel ADC as described in claim 1, which is characterized in that the school
Quasi- reference signal generation circuit includes：One programmable calibration voltage generation circuit and benchmark output quantization code generation circuit；
The reference voltage input terminal of the programmable calibration voltage generation circuit is connected to the M of reference voltage remote driver circuit
+ 1 road output reference voltage Vrinref, programmable calibration voltage generation circuit export calibration benchmark under the control of K option codes
Voltage；Benchmark output quantization code generation circuit output reference output quantization code under the control of K option codes.
5. calibrating circuit for the gain mismatch errors of multichannel ADC as claimed in claim 4, which is characterized in that the base
Quasi- output quantization code generation circuit only works in the calibration mode, including by Ctrl_mode signals control ROM look-up tables,
ROM module and benchmark quantization code output circuit；K option codes enter ROM look-up tables, obtain corresponding address to ROM module,
ROM module appropriate address is corresponded to stored in memory cell benchmark quantization code data export to benchmark quantization code export electricity
Road, benchmark quantization code output circuit output reference output quantization code.
6. calibrating circuit for the gain mismatch errors of multichannel ADC as described in claim 1, which is characterized in that the control
Circuit processed includes：Core control circuit, adjustment code generation circuit, computing circuit, K bit registers group, is mended option code generation circuit
Repay yard output register 1~compensation codes output register M and a channel selection circuit；
Wherein, the input terminal of core control circuit connects calibration activation information, and the first output end connection of core control circuit is logical
The control signal of road selection circuit, second output terminal connect the control signal of computing circuit, the connection selection of third output end
The control signal of code generation circuit, the control signal of the 4th output end connection adjustment code generation circuit, the 5th output end connect
Meet the control signal of K bit register groups, M calibration control signal Ctrl1~Ctrl M that the six~the M+5 output ends generate
It is separately connected compensation codes output register 1~compensation codes output register M；The data input pin of computing circuit receives K deposits
The data that device group output end is sent, and K error codes are generated according to the control instruction of core control circuit；Compensation codes output deposit
The data input pin of device 1~compensation codes output register M is all connected to the positions the K error codes output end of computing circuit, compensation codes
The 1st~the M data that the output end of output register 1~compensation codes output register M is connected respectively to channel selection circuit is defeated
Enter end；Channel selection circuit exports K 1 ~ M of compensation codes according to the control instruction of core control circuit；Option code generation circuit root
K option codes are generated according to the control instruction of core control circuit；Adjustment code generation circuit refers to according to the control of core control circuit
It enables and generates K global adaptation codes；The data input pin of K bit register groups receives the output end hair of the N bit digitals subtraction circuit
The positions the K quantization code sent, and be sent to the data being stored in its internal register according to the control instruction of core control circuit
Computing circuit.
7. calibrating circuit for the gain mismatch errors of multichannel ADC as claimed in claim 6, which is characterized in that the school
In the calibration mode, any time, only one signal was effective by quasi- control signal Ctrl1~Ctrl M；In the N to the channels M
During position analog-digital converter is calibrated, the channel selection circuit is corresponding by the positions the N calibrated analog-digital converter
The output of compensation codes output register is opened, and the output of remaining compensation codes output register is closed.
8. calibrating circuit for the gain mismatch errors of multichannel ADC as claimed in claim 6, which is characterized in that the fortune
It calculates circuit and generates K error codes using two points of successive approximation algorithms, each operation only changes 1 in K error codes；It is final defeated
Going out the positions the K error codes remained unchanged needs loop computation just to can determine that for K times.
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