CN108766870B - Ltps tft基板的制作方法及ltps tft基板 - Google Patents

Ltps tft基板的制作方法及ltps tft基板 Download PDF

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CN108766870B
CN108766870B CN201810546898.0A CN201810546898A CN108766870B CN 108766870 B CN108766870 B CN 108766870B CN 201810546898 A CN201810546898 A CN 201810546898A CN 108766870 B CN108766870 B CN 108766870B
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insulating layer
layer
gate insulating
tft substrate
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CN108766870A (zh
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程涛
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Wuhan China Star Optoelectronics Technology Co Ltd
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Abstract

本发明提供一种LTPS TFT基板的制作方法及LTPS TFT基板。本发明的LTPS TFT基板的制作方法，在栅极绝缘层成膜后用含氮的等离子体对栅极绝缘层进行掺氮处理，使栅极绝缘层内的正电荷增加，从而能够使P型TFT阈值电压减小，进而能够改善显示面板闪屏的问题。

Description

LTPS TFT基板的制作方法及LTPS TFT基板
技术领域
本发明涉及显示技术领域，尤其涉及一种LTPS TFT基板的制作方法及LTPS TFT基板。
背景技术
在显示技术领域，液晶显示器(LiquidCrystalDisplay，LCD)和有源矩阵驱动式有机电致发光(ActiveMatrixOrganicLight-EmittingDiode，AMOLED)显示器等平板显示装置因具有机身薄、高画质、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本屏幕等。
薄膜晶体管(ThinFilmTransistor，TFT)阵列(Array)基板是目前LCD装置和AMOLED装置中的主要组成部件，直接关系到高性能平板显示装置的发展方向，用于向显示器提供驱动电路，通常设置有数条栅极扫描线和数条数据线，该数条栅极扫描线和数条数据线限定出多个像素单元，每个像素单元内设置有薄膜晶体管和像素电极，薄膜晶体管的栅极与相应的栅极扫描线相连，当栅极扫描线上的电压达到开启电压时，薄膜晶体管的源极和漏极导通，从而将数据线上的数据电压输入至像素电极，进而控制相应像素区域的显示。通常阵列基板上薄膜晶体管的结构又包括层叠设置于衬底基板上的栅极、栅极绝缘层、有源层、源漏极、及绝缘保护层。
其中，低温多晶硅(LowTemperaturePoly-Silicon，LTPS)薄膜晶体管与传统非晶硅(A-Si)薄膜晶体管相比，虽然制作工艺复杂，但因其具有更高的载流子迁移率，被广泛用于中小尺寸高分辨率的LCD和AMOLED显示面板的制作，低温多晶硅被视为实现低成本全彩平板显示的重要材料。
GOA(Gate Driver on Array)技术即阵列基板行驱动技术，是利用薄膜晶体管阵列制程将栅极扫描驱动电路制作在TFT阵列基板上，以实现逐行扫描的驱动方式，具有降低生产成本和实现面板窄边框设计的优点，为多种显示器所使用。GOA电路具有两项基本功能：第一是输出栅极扫描驱动信号，驱动面板内的栅极线，打开显示区内的TFT，以对像素进行充电；第二是移位寄存功能，当一个栅极扫描驱动信号输出完成后，通过时钟控制进行下一个栅极扫描驱动信号的输出，并依次传递下去。GOA技术能减少外接IC的焊接(Bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框的显示产品。
目前，金属氧化物半导体(MetalOxideSemiconductor，MOS)器件通常采用LTPS制作，其主要分为N型金属氧化物半导体(Negative channel Metal Oxide Semiconductor，NMOS)、P型金属氧化物半导体(Positive channel MetalOxide Semiconductor，PMOS),其中NMOS晶体管(N型TFT)和PMOS晶体管(P型TFT)的主要区别在于所设置的源漏极接触区分别由N型离子重掺杂和P型离子重掺杂所形成。
对于P型TFT而言，当加在栅极上的电压小于阈值电压(VTH)时，源极和漏极之间导通，因此，阈值电压是决定TFT性能的一个重要参量。从节省能耗角度出发，IC芯片的降频驱动模式倍受欢迎，但当P型TFT Vth较大时，在IC芯片驱动下，显示面板在降频时会出现闪屏的情况。这归因于降频情况下IC对GOA信号无推力，导致开通电压(VGH)和关断电压(VGL)电压降增加；期间像素漏电增加，表现为产生串扰(Crosstalk)画面。
针对以上降频闪屏问题，可通过调节P型TFTVth来实现，同时改善TFT器件质量问题和节省能耗。
发明内容
本发明的目的在于提供一种LTPS TFT基板的制作方法，能够使P型TFT阈值电压负移，相对现有技术，能够使得P型TFT阈值电压(P-VTH)的最大值从-1V减小到-1.3V，进而能够改善显示面板闪屏的问题。
本发明的目的还在于提供一种LTPS TFT基板，能够使P型TFT阈值电压减小，进而能够改善显示面板闪屏的问题。
为实现上述目的，本发明提供一种LTPS TFT基板的制作方法，包括如下步骤：
步骤S1、提供衬底基板，在所述衬底基板上形成多晶硅有源层；
步骤S2、在所述衬底基板上沉积形成覆盖多晶硅有源层的栅极绝缘层，用含氮的等离子体对所述栅极绝缘层进行掺氮处理；
步骤S3、在栅极绝缘层上形成栅极及源漏极。
所述栅极绝缘层为氧化硅层。
所述步骤S2中，通过反应气体在PECVD设备内形成含氮的等离子对所述栅极绝缘层进行掺氮处理，所述反应气体包括氨气、氮气及氧化二氮中至少一种；所述PECVD设备对栅极绝缘层进行掺氮处理时所使用的电功率为2000-10000w，对所述栅极绝缘层进行掺氮处理的时间为10-120s。
所述步骤S2中，在PECVD设备内形成含氮的等离子的所述反应气体为氨气；所述PECVD设备对栅极绝缘层进行掺氮处理时所使用的电功率为6000-8000W，对所述栅极绝缘层进行掺氮处理的时间为40-70s。
所述步骤S3还包括在形成源漏极之前，在所述栅极绝缘层上形成对应于所述多晶硅有源层两端上方的过孔，在形成源漏极之后，所述源漏极通过所述过孔与所述多晶硅有源层相接触。
所述步骤S1或步骤S3还包括对所述多晶硅有源层进行P型离子掺杂。
对所述多晶硅有源层进行P型离子掺杂时所掺入的离子为硼离子。
本发明还提供一种LTPS TFT衬底基板，包括衬底基板、设于衬底基板上的多晶硅有源层、设于衬底基板上覆盖多晶硅有源层的栅极绝缘层及设于所述栅极绝缘层上的栅极和源漏极；
所述栅极绝缘层经过掺氮处理。
所述栅极绝缘层为氧化硅层。
所述多晶硅有源层经过P型离子掺杂；所述栅极绝缘层上在对应于所述多晶硅有源层两端上方设有过孔，所述源漏极通过所述过孔与所述多晶硅有源层相接触。
本发明的有益效果：本发明的LTPS TFT基板的制作方法，在栅极绝缘层成膜后用含氮的等离子体对栅极绝缘层进行掺氮处理，使栅极绝缘层内的正电荷增加，从而能够使P型TFT阈值电压负移，相对现有技术能够使得P型TFT阈值电压的最大值从-1V减小到-1.3V，进而能够改善显示面板闪屏的问题。本发明的LTPS TFT基板，栅极绝缘层经过掺氮处理，从而能够使P型TFT阈值电压负移，相对现有技术能够使得P型TFT阈值电压的最大值从-1V减小到-1.3V，进而能够改善显示面板闪屏的问题。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的LTPS TFT基板的制作方法的流程示意图；
图2为本发明的LTPS TFT基板的制作方法的步骤S1的示意图；
图3为本发明的LTPS TFT基板的制作方法的步骤S2的示意图；
图4为本发明的LTPS TFT基板的制作方法的步骤S3的示意图暨本发明的LTPS TFT基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种LTPS TFT基板的制作方法，其特征在于，包括如下步骤：
步骤S1、如图2所示，提供衬底基板10，在所述衬底基板10上形成多晶硅有源层30。
步骤S2、如图3所示，在所述衬底基板10上沉积形成覆盖多晶硅有源层30的栅极绝缘层40，用含氮的等离子体对所述栅极绝缘层40进行掺氮处理。
步骤S3、如图4所示，在栅极绝缘层40上形成栅极20及源漏极50，得到TFT结构。
具体地，所述栅极绝缘层40为氧化硅层。
具体地，所述步骤S2中，采用氨气(NH3)、氮气(N2)氧化二氮(NO2)中的至少一种作为反应气体在PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学的气相沉积)设备内形成含氮的等离子对所述栅极绝缘层40进行掺氮处理。
优选地，所述步骤S2中，采用氨气作为反应气体在PECVD设备内形成含氮的等离子。
具体地，所述步骤S2中，所述PECVD设备对栅极绝缘层40进行掺氮处理所使用的电功率为2000-10000w，进一步优选为6000-8000W；对所述栅极绝缘层40进行掺氮处理的时间为10-120s，进一步优选为40-70s。
具体地，所述步骤S3还包括在形成源漏极50之前，在所述栅极绝缘层40上形成对应于所述多晶硅有源层30两端上方的过孔45，在形成源漏极50之后，所述源漏极50通过所述过孔45与所述多晶硅有源层30相接触。
具体地，所述步骤S1或步骤S3还包括对所述多晶硅有源层30进行P型离子掺杂，即所形成的TFT结构为P型TFT结构。
具体地，对所述多晶硅有源层30进行P型离子掺杂时所掺入的离子为硼离子。
本发明通过以下实验对本发明的技术效果进行了验证:
实验一
采用NH3和N2作为反应气体在PECVD设备内形成含氮的等离子对氧化硅层的栅极绝缘层40进行掺氮处理，PECVD设备所使用的电功率为6000w，掺氮处理的时间为55s；结果使P-Vth负移，P-Vth分布区间为-2.61到-1.31V。
实验二
采用NH3和N2作为反应气体在PECVD设备内形成含氮的等离子对氧化硅层的栅极绝缘层40进行掺氮处理，PECVD设备所使用的电功率为7000w，掺氮处理的时间为55s；结果使P-Vth负移，P-Vth分布区间为-2.48V到-1.23V。
实验三
采用NH3和N2作为反应气体在PECVD设备内形成含氮的等离子对氧化硅层的栅极绝缘层40进行掺氮处理，PECVD设备所使用的电功率为8000w，掺氮处理的时间为55s；结果使P-Vth负移，P-Vth分布区间为-2.8V到-1.39V。
通过上述实验可以得出，本发明具有使P型TFT阈值电压负移的效果，相对现有技术能够使得P型TFT阈值电压的最大值从-1V减小到-1.3V；需要说明的是，本发明同样可以达到使N型TFT阈值电压减小的效果。
本发明的LTPS TFT基板的制作方法，在栅极绝缘层40成膜后用含氮的等离子体对栅极绝缘层40进行掺氮处理，使栅极绝缘层40内的正电荷增加，从而能够使P型TFT阈值电压负移，相对现有技术能够使得P型TFT阈值电压的最大值从-1V减小到-1.3V，进而能够改善显示面板闪屏的问题。
请参阅图4，基于上述的LTPS TFT基板的制作方法，本发明还提供一种LTPS TFT基板，包括衬底基板10、设于衬底基板10上的多晶硅有源层30、设于衬底基板10上覆盖多晶硅有源层30的栅极绝缘层40及设于所述栅极绝缘层40上的栅极20和源漏极50；
所述栅极绝缘层40经过掺氮处理。
具体地，所述栅极绝缘层40为氧化硅层。
具体地，所述多晶硅有源层30经过P型离子掺杂；所述栅极绝缘层40上在对应于所述多晶硅有源层30两端上方设有过孔45，所述源漏极50通过所述过孔45与所述多晶硅有源层30相接触。
本发明的LTPS TFT基板，栅极绝缘层40经过掺氮处理，从而能够使P型TFT阈值电压负移，相对现有技术能够使得P型TFT阈值电压的最大值从-1V减小到-1.3V，进而能够改善显示面板闪屏的问题。
综上所述，本发明的LTPS TFT基板的制作方法，在栅极绝缘层成膜后用含氮的等离子体对栅极绝缘层进行掺氮处理，使栅极绝缘层内的正电荷增加，从而能够使P型TFT阈值电压负移，相对现有技术能够使得P型TFT阈值电压的最大值从-1V减小到-1.3V，进而能够改善显示面板闪屏的问题。本发明的LTPS TFT基板，栅极绝缘层经过掺氮处理，从而能够使P型TFT阈值电压负移，相对现有技术能够使得P型TFT阈值电压的最大值从-1V减小到-1.3V，进而能够改善显示面板闪屏的问题。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (7)

1.一种LTPS TFT基板的制作方法，其特征在于，包括如下步骤：
步骤S1、提供衬底基板(10)，在所述衬底基板(10)上形成多晶硅有源层(30)；
步骤S2、在所述衬底基板(10)上沉积形成覆盖多晶硅有源层(30)的栅极绝缘层(40)，用含氮的等离子体对所述栅极绝缘层(40)进行掺氮处理；
步骤S3、在栅极绝缘层(40)上形成栅极(20)及源漏极(50)；
所述步骤S1或步骤S3还包括对所述多晶硅有源层(30)进行P型离子掺杂；
所述步骤S2中，通过反应气体在PECVD设备内形成含氮的等离子对所述栅极绝缘层(40)进行掺氮处理，所述反应气体为氨气；所述PECVD设备对栅极绝缘层(40)进行掺氮处理时所使用的电功率为6000-8000W，对所述栅极绝缘层(40)进行掺氮处理的时间为40-70s。
2.如权利要求1所述的LTPS TFT基板的制作方法，其特征在于，所述栅极绝缘层(40)为氧化硅层。
3.如权利要求1所述的LTPS TFT基板的制作方法，其特征在于，所述步骤S3还包括在形成源漏极(50)之前，在所述栅极绝缘层(40)上形成对应于所述多晶硅有源层(30)两端上方的过孔(45)，在形成源漏极(50)之后，所述源漏极(50)通过所述过孔(45)与所述多晶硅有源层(30)相接触。
4.如权利要求1所述的LTPS TFT基板的制作方法，其特征在于，对所述多晶硅有源层(30)进行P型离子掺杂时所掺入的离子为硼离子。
5.一种LTPS TFT基板，其特征在于，包括衬底基板(10)、设于衬底基板(10)上的多晶硅有源层(30)、设于衬底基板(10)上覆盖多晶硅有源层(30)的栅极绝缘层(40)及设于所述栅极绝缘层(40)上的栅极(20)和源漏极(50)；
所述栅极绝缘层(40)经过掺氮处理；
所述多晶硅有源层(30)经过P型离子掺杂；
通过反应气体在PECVD设备内形成含氮的等离子对所述栅极绝缘层(40)进行掺氮处理，所述反应气体为氨气；所述PECVD设备对栅极绝缘层(40)进行掺氮处理时所使用的电功率为6000-8000W，对所述栅极绝缘层(40)进行掺氮处理的时间为40-70s。
6.如权利要求5所述的LTPS TFT基板，其特征在于，所述栅极绝缘层(40)为氧化硅层。
7.如权利要求5所述的LTPS TFT基板，其特征在于，所述栅极绝缘层(40)上在对应于所述多晶硅有源层(30)两端上方设有过孔(45)，所述源漏极(50)通过所述过孔(45)与所述多晶硅有源层(30)相接触。
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