CN108718196B - Operational amplifier offset self-calibration circuit applied to voice coil motor driving chip - Google Patents
Operational amplifier offset self-calibration circuit applied to voice coil motor driving chip Download PDFInfo
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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Abstract
The invention discloses an operational amplifier offset self-calibration circuit applied to a voice coil motor driving chip, which comprises an operational amplifier OPAMP, a counting latch, a comparator, an oscillator and a digital-to-analog converter calibration DAC, wherein the output end of the operational amplifier OPAMP is connected with the negative input end of the comparator, the output end of the comparator is connected with the input end of the oscillator and one input end of the counting latch, the output end of the oscillator is connected with the other input end of the counting latch, the output end of the counting latch is connected with the input end of the digital-to-analog converter calibration DAC, the output end of the digital-to-analog converter calibration DAC is connected with the signal feedback end of the operational amplifier OPAMP, and the input end and the output end of the operational amplifier OPAMP are respectively connected with the voice coil motor driving chip. The offset of the OPAMP can be eliminated or greatly reduced, the accuracy of the output current of the motor driving chip is improved, the service time of a system battery is prolonged, and the chip development and test cost is increased by avoiding trimming the fuse.
Description
Technical Field
The invention relates to the technical field of semiconductor equipment, in particular to an operational amplifier offset self-calibration circuit applied to a voice coil motor driving chip.
Background
There are many methods for implementing camera focusing, in which, the Voice Coil Motor (VCM) has advantages of simple structure, small volume, fast response speed, and the most widely used range includes: an automatic focusing camera shooting module of a smart phone, a notebook computer, a network camera, a video monitor, a scanner and the like.
As shown in fig. 1, a circuit block diagram of a voice coil motor driver chip 100 includes modules including: the circuit equivalent model 110 of the voice coil motor comprises a coil inductance L1 and a coil internal resistance R1. The basic principle of VCM driving is as follows: the control end of the motor sends an instruction of outputting current to the voice coil motor driving chip through the I2C interface, and after the I2C interface of the voice coil motor driving chip receives the instruction, the instruction is converted into a corresponding voltage signal Vdac through the digital-to-analog converter main DAC. Due to the "virtual short" of the op amp input, in an ideal case the voltage Vsen of the current sense resistor Rsense is equal to Vdac, and the output current iout=vsen/rsense=vdac/Rsense is controlled by Vdac by ohm's law, thus completing the driving process from the input command to the output current.
Since the op amp input has an offset error in the actual situation, vsen is not equal to Vdac, resulting in an error between the actual output current and the output current required by the control terminal, which error not only affects the accuracy of the motor drive, but also still has a current output in the case of a zero current command output by the control terminal. In battery-powered applications such as portable phones, the voice coil motor is in a zero-output current state most of the time, so that input imbalance of the operational amplifier OPAMP can cause great power consumption waste, and the service time of a system battery is shortened.
At present, in order to solve the contradiction, the following solutions mainly exist:
1) The area of the OPAMP input pair tube is enlarged, and a common centroid and other symmetrical drawing methods are adopted on the layout. This approach only partially reduces the imbalance and does not completely eliminate the imbalance to a systematically acceptable range.
2) Chopper auto-zeroing technique. This technique is limited in continuous time applications and the non-idealities of the clock switch introduce noise that degrades system performance.
3) A fuse Trimming (Trimming) scheme is employed, however Trimming increases the development and testing costs of the entire chip.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides the operational amplifier offset self-calibration circuit and the operational amplifier offset self-calibration method applied to the voice coil motor driving chip, which can eliminate or greatly reduce the offset of the operational amplifier OPAMP, improve the accuracy of the output current of the motor driving chip, prolong the service time of a system battery, and avoid the use of fuses to repair and increase the development and test cost of the chip.
The technical scheme adopted by the invention for solving the technical problems is as follows:
the operational amplifier offset self-calibration circuit comprises an operational amplifier OPAMP, a counting latch, a comparator, an oscillator and a digital-to-analog converter calibration DAC, wherein the output end of the operational amplifier OPAMP is connected with the negative input end of the comparator, the output end of the comparator is connected with the input end of the oscillator and one input end of the counting latch, the output end of the oscillator is connected with the other input end of the counting latch, the output end of the counting latch is connected with the input end of the digital-to-analog converter calibration DAC, the output end of the digital-to-analog converter calibration DAC is connected with the signal feedback end of the operational amplifier OPAMP, and the input end and the output end of the operational amplifier OPAMP are respectively connected with an output stage circuit of the voice coil motor driving chip.
According to the technical scheme, a switch POR is connected between the output end of the operational amplifier OPAMP and the negative electrode input end of the comparator, the switch POR is connected with the voice coil motor driving chip, the voice coil motor driving chip is powered on for resetting, the switch POR becomes high level, and the switch POR is in a closed state.
According to the technical scheme, the digital-to-analog converter calibration DAC is an N-bit current type digital-to-analog converter, and the counting latch is an N-bit counting latch.
According to the technical scheme, the output stage circuit of the voice coil motor driving chip comprises a digital-to-analog converter main DAC, a current detection resistor Rsense and an output stage power transistor NM0, wherein the output end of the digital-to-analog converter main DAC is connected with the positive input end of the operational amplifier OPAMP, one end of the current detection resistor Rsense is grounded, the other end of the current detection resistor Rsense is connected with the negative input end of the operational amplifier OPAMP and the source electrode of the output stage power transistor NM0, and the grid electrode of the output stage power transistor NM0 is connected with the output end of the operational amplifier OPAMP;
a fourth switch is connected between the current detection resistor Rsense and the negative input end of the operational amplifier OPAMP, a third switch is connected between the digital-to-analog converter main DAC and the positive input end of the operational amplifier OPAMP, a fifth switch is connected between the grid electrode of the output stage power transistor NM0 and the output end of the operational amplifier OPAMP, the control ends of the third switch, the fourth switch and the fifth switch are connected with the output end COB of the first inverter, when the output end COB of the first inverter is in a high level, the third switch, the fourth switch and the fifth switch are closed, and when the output end COB of the first inverter is in a low level, the third switch, the fourth switch and the fifth switch are opened;
the positive input end of the operational amplifier OPAMP is grounded through a first switch, the negative input end of the operational amplifier OPAMP is grounded through a second switch, the control ends of the first switch and the second switch are connected with the output end CO of the second inverter, when the output end CO of the second inverter is at a high level, the first switch and the second switch are closed, and when the output end CO of the second inverter is at a low level, the first switch and the second switch are opened.
According to the technical scheme, the offset voltage range of the operational amplifier OPAMP is [ -100mV,0mV ].
According to the above technical solution, the operational amplifier OPAMP includes an input pair transistor MP0a, an input pair transistor MP0b, a bias current IBIAS, a load MOS transistor MN1, a load MOS transistor MN2, a load MOS transistor MN3, a load MOS transistor MN4, a pull-down enabling MOS transistor MN5, and an adjustable current mirror load, where the source of the input pair transistor MP0a is connected to the source of the input pair transistor MP0b and the bias current IBIAS, the drain of the input pair transistor MP0a is connected to the source of the load MOS transistor MN1 and the drain of the load MOS transistor MN3, the drain of the input pair transistor MP0b is connected to the source of the load MOS transistor MN2 and the drain of the load MOS transistor MN4, the drain of the load MOS transistor MN1 is connected to the input of the adjustable current mirror load, the drain of the load MOS transistor MN2 is connected to the output of the adjustable current mirror load and the drain of the pull-down enabling MOS transistor MN5, and serves as the output of the operational amplifier OPAMP, and the source of the load MOS transistor MN3 is connected to the source of the load MOS transistor MN4 and the source of the pull-down enabling transistor MN5, and is grounded.
The gate of the input pair tube MP0a and the gate of the input pair tube MP0b are respectively used as the positive electrode input terminal and the negative electrode input terminal of the operational amplifier OPAMP.
According to the above technical scheme, the gate of the load MOS transistor MN1 and the gate of the load MOS transistor MN2 are both connected to the bias voltage Vnbias1, and the gate of the load MOS transistor MN3 and the gate of the load MOS transistor MN4 are both connected to the bias voltage Vnbias2.
According to the technical scheme, the adjustable current mirror load comprises a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3 and a PMOS tube MP4, wherein the source electrode of the PMOS tube MP1 is connected with the source electrode of the PMOS tube MP2, the drain electrode of the PMOS tube MP1 is connected with the source electrode of the PMOS tube MP3, the drain electrode of the PMOS tube MP2 is connected with the source electrode of the PMOS tube MP4, the drain electrode of the PMOS tube MP3 is connected with the grid electrode of the PMOS tube MP3 and the grid electrode of the PMOS tube MP4 and is used as the input end of the adjustable current mirror, and the drain electrode of the PMOS tube MP4 is used as the output end of the adjustable current mirror.
According to the above technical scheme, the gate of the PMOS transistor MP1 and the gate of the PMOS transistor MP2 are respectively connected to the bias voltage Vconb and the bias voltage Vcon.
According to the technical scheme, the DAC is calibrated into an eight-bit R2R framework.
The invention has the following beneficial effects:
1. after the chip is powered on and reset, the output Vout of the operational amplifier OPAMP is smaller than 0.5 x VDD, so that the output COMP of the comparator is high level '1', the oscillator starts working and outputs a clock CLK to the counting latch, the counter counts down the rising edge number of the CLK clock from all '1', and the digital-to-analog converter is controlled by the output of the data N which is continuously decreased, the calibration DAC continuously reduces Vcon and compensates offset voltage, and therefore Vout is improved; when Vout crosses 0.5 x VDD and changes from low level to high level, the output COMP of the comparator changes from high level '1' to low level '0', the oscillator stops working, the counting latch latches the data N < N-1:0> calibrated at the moment, and the calibration process is ended; the offset of the OPAMP can be eliminated or greatly reduced, the accuracy of the output current of the motor driving chip is improved, the service time of a system battery is prolonged, and the chip development and test cost is increased by avoiding trimming the fuse.
The novel operational amplifier provided by the invention can eliminate or reduce offset below the resolution of the calibration DAC, the latch latches the calibration data after the calibration is completed, and then the calibrated amplifier OPAMP is connected into the output stage circuit of the voice coil motor driving chip, so that the output current precision of the voice coil motor driving chip is greatly improved, the situations of error current output and power consumption waste in a zero output current state are avoided, the service time of a system battery is prolonged, and the automatic calibration is not required to be modified by a fuse, so that the cost of chip research, development and test is saved.
Drawings
FIG. 1 is a block diagram of a prior art voice coil motor driver chip in accordance with an embodiment of the present invention;
FIG. 2 is a schematic diagram of an operational amplifier offset self-calibration circuit applied to a voice coil motor driver chip in an embodiment of the invention;
FIG. 3 is a self-calibration flow chart of an operational amplifier offset self-calibration circuit applied to a voice coil motor driver chip in an embodiment of the invention;
FIG. 4 is a circuit diagram of an operational amplifier OPAM in an embodiment of the invention;
FIG. 5 is a circuit diagram of an adjustable current mirror load in an embodiment of the invention;
FIG. 6 is a schematic diagram of the adjustable range of the adjustable current mirror load in an embodiment of the invention;
fig. 7 is a graph showing the relationship between Vcon and offset voltage Vos when vconb=1.5v is fixed in the embodiment of the present invention;
FIG. 8 is a circuit diagram of a digital to analog converter calibration DAC in an embodiment of the present invention;
FIG. 9 is a graph showing the relationship between the output voltage Vcon and the N-bit input count value in the embodiment of the invention;
FIG. 10 is a schematic diagram of a detailed calibration process of an OPAM in an embodiment of the invention;
in the figure, the 100-voice coil motor driving chip, the 102-digital-to-analog converter main DAC, the circuit equivalent model of the 110-voice coil motor, the output stage circuit of the 200-voice coil motor driving chip, the 201-first switch, the 202-second switch, the 203-third switch, the 204-fourth switch, the 205-fifth switch, the 206-first inverter, the 207-second inverter, the 400-operational amplifier OPAMP, the 401-adjustable current mirror load and the 500-digital-to-analog converter calibration DAC are shown.
Detailed Description
The invention will now be described in detail with reference to the drawings and examples.
Referring to fig. 1 to 10, the operational amplifier offset self-calibration circuit applied to the voice coil motor driving chip in one embodiment of the present invention includes an operational amplifier OPAMP, a count latch, a comparator, an oscillator, and a digital-to-analog converter calibration DAC500, wherein an output end of the operational amplifier OPAMP is connected to a negative input end of the comparator, an output end of the comparator is connected to an input end of the oscillator and one input end of the count latch, an output end of the oscillator is connected to another input end of the count latch, an output end of the count latch is connected to an input end of the digital-to-analog converter calibration DAC500, an output end of the digital-to-analog converter calibration DAC500 is connected to a signal feedback end of the operational amplifier OPAMP, and an input end and an output end of the operational amplifier OPAMP are also respectively connected to the output stage circuit 200 of the voice coil motor driving chip.
Further, a switch POR is connected between the output end of the operational amplifier OPAMP and the negative input end of the comparator, the switch POR is connected with the voice coil motor driving chip 100, the voice coil motor driving chip 100 is powered on for resetting, the switch POR becomes high level, and the switch POR is in a closed state.
Further, the positive input end and the negative input end of the operational amplifier OPAMP are respectively a 1 st pin and a 2 nd pin of the operational amplifier OPAMP, the output end of the operational amplifier OPAMP is a 3 rd pin of the operational amplifier OPAMP, and the signal feedback end of the operational amplifier OPAMP is a 4 th pin of the operational amplifier OPAMP.
Further, the DAC calibration DAC500 is an N-bit current-type DAC, and the counter latch is an N-bit counter latch.
Further, the output stage circuit 200 of the voice coil motor driving chip includes a digital-to-analog converter main DAC102, a current detection resistor Rsense and an output stage power transistor NM0, where an output end of the digital-to-analog converter main DAC102 is connected to an anode input end of the operational amplifier OPAMP, one end of the current detection resistor Rsense is grounded, the other end of the current detection resistor Rsense is connected to a cathode input end of the operational amplifier OPAMP and a source electrode of the output stage power transistor NM0, and a gate electrode of the output stage power transistor NM0 is connected to an output end of the operational amplifier OPAMP;
a fourth switch 204 is connected between the current detection resistor Rsense and the negative input end of the operational amplifier OPAMP, a third switch 203 is connected between the digital-to-analog converter main DAC102 and the positive input end of the operational amplifier OPAMP, a fifth switch 205 is connected between the gate of the output stage power transistor NM0 and the output end of the operational amplifier OPAMP, the control ends of the third switch 203, the fourth switch 204 and the fifth switch 205 are connected with the output end COB of the first inverter 206, when the output end COB of the first inverter 206 is at a high level, the third switch 203, the fourth switch 204 and the fifth switch 205 are closed, and when the output end COB of the first inverter 206 is at a low level, the third switch 203, the fourth switch 204 and the fifth switch 205 are opened;
the positive input end of the operational amplifier OPAMP is grounded through the first switch 201, the negative input end of the operational amplifier OPAMP is grounded through the second switch 202, the control ends of the first switch 201 and the second switch 202 are connected with the output end CO of the second inverter 207, when the output end CO of the second inverter 207 is in a high level, the first switch 201 and the second switch 202 are closed, and when the output end CO of the second inverter 207 is in a low level, the first switch 201 and the second switch 202 are opened; the drain of the output stage power transistor NM0 serves as the output terminal of the voice coil motor driving chip 100.
Further, the offset voltage of the operational amplifier OPAMP is within the range of [ -100mV,0mV ].
Further, offset voltage of-50 mV is added to the operational amplifier in advance, the original offset voltage range of the operational amplifier is [ -50mV,50mV ], so that the total offset voltage range of the operational amplifier is changed into [ -100mV,0], the offset calibration direction is changed from uncertain positive and negative to unidirectional elimination of negative offset voltage, and the calibration logic complexity or error caused by uncertainty of positive and negative polarities of the offset voltage of the operational amplifier is avoided.
Further, the operational amplifier OPAMP includes an input pair of tubes MP0a, an input pair of tubes MP0b, a bias current IBIAS, a load MOS tube MN1, a load MOS tube MN2, a load MOS tube MN3, a load MOS tube MN4, a pull-down enabling MOS tube MN5 and an adjustable current mirror load 401, a source of the input pair of tubes MP0a is connected with a source of the input pair of tubes MP0b and the bias current IBIAS, a drain of the input pair of tubes MP0a is connected with a source of the load MOS tube MN1 and a drain of the load MOS tube MN3, a drain of the input pair of tubes MP0b is connected with a source of the load MOS tube MN2 and a drain of the load MOS tube MN4, a drain of the load MOS tube MN1 is connected with an input of the adjustable current mirror load 401, a drain of the load MOS tube MN2 is connected with an output of the adjustable current mirror load 401 and a drain of the pull-down enabling MOS tube MN5, and serves as an output of the operational amplifier OPAMP, an output signal of the operational amplifier OPAMP is noted Vout, a source of the load MOS tube MN3 is connected with a source of the load MOS tube MN4 and the pull-down enabling tube MN5, and is grounded;
the grid of the input pair tube MP0a and the grid of the input pair tube MP0b are respectively used as the positive input end and the negative input end of the operational amplifier OPAMP and are respectively marked as INN and INP;
further, the gate of the pull-down enable MOS transistor MN5 receives the enable signal PORB of the op amp;
further, the gate of the load MOS transistor MN1 and the gate of the load MOS transistor MN2 are both connected to the bias voltage Vnbias1, and the gate of the load MOS transistor MN3 and the gate of the load MOS transistor MN4 are both connected to the bias voltage Vnbias2.
Further, the adjustable current mirror load 401 includes a PMOS transistor MP1, a PMOS transistor MP2, a PMOS transistor MP3, and a PMOS transistor MP4, where a source of the PMOS transistor MP1 is connected to a source of the PMOS transistor MP2, a drain of the PMOS transistor MP1 is connected to a source of the PMOS transistor MP3, a drain of the PMOS transistor MP2 is connected to a source of the PMOS transistor MP4, a drain of the PMOS transistor MP3 is connected to a gate of the PMOS transistor MP3 and a gate of the PMOS transistor MP4, and is used as an input terminal of the adjustable current mirror, and a drain of the PMOS transistor MP4 is used as an output terminal of the adjustable current mirror; the PMOS tube MP1 and the PMOS tube MP2 are used as variable resistors, and the PMOS tube MP3 and the PMOS tube MP4 form a current mirror.
Further, the bias current IBIAS, the source of the PMOS transistor MP1, and the source of the PMOS transistor MP2 are all connected to the power supply voltage VDD.
Further, the gate of the PMOS transistor MP1 and the gate of the PMOS transistor MP2 are respectively connected to the bias voltage Vconb and the bias voltage Vcon.
Further, the digital-to-analog converter calibrates the DAC500 to an eight bit R2R architecture.
Further, the DAC500 includes 8 current sources and 8 switches, one ends of the 8 switches are connected to the 8 current sources respectively, the other end of the innermost switch N0 is connected to a resistor R, the other ends of the remaining 7 switches are connected to 2R, a resistor R is connected between the resistor connection ends of two adjacent switches, the current sources are 0.5×i, and the resistor connection end of the outermost switch N7 is used as the output end Vcon of the DAC500.
The working principle of the invention is as follows:
as shown in FIG. 2, the offset self-calibration method is schematically shown in FIG. 2, 200 is an output stage circuit of a chip in normal operation, and 210 is an operational amplifier offset self-calibration circuit provided by the invention, and the offset self-calibration method comprises an operational amplifier OPAMP, an N-bit counting latch, a comparator, an oscillator and an N-bit digital-to-analog converter calibration DAC500. The basic principle of the method is as follows: initially, the chip is reset on power, and the POR goes high. The output Vout of the op amp is set to a low level just at the beginning and is connected to the negative input of the comparator. COMP is high since the comparator's positive input VREF is VDD/2. At this time, CO is high level, COB is low level, and op amp enters an auto calibration process. After the calibration is completed, CO becomes low level, COB becomes high level, and the operational amplifier OPAMP disconnects the self-calibration circuit and is connected to the output stage circuit 200 of the voice coil motor driving chip which normally works.
As shown in fig. 3, the self-calibration flowchart is started immediately before the op amp input is shorted to ground, and the output Vout is low. Because the positive and negative polarities of the offset voltage of the operational amplifier are uncertain, and the offset voltage of the uncalibrated CMOS is in the range of [ -50mV,50mV ], the offset of-50 mV is arranged at the input end of the operational amplifier, so that the total input offset voltage range of the operational amplifier is [ -100mV,0mV ], the calibration direction is ensured to be unidirectional, the calibration logic is simplified, and the output Vout is still low level when the input ends of the operational amplifier are all short to the ground, so that the calibration logic cannot be wrong.
Since Vout is less than 0.5 x vdd, the comparator output COMP is high "1", at which time the oscillator starts to operate and outputs the clock CLK to the N-bit counting latch, the counter counts down the number of rising edges of the CLK clock starting from all '1's and outputs the continuously decreasing data N to control the digital-to-analog converter calibration DAC500. The calibration DAC continuously reduces Vcon, compensates for offset voltage, and thereby increases Vout. When Vout crosses 0.5×vdd, from low level to high level, the comparator output COMP changes from high level "1" to low level "0", the oscillator stops working, the counter latch latches the data N < N-1:0> calibrated at this time, and the calibration process ends.
After the voice coil motor driving chip 100 is powered on, the offset voltage of-50 mV is added to the OPAMP input stage in advance, and after the offset voltage of the OPAMP is added, the total offset voltage range of the OPAMP is [ -100mV,0mV ], so that the problems of complex calibration logic and error calibration direction caused by uncertainty of the positive and negative polarities of the offset voltage of the OPAMP are avoided. The novel operational amplifier provided by the invention can eliminate or reduce offset below the resolution of the calibration DAC, the latch latches the calibration data after the calibration is completed, and then the calibrated amplifier OPAMP is connected into the output stage circuit of the voice coil motor driving chip, so that the output current precision of the voice coil motor driving chip is greatly improved, the situations of error current output and power consumption waste in a zero output current state are avoided, the service time of a system battery is prolonged, and the automatic calibration is not required to be modified by a fuse, thereby saving the cost of chip research, development and test.
The key points of the invention are as follows: 1) And adding offset voltage of-50 mV to the operational amplifier in advance, wherein the offset voltage range of the operational amplifier is [ -50mV,50mV ], so that the total offset voltage range of the operational amplifier is [ -100mV,0], thus the offset calibration direction is changed from uncertain positive and negative to unidirectional elimination of negative offset voltage, and the complex or error of calibration logic caused by uncertain positive and negative polarities of the offset voltage of the operational amplifier is avoided. 2) The novel operational amplifier OPAMP can eliminate offset voltage by calibrating the load current mirror proportion of the PMOS current mirror, has a simple structure and small use area, and can reduce the offset voltage to uV order of magnitude by combining with an 8-bit DAC.
In order to describe the effects that the present invention can achieve, as shown in fig. 4, a novel operational amplifier is provided, and the amplifier includes differential input pair transistors MP0a and MP0b, input pair transistor bias current IBIAS, load MOS transistor MN1, load MOS transistor MN2, load MOS transistor MN3, load MOS transistor MN4, pull-down enable MOS transistor MN5 and bias voltage Vnbias1, bias voltage Vnbias2, and adjustable current mirror load 401; the adjustable current mirror load 401 includes a current mirror (the current mirror is composed of a PMOS transistor MP3 and a PMOS transistor MP 4), and a PMOS transistor MP1 and a PMOS transistor MP2 serving as a variable resistor; wherein INP and INN are positive and negative input terminals of the op-amp, PORB is an enable signal of the op-amp, and Vout is an output signal of the op-amp.
Firstly, to ensure the correct calibration logic, a fixed-50 mV offset needs to be added to the op-amp; the voltage difference VSG1 between the gate and source of the input pair transistor MP0a in the saturated state, and the voltage difference VSG2 between the gate and source of MP0b are given by formulas (1-1) and (1-2), respectively:
VSG1＝Vth+(2*I/(W/L) MP0a ) 1/2 (1-1)
VSG2＝Vth+(2*I/(W/L) MP0b ) 1/2 (1-2)
wherein Vth represents the threshold voltage of the input pair MOS transistor, I represents the drain current of the input pair MOS transistor, W represents the channel width of the MOS transistor, and L represents the channel length of the MOS transistor, so that the difference between the gate and source voltages of the input pair transistor can be obtained as follows:
ΔVSG＝VSG1-VSG2＝(2*I/(W/L) MP0a ) 1/2 -(2*I/(W/L) MP0b ) 1/2 (1-3)
according to the formula (1-3), the dimension W/L of MP0a is regulated to be larger than the dimension of MP0b by a certain proportion, so that DeltaVSG=VSG1-VSG2= -50mV, VG1 (INN) is 50mV larger than INP (INP) because the source voltage of the differential input pair tube is equal, thus the input end introduces-50 mV offset at the beginning, and the offset voltage range of the whole operational amplifier is [ -100mV,0mV ].
As shown in fig. 5, the Ratio of the input currents Iin and Iout of the adjustable current mirror load 401 is determined by the equation (1-4),
wherein gmp3 and gmp 4 are transconductance of the PMOS transistors MP3 and MP4, rds1 and rds2 are source-drain resistances of the PMOS transistors MP1 and MP2, when MP1 and MP2 are in a deep linear region, i.e. Vds is far smaller than Vgs-Vth, MP1 and MP2 are similar to a controllable linear resistance, and the resistance rds is:
then, by adjusting the bias voltages Vcon and Vconb of MP1 and MP2, the values of rds1 and rds2 can be controlled, and thus the mirror Ratio of the current mirror load can be controlled, the adjustable range of Ratio being shown in fig. 6.
The output current of PMOS at the end of Vout can be improved by improving the mirror proportion Ratio of the current mirror load, so that Vout can be pulled up, and negative offset voltage is compensated; assuming the offset voltage is Vos, the output compensation current deltaiout to be adjusted can be calculated by (1-6),
ΔIout＝Vos*Gm (1-6)
where Gm is the total transconductance of the op-amp, ΔIout is generated by adjusting the ratio of the current mirror loads, as shown in equations (1-7)
ΔIout＝Iout-Iin＝Iin(Ratio-1) (1-7)
Then, substituting equation (1-4) (1-5) (1-7) into equation (1-6), and assuming gmp rds is much larger than 1, the relationship (1-8) between offset voltage Vos and Vcon can be obtained after simplification:
if the bias voltage Vconb is fixed, the negative offset voltage of the op-amp can be compensated by calibrating the DAC to continuously decrease Vcon. The relationship between vconb=1.5v and the offset voltage to be compensated is shown in fig. 7, and when the offset voltage of the op-amp is-100 mV, the offset voltage to be compensated is 100mV at maximum, and Vcon should be adjusted to 0.75V.
As shown in fig. 8, vcon is controlled by an eight bit digital-to-analog converter calibration DAC circuit 500, where the 500 digital-to-analog converter calibration DAC is composed of 8 current sources 0.5 x i and a resistor string R-2R, and the resolution of the offset voltage calibration Vos is 100 mV/256= 390.625uV. The current sources used by the structure have the same value, and the resistance values only differ by two times, so that the structure can achieve good matching and high precision. The switching of the current source is controlled by eight bits of input data N0-N7, and the output voltage Vcon is determined by equations (1-9):
at the beginning, all switches are turned onAs the down counter counts, the value of N gradually decreases, as does the value of Vcon, decreasing by a factor of 256 per step. As can be seen from fig. 7, vcon should be gradually adjusted from 1.5V to 0.75V to compensate for offset voltage at the input terminal, and the range of Vcon is set from 1.5V to 0.5V in consideration of process angle, power supply and temperature, the resolution of offset voltage calibration Vos becomes 488.28uV, and the relationship between output Vcon and input count value of the calibration DAC is shown in fig. 9.
In the specific calibration process, as shown in fig. 10, PORB is high before the power supply voltage AVDD is powered up, and Vout is pulled down to ground. After the AVDD is powered on, the 300 operational amplifier is connected into the 210 offset self-calibration circuit, and the input end of the 300 operational amplifier is connected to the ground. At this time, since the offset voltage range of the operational amplifier is between [ -50mV,50mV ], the total offset voltage INP-INN of the operational amplifier is within [ -100mV,0mV ], which is a negative offset voltage, so after the automatic calibration circuit is connected, the output of Vout is not changed or is at low level, the counting latches in the 210 self calibration circuit start counting, the output data N <7:0> is reduced step by step from 8'd255, vcon is also gradually reduced, negative voltage is compensated, INP is gradually raised, and each step is increased (I x R)/256. Until the time of Tstop, INP just changes from being smaller than INN to INP > INN, the voltage of Vout crosses 0.5 x vdd, from low level to high level, the counter latch in the self-calibration of 201 stops counting, latches the current calibration DAC code N <7:0> =8'd 245, and the offset error at the input of the op amp is eliminated to below the resolution voltage 488.28uV compensated by the least significant bit LSB of the calibration DAC, so that the calibration process is completed. The operational amplifier can be connected to the normal output stage of the voice coil motor to output high-precision control current.
The foregoing is merely illustrative of the present invention and is not intended to limit the scope of the invention, which is defined by the claims and their equivalents.
Claims (6)
1. The operational amplifier offset self-calibration circuit is characterized by comprising an operational amplifier OPAMP, a counting latch, a comparator, an oscillator and a digital-to-analog converter calibration DAC, wherein the output end of the operational amplifier OPAMP is connected with the negative input end of the comparator, the output end of the comparator is connected with the input end of the oscillator and one input end of the counting latch, the output end of the oscillator is connected with the other input end of the counting latch, the output end of the counting latch is connected with the input end of the digital-to-analog converter calibration DAC, the output end of the digital-to-analog converter calibration DAC is connected with the signal feedback end of the operational amplifier OPAMP, and the input end and the output end of the operational amplifier OPAMP are respectively connected with an output stage circuit of the voice coil motor driving chip;
the operational amplifier OPAMP comprises an input pair pipe MP0a, an input pair pipe MP0b, a bias current IBIAS, a load MOS pipe MN1, a load MOS pipe MN2, a load MOS pipe MN3, a load MOS pipe MN4, a pull-down enabling MOS pipe MN5 and an adjustable current mirror load, wherein a source electrode of the input pair pipe MP0a is connected with a source electrode of the input pair pipe MP0b and the bias current IBIAS, a drain electrode of the input pair pipe MP0a is connected with a source electrode of the load MOS pipe MN1 and a drain electrode of the load MOS pipe MN3, a drain electrode of the input pair pipe MP0b is connected with a source electrode of the load MOS pipe MN2 and a drain electrode of the load MOS pipe MN4, a drain electrode of the load MOS pipe MN2 is connected with an output end of the adjustable current mirror load and a drain electrode of the pull-down enabling MOS pipe MN5, and serves as an output end of the operational amplifier OPAMP, and a source electrode of the load MOS pipe MN3 is connected with a source electrode of the load MOS pipe MN4 and a source electrode of the pull-down enabling MOS pipe 5, and is grounded;
the grid electrode of the input pair tube MP0a and the grid electrode of the input pair tube MP0b are respectively used as the positive electrode input end and the negative electrode input end of the operational amplifier OPAMP;
the adjustable current mirror load comprises a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3 and a PMOS tube MP4, wherein the source electrode of the PMOS tube MP1 is connected with the source electrode of the PMOS tube MP2, the drain electrode of the PMOS tube MP1 is connected with the source electrode of the PMOS tube MP3, the drain electrode of the PMOS tube MP2 is connected with the source electrode of the PMOS tube MP4, the drain electrode of the PMOS tube MP3 is connected with the grid electrode of the PMOS tube MP3 and the grid electrode of the PMOS tube MP4 and is used as the input end of the adjustable current mirror, and the drain electrode of the PMOS tube MP4 is used as the output end of the adjustable current mirror;
the grid electrode of the PMOS tube MP1 and the grid electrode of the PMOS tube MP2 are respectively connected with the bias voltage Vconb and the bias voltage Vcon;
the offset voltage of the operational amplifier OPAMP is within the range of [ -100mV,0mV ].
2. The operational amplifier offset self-calibration circuit applied to a voice coil motor driving chip according to claim 1, wherein a switch POR is connected between an output end of an operational amplifier OPAMP and a negative electrode input end of a comparator, the switch POR is connected with the voice coil motor driving chip, the voice coil motor driving chip is powered on for resetting, the switch POR becomes a high level, and the switch POR is in a closed state.
3. The self-calibration circuit of claim 1, wherein the DAC calibration DAC is an N-bit current mode DAC, and the count latch is an N-bit count latch.
4. The operational amplifier offset self-calibration circuit applied to a voice coil motor driving chip according to claim 1, wherein the output stage circuit of the voice coil motor driving chip comprises a digital-to-analog converter main DAC, a current detection resistor Rsense and an output stage power transistor NM0, wherein the output end of the digital-to-analog converter main DAC is connected with the positive input end of an operational amplifier OPAMP, one end of the current detection resistor Rsense is grounded, the other end of the current detection resistor Rsense is connected with the negative input end of the operational amplifier OPAMP and the source electrode of the output stage power transistor NM0, and the grid electrode of the output stage power transistor NM0 is connected with the output end of the operational amplifier OPAMP;
a fourth switch is connected between the current detection resistor Rsense and the negative input end of the operational amplifier OPAMP, a third switch is connected between the digital-to-analog converter main DAC and the positive input end of the operational amplifier OPAMP, a fifth switch is connected between the grid electrode of the output stage power transistor NM0 and the output end of the operational amplifier OPAMP, and the control ends of the third switch, the fourth switch and the fifth switch are connected with the output end COB of the first inverter;
the positive input end of the operational amplifier OPAMP is grounded through a first switch, the negative input end of the operational amplifier OPAMP is grounded through a second switch, and the control ends of the first switch and the second switch are connected with the output end CO of the second inverter.
5. The operational amplifier offset self-calibration circuit applied to the voice coil motor driving chip according to claim 1, wherein the grid electrode of the load MOS tube MN1 and the grid electrode of the load MOS tube MN2 are both connected with a bias voltage Vnbias1, and the grid electrode of the load MOS tube MN3 and the grid electrode of the load MOS tube MN4 are both connected with a bias voltage Vnbias2.
6. The operational amplifier offset self-calibration circuit applied to a voice coil motor driving chip according to claim 1, wherein the digital-to-analog converter calibrates the DAC to an eight-bit R2R architecture.
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| CN109696630B (en) * | 2018-12-20 | 2021-01-26 | 聚辰半导体股份有限公司 | Voice coil motor parameter self-detection method |
| CN110022110B (en) * | 2019-05-05 | 2021-01-26 | 聚辰半导体股份有限公司 | Voice coil motor damping control circuit |
| CN112083330B (en) * | 2020-09-16 | 2023-06-09 | 聚辰半导体股份有限公司 | Device and method for measuring voice coil motor parameters |
| CN112366999B (en) * | 2020-11-02 | 2022-03-08 | 普冉半导体(上海)股份有限公司 | Voice coil motor driving circuit and method thereof |
| CN113726339B (en) * | 2021-08-19 | 2022-06-03 | 江苏润石科技有限公司 | Error feedback-based offset voltage reduction method and data converter |
| CN115033047B (en) * | 2022-06-22 | 2023-07-07 | 福州大学 | Band gap reference voltage source with single point calibration |
| CN115118230A (en) * | 2022-07-18 | 2022-09-27 | 普源精电科技股份有限公司 | Combined operational amplifier circuit, chip and signal processing device |
| US20240223082A1 (en) * | 2023-01-04 | 2024-07-04 | Texas Instruments Incorporated | Determination of values indicative of multiple passive components connected to a device pin |
| CN117978167B (en) * | 2024-03-29 | 2024-06-25 | 杰华特微电子股份有限公司 | Multi-operational amplifier rotation calibration method, calibration circuit and multi-channel driving system |
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