TWI611534B - 適用於可堆疊式半導體組體之具有凹穴的互連基板、其製作方法及垂直堆疊式半導體組體 - Google Patents

適用於可堆疊式半導體組體之具有凹穴的互連基板、其製作方法及垂直堆疊式半導體組體 Download PDF

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TWI611534B
TWI611534B TW105127335A TW105127335A TWI611534B TW I611534 B TWI611534 B TW I611534B TW 105127335 A TW105127335 A TW 105127335A TW 105127335 A TW105127335 A TW 105127335A TW I611534 B TWI611534 B TW I611534B
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metal
layer
core layer
cavity
circuit
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TW105127335A
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TW201711149A (zh
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文強 林
王家忠
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鈺橋半導體股份有限公司
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Abstract

本發明之互連基板於凹穴周圍處設有垂直連接通道，其特徵在於，接觸墊由凹穴顯露，且垂直連接通道由金屬柱與金屬化盲孔結合而成。該凹穴包括有核心層中之凹口及加強層中之穿口。設置於核心層頂面上之金屬柱係封埋於加強層中，且電性連接至鄰近核心層底面之增層電路。用於垂直連接之金屬柱，其可利用凹口之深度以降低金屬柱所需之最小高度。增層電路藉由金屬化盲孔，電性連接至金屬柱，並提供從凹穴顯露之接觸墊，以用於連接元件。

Description

適用於可堆疊式半導體組體之具有凹穴的互連基板、其 製作方法及垂直堆疊式半導體組體
本發明是關於一種互連基板、其製作方法及垂直堆疊式半導體組體，尤指一種具有凹穴之互連基板，其中該凹穴被一系列垂直連接通道所環繞，且該些垂直連接通道係由金屬柱及金屬化盲孔組合而成。
多媒體裝置之市場趨勢係傾向於更迅速且更薄型化之設計需求。其中一種方法是將多個元件堆疊於線路板上，以改善電性效能並達到最小外觀(form-factor)。如美國專利案號7,894,203即基於此目的而揭露一種具有凹穴之線路板，其凹穴周圍設有電鍍金屬柱。然而，由於很難藉由電鍍形成具有高縱橫尺寸比(aspect ratio opening)之金屬柱(即高細的金屬柱)，因此金屬柱處的空隙或接合強度不足皆可能導致未連接I/O、元件失效及生產良率低等問題。此外，美國專利案號7,989,950則是於基板上接置焊球以作為垂直連接通道，再以模封材包覆該些垂直連接通道，並形成凹穴。然而，由於焊球通常於回焊後會形成球狀，故符合所需高度之大顆焊球會導致線 路板尺寸變大。因此，使用焊球作為垂直連接並無法滿足行動裝置的嚴苛要求。
為了上述理由及以下所述之其他理由，目前亟需發展一種具有凹穴的新式線路板，以達到超高封裝密度、高信號完整度、小尺寸及高生產良率之要求。
本發明之主要目的係提供一種互連基板，其具有一凹穴及複數個設於凹穴周圍之垂直連接通道，適用於製作超薄的垂直堆疊式半導體組體。
本發明之另一目的係提供一種互連基板，其凹穴係由核心層中的凹口及加強層中之穿口組合而成，如此一來凹穴便可達到足以容納半導體元件之深度。
本發明之再一目的係提供一種互連基板，其設於凹穴周圍之一系列垂直連接通道係由金屬柱及金屬化盲孔組合而成。由於金屬柱的高度加上盲孔的深度可符合或大於凹穴的深度，故該互連基板可對堆疊設置的元件提供垂直互連路由，且具有高生產良率及低成本之優點。
依據上述及其他目的，本發明提供一種互連基板，其包括一核心層、一增層電路、一加強層、一系列金屬柱及一凹穴。該核心層具有第一表面及相反第二表面。該增層電路設置於核心層之第一表面上，並具有背向核心層第一表面之一外表面。該加強層設置於核心層之第二表面上，並具有背向核心層第二表面之一外表面。所述金屬柱封埋於加強層中，並由加強層之外表面顯露，且藉由核心層中的金屬化盲孔電性連接至增層電路。該凹穴包含加強層中之穿口及核心層中之凹口，且具有一底表面及側壁，該底表面背向增層電路之外表面，而該些側壁由底表面延伸至加強層 之外表面。該穿口及該凹口相互對準。該增層電路具有一系列接觸墊，且該些接觸墊由凹穴之底表面顯露。
於另一態樣中，本發明提供一種垂直堆疊式半導體組體，其包括上述互連基板、一第一半導體元件及一第二半導體元件。該第一半導體元件設置於凹穴中，並藉由從凹穴底表面顯露之接觸墊，電性耦接至互連基板。該第二半導體元件設置於增層電路之外表面或加強層之外表面上，並藉由增層電路或金屬柱，電性耦接至互連基板。
於再一態樣中，本發明提供一種互連基板之製作方法，其包括下述步驟：於一金屬載板之一表面上形成一金屬凸層；形成一核心層，其覆蓋該金屬凸層及該金屬載板之剩餘表面，且該核心層具有背向金屬載板之第一表面及鄰近金屬載板之相反第二表面；移除金屬載板之一部分，以形成一系列金屬柱及一金屬塊，該金屬塊係對準該金屬凸層；由核心層之第一表面形成一增層電路，該第一增層電路具有背向核心層第一表面之一外表面；形成一加強層，其覆蓋核心層之第二表面及金屬塊與金屬柱之側壁，該加強層具有背向核心層第二表面之一外表面；以及移除金屬塊及金屬凸層，以形成一凹穴，該凹穴包含一穿口及一凹口，該穿口位於加強層中，而該凹口位於該核心層中，同時該凹穴具有一底表面及側壁，其側壁係由該底表面延伸至加強層之外表面。
除非特別描述或必須依序發生之步驟，上述步驟之順序並無限制於以上所列，且可根據所需設計而變化或重新安排。
本發明之互連基板製作方法具有許多優點。舉例來說，於核心層中形成凹口的作法是特別具有優勢的，其原因在於，用於垂直連接之金屬柱，其可利用凹口之深度以降低金屬柱所需之最小高度。由於第一半導體元件可設置於核心層之凹口處，並延伸至加強層之穿口，故無需為了達到 超薄垂直堆疊半導體組體的特色而對第一半導體元件進行額外的輪磨(grinding)或研磨(lapping)步驟。於核心層上形成金屬柱可提供進行封裝疊加(package-on-package)互連製程時所需的垂直路由，藉此可將第二半導體元件設置於加強層上，並藉由增層電路使第二半導體元件電性耦接至凹穴中之第一半導體元件。此外，第二半導體元件亦可接置於增層電路之外表面上，藉此核心層第一表面上之增層電路可於第一及第二半導體元件間提供最短的互連距離。
本發明之上述及其他特徵與優點可藉由下述較佳實施例之詳細敘述更加清楚明瞭。
100、200、300、400、500、600‧‧‧互連基板
11‧‧‧金屬載板
111‧‧‧金屬塊
113‧‧‧金屬柱
12‧‧‧金屬凸層
121、503‧‧‧側壁
13‧‧‧輔助金屬墊
20‧‧‧凹口
21‧‧‧核心層
212‧‧‧第一表面
213、313、323‧‧‧盲孔
214‧‧‧第二表面
30‧‧‧增層電路
302、402‧‧‧外表面
31‧‧‧金屬層
31’‧‧‧被覆層
311‧‧‧路由線
315‧‧‧導線
316‧‧‧第一導線
317‧‧‧金屬化盲孔
318‧‧‧第一金屬化盲孔
319‧‧‧接觸墊
322‧‧‧介電層
326‧‧‧第二導線
328‧‧‧第二金屬化盲孔
40‧‧‧穿口
41‧‧‧加強層
413‧‧‧開孔
50‧‧‧凹穴
502‧‧‧底表面
61‧‧‧第一半導體元件
63‧‧‧第二半導體元件
81、85‧‧‧凸塊
83‧‧‧焊球
91‧‧‧樹脂密封元件
參考隨附圖式，本發明可藉由下述較佳實施例之詳細敘述更加清楚明瞭，其中：圖1及2分別為本發明第一實施態樣中，於金屬載板上形成金屬凸層之剖視圖及底部立體示意圖；圖3為本發明第一實施態樣中，圖1結構上形成核心層及金屬層之剖視圖；圖4及5分別為本發明第一實施態樣中，圖3結構上形成盲孔之剖視圖及頂部立體示意圖；圖6為本發明第一實施態樣中，圖4結構上形成被覆層之剖視圖；圖7及8分別為本發明第一實施態樣中，將圖6結構中之一部分金屬載板移除之剖視圖及頂部立體示意圖；圖9及10分別為本發明第一實施態樣中，圖7及8之結構上形成加強層之剖視圖及頂部立體示意圖； 圖11及12分別為本發明第一實施態樣中，圖9及10之結構上形成導線之剖視圖及底部立體示意圖；圖13及14分別為本發明第一實施態樣中，圖11及12之結構上形成凹穴，以製作完成互連基板之剖視圖及頂部立體示意圖；圖15為本發明第一實施態樣中，將第一半導體元件電性耦接至圖13互連基板之半導體組體剖視圖；圖16為本發明第一實施態樣中，將第二半導體元件電性耦接至圖15半導體組體之垂直堆疊式半導體組體剖視圖；圖17為本發明第一實施態樣中，將第二半導體元件電性耦接至圖15半導體組體之另一垂直堆疊式半導體組體剖視圖；圖18為本發明第二實施態樣中，金屬載板上形成金屬凸層及一系列輔助金屬墊之剖視圖；圖19為本發明第二實施態樣中，圖18結構上形成核心層之剖視圖；圖20為本發明第二實施態樣中，圖19結構上形成盲孔之剖視圖；圖21為本發明第二實施態樣中，圖20結構上形成被覆層之剖視圖；圖22為本發明第二實施態樣中，由圖21結構形成一金屬塊、金屬柱及導線之剖視圖；圖23為本發明第二實施態樣中，圖22之結構上形成加強層之剖視圖；圖24為本發明第二實施態樣中，圖23之結構上形成凹穴，以製作完成互連基板之剖視圖；圖25為本發明第二實施態樣中，將第一半導體元件電性耦接至圖24互連基板之半導體組體剖視圖；圖26為本發明第二實施態樣中，將第二半導體元件電性耦接至圖25半導體組體之垂直堆疊式半導體組體剖視圖； 圖27為本發明第二實施態樣中，將第二半導體元件電性耦接至圖25半導體組體之另一垂直堆疊式半導體組體剖視圖；圖28為本發明第三實施態樣中，圖18之結構上形成路由線之剖視圖；圖29為本發明第三實施態樣中，圖28結構上形成核心層之剖視圖；圖30為本發明第三實施態樣中，圖29結構上形成盲孔之剖視圖；圖31為本發明第三實施態樣中，圖30結構上形成導線之剖視圖；圖32為本發明第三實施態樣中，由圖31結構形成一金屬塊及金屬柱之剖視圖；圖33為本發明第三實施態樣中，圖32之結構上形成加強層之剖視圖；圖34為本發明第三實施態樣中，圖33之結構上形成凹穴，以製作完成互連基板之剖視圖；圖35為本發明第三實施態樣中，將第一半導體元件電性耦接至圖34互連基板之半導體組體剖視圖；圖36為本發明第三實施態樣中，將第二半導體元件電性耦接至圖35半導體組體之垂直堆疊式半導體組體剖視圖；圖37為本發明第三實施態樣中，將第二半導體元件電性耦接至圖35半導體組體之另一垂直堆疊式半導體組體剖視圖；圖38為本發明第四實施態樣中，圖1結構上形成核心層且於核心層中形成盲孔之剖視圖；圖39為本發明第四實施態樣中，圖38結構上形成第一導線之剖視圖；圖40為本發明第四實施態樣中，圖39結構上形成介電層並於介電層中形成盲孔之剖視圖；圖41為本發明第四實施態樣中，圖40結構上形成第二導線之剖視圖； 圖42為本發明第四實施態樣中，由圖41結構形成一金屬塊及金屬柱之剖視圖；圖43為本發明第四實施態樣中，圖42之結構上形成加強層之剖視圖；圖44為本發明第四實施態樣中，圖43之結構上形成凹穴之剖視圖；圖45為本發明第四實施態樣中，圖44之結構上形成盲孔，以製作完成互連基板之剖視圖；圖46為本發明第四實施態樣中，將第一半導體元件電性耦接至圖45互連基板之半導體組體剖視圖；圖47為本發明第四實施態樣中，將第二半導體元件電性耦接至圖46半導體組體之垂直堆疊式半導體組體剖視圖；圖48為本發明第四實施態樣中，將第二半導體元件電性耦接至圖46半導體組體之另一垂直堆疊式半導體組體剖視圖；圖49為本發明第五實施態樣中，金屬柱凸出加強層之另一互連基板剖視圖；以及圖50為本發明第六實施態樣中，加強層中形成開孔以顯露金屬柱之再一互連基板剖視圖。
在下文中，將提供一實施例以詳細說明本發明之實施態樣。本發明之優點以及功效將藉由本發明所揭露之內容而更為顯著。在此說明所附之圖式係簡化過且做為例示用。圖式中所示之元件數量、形狀及尺寸可依據實際情況而進行修改，且元件的配置可能更為複雜。本發明中也可進行其他方面之實踐或應用，且不偏離本發明所定義之精神及範疇之條件下，可進行各種變化以及調整。
[實施例1]
圖1-14為本發明第一實施態樣中，一種互連基板之製作方法圖，該互連基板包括一核心層、一增層電路、一加強層、一系列金屬柱及一凹穴。
圖1及2分別為金屬載板11上形成金屬凸層12之剖視圖及底部立體示意圖。金屬載板11及金屬凸層12通常由銅、鋁、鎳、不銹鋼、或其他金屬或合金製成。金屬凸層12之材料可與金屬載板11相同或相異。金屬載板11之厚度可為0.05毫米至0.5毫米(較佳為0.1毫米至0.2毫米)，而金屬凸層12之厚度可為10微米至100微米。於本實施態樣中，該金屬載板11係由銅所製成並具有0.15毫米厚度，而金屬凸層12係由銅所製成並具有30微米厚度。金屬凸層12可藉由圖案化沉積法形成於金屬載板11之一表面上，如電鍍、無電電鍍、蒸鍍、濺鍍或其組合，或者藉由蝕刻或機械刻蝕(carving)而形成。
圖3為金屬載板11與金屬凸層12上形成核心層21及金屬層31之剖視圖。該核心層21及該金屬層31通常係藉由層壓或塗佈方式形成。核心層21可由環氧樹脂、玻璃環氧樹脂、聚醯亞胺、或其類似物所製成，而金屬層31通常為銅層。核心層21接觸金屬凸層12及金屬載板11之剩餘表面，並由下方覆蓋並側向延伸於金屬凸層12及金屬載板11之剩餘表面上，同時於側面方向上環繞且同形披覆金屬凸層12之側壁121。據此，核心層21之第一表面212係背向金屬載板11及金屬凸層12，且其相對之第二表面214則係鄰接並接觸金屬載板11。金屬層31係接觸核心層21之第一表面212，並由下方覆蓋核心層21之第一表面212。
圖4及5分別為形成盲孔213之剖視圖及底部立體示意圖，以由下方顯露金屬載板11及金屬凸層12之選定部位。盲孔213可藉由各種技術形成，其包括雷射鑽孔、電漿蝕刻、及微影技術，且通常具有50微米之直徑。可 使用脈衝雷射提高雷射鑽孔效能。或者，可使用掃描雷射光束，並搭配金屬光罩。盲孔213係延伸穿過核心層21及金屬層31，並對準金屬載板11及金屬凸層12之選定部位。
圖6為金屬層31上及盲孔213內形成被覆層31’之剖視圖。被覆層31’自金屬載板11及金屬凸層12朝下延伸，並填滿盲孔213，以形成直接接觸金屬載板11及金屬凸層12之金屬化盲孔317，同時側向延伸於核心層21上。
被覆層31’可藉由各種技術沉積為單層或多層，如電鍍、無電電鍍、蒸鍍、濺鍍或其組合。舉例來說，首先藉由將該結構浸入活化劑溶液中，使核心層21與無電鍍銅產生觸媒反應，接著以無電電鍍方式被覆一薄銅層作為晶種層，然後以電鍍方式將所需厚度之第二銅層形成於晶種層上。或者，於晶種層上沉積電鍍銅層前，該晶種層可藉由濺鍍方式形成如鈦/銅之晶種層薄膜。
圖7及8分別為形成一金屬塊111及陣列式金屬柱113之剖視圖及頂部立體示意圖。在此，可藉由如微影技術及濕蝕刻方式，移除金屬載板11之選定部位，以形成金屬塊111及金屬柱113。金屬塊111係對準金屬凸層12，並由上方覆蓋金屬凸層12，而金屬柱113則位於核心層21之第二表面214上，並電性連接至金屬化盲孔317。
圖9及10分別為於核心層21之外露第二表面214上形成加強層41之剖視圖及頂部立體示意圖。加強層41通常係透過樹脂密封材之印刷或模封(molding)製程而形成，以由上方覆蓋核心層21之第二表面214，並於側面方向上環繞、同形披覆且覆蓋金屬塊111及金屬柱113之側壁。於此圖中，該加強層14之厚度係與金屬塊111及金屬柱113之厚度相同。
圖11及12分別為藉由金屬圖案化製程形成導線315於核心層21上之剖視圖及底部立體示意圖。在此，可使用各種技術，對金屬層31及被覆層31’進行圖案化，以形成導線315，如濕蝕刻、電化學蝕刻、雷射輔助蝕刻或其組合，並使用蝕刻光罩(圖未示)，以定義出導線315，其中導線315包含有核心層21中之金屬化盲孔317，並側向延伸於核心層21之第一表面212上。因此，導線315可提供X及Y方向的水平信號路由以及穿過盲孔213的垂直路由。
此階段已製作完成之增層電路30包含有導線315，其中導線315藉由核心層21中之金屬化盲孔317電性連接至金屬柱113。
圖13及14分別為移除金屬塊111及金屬凸層12之剖視圖及頂部立體示意圖。金屬塊111及金屬凸層12可藉由各種技術移除，如濕蝕刻、電化學蝕刻或雷射。因此，可形成一凹穴50，其係由核心層21中之一凹口20及加強層41中之一穿口40所組成。該穿口40是對準於凹口20，以顯露凹口20處之金屬化盲孔317。
據此，如圖13及14所示，已完成之互連基板100包括一系列金屬柱113、一核心層21、一增層電路30、一加強層41及一凹穴50。該增層電路30設置於核心層21之第一表面212上，其具有背向核心層21第一表面212之一外表面302，且包含位於核心層21中之金屬化盲孔317。一部分的金屬化盲孔317對準並電性連接至金屬柱113，而其他金屬化盲孔317則對準凹穴50，並具有從凹穴50顯露之表面，以作為連接元件用之接觸墊319。加強層41設置於核心層21之第二表面214上，且具有背向核心層21第二表面214之一外表面402。金屬柱113封埋於加強層41中，並由加強層41之外表面402顯露，且藉由核心層21中之金屬化盲孔317電性連接至增層電路30。凹穴50具有一底表面502及側壁503，其中底表面502與增層電路30之外表面302保 持距離，而側壁503由底表面502延伸至加強層41之外表面402。於此圖中，該凹穴50之底表面502與凹口20處之金屬化盲孔317的顯露表面呈實質上共平面。然而，於某些實例中，凹口20處之金屬化盲孔317的顯露表面可能低於凹穴50之底表面502，這是由於移除金屬凸層12時可能稍微蝕刻到金屬化盲孔317。無論如何，增層電路30之接觸墊319會由凹穴50之底表面502顯露。
圖15為半導體組體之剖視圖，其係將第一半導體元件61電性耦接至圖13之互連基板100。第一半導體元件61係設置於互連基板100之凹穴50中，並藉由如熱壓、迴焊、或熱超音波接合技術，經由凸塊81電性耦接至增層電路30之接觸墊319。在此，凸塊81可為銅柱、錫柱、金柱或其他導電凸塊。此外，可選擇性提供一樹脂密封元件91，以覆蓋凹穴50之底表面502，且由凹穴50之底表面502延伸並填充第一半導體元件61未佔據的空間。
圖16為垂直堆疊式半導體組體之剖視圖，其係將第二半導體元件63接置於圖15之半導體組體上。該第二半導體元件63設置於加強層41之外表面402上，並藉由與金屬柱113接觸之焊球83電性耦接至互連基板100。據此，可製作完成封裝疊加(package-on-package)組體，其中第二半導體元件63係藉由金屬柱113及增層電路30電性連接至第一半導體元件61。
圖17為另一垂直堆疊式半導體組體之剖視圖，其係將第二半導體元件63接置於圖15之半導體組體上。該第二半導體元件63設置於增層電路30之外表面302上，並藉由與增層電路30之導線315接觸的凸塊85電性耦接至互連基板100。據此，可製作完成面朝面組體，其中第二半導體元件63係藉由第一半導體元件61與第二半導體元件63間的增層電路30，而與第一半導體元件61面朝面地相互電性連接。
[實施例2]
圖18-24為本發明第二實施態樣之互連基板製作方法圖，其核心層中更設有輔助金屬墊。
為了簡要說明之目的，上述實施例1中任何可作相同應用之敘述皆併於此，且無須再重複相同敘述。
圖18為金屬載板11上形成金屬凸層12及陣列式輔助金屬墊13之剖視圖。金屬凸層12及輔助金屬墊13係自金屬載板11之一表面朝向下方向延伸，且具有相同厚度。輔助金屬墊13之材料可與金屬凸層12之材料相同，且可藉由圖案化沉積法形成，如電鍍、無電電鍍、蒸鍍、濺鍍或其組合，或者藉由蝕刻或機械刻蝕而形成。
圖19為金屬載板11、金屬凸層12及輔助金屬墊13上形成核心層21之剖視圖。核心層21接觸金屬載板11、金屬凸層12及輔助金屬墊13，並由下方覆蓋金屬載板11、金屬凸層12及輔助金屬墊13，同時於側面方向上環繞且同形披覆金屬凸層12及輔助金屬墊13之側壁。
圖20為形成盲孔213以由下方顯露金屬凸層12及輔助金屬墊13選定部位之剖視圖。盲孔213延伸穿過核心層21，並對準金屬凸層12及輔助金屬墊13之選定部位。
圖21為核心層21上及盲孔213內形成被覆層31’之剖視圖。被覆層31’自金屬凸層12及輔助金屬墊13朝下延伸，並填滿盲孔213，以形成直接接觸金屬凸層12及輔助金屬墊13之金屬化盲孔317，同時側向延伸於核心層21之第一表面212上。
圖22為藉由移除金屬載板11及被覆層31’選定部位而形成一金屬塊111、陣列式金屬柱113及導線315之剖視圖。金屬塊111係對準金屬凸層12，並由上方覆蓋金屬凸層12。金屬柱113係對準並電性連接至輔助金屬墊13。金屬柱113底面處之直徑可與輔助金屬墊13頂面處之直徑相同或相異。 導線315包含有核心層21中之金屬化盲孔317，並側向延伸於核心層21之第一表面212上。
圖23為核心層21之外露第二表面214上形成加強層41之剖視圖。加強層41係由上方覆蓋核心層21之第二表面214，並於側面方向上環繞、同形披覆且覆蓋金屬塊111及金屬柱113之側壁。
圖24為移除金屬塊111及金屬凸層12之剖視圖。藉此，可形成一凹穴50，其係由核心層21中之一凹口20及加強層41中之一穿口40所組成。該凹口20之深度實質上相等於輔助金屬墊13之厚度，且該穿口40是對準於凹口20。
據此，如圖24所示，已完成之互連基板200包括一系列金屬柱113、一系列輔助金屬墊13、一核心層21、一增層電路30、一加強層41及一凹穴50。增層電路30包含有導線315，且導線315電性連接至輔助金屬墊13並具有從凹穴50顯露之選定部位，以作為連接元件用之接觸墊319，同時導線315側向延伸於核心層21之第一表面212上。加強層41設置於核心層21之第二表面214上，且覆蓋金屬柱113之側壁。輔助金屬墊13係封埋於核心層21中，並電性連接至金屬柱113及金屬化盲孔317，且位於金屬柱113與金屬化盲孔317之間。
圖25為半導體組體之剖視圖，其係將第一半導體元件61電性耦接至圖24之互連基板200。第一半導體元件61係設置於互連基板200之凹穴50中，並藉由凸塊81電性耦接至增層電路30之接觸墊319。
圖26為垂直堆疊式半導體組體之剖視圖，其係將第二半導體元件63電性耦接至圖25之半導體組體。該第二半導體元件63是藉由與金屬柱113接觸之焊球83接置於互連基板200上。據此，該第二半導體元件63係藉由金屬柱113、輔助金屬墊13及增層電路30電性連接至第一半導體元件61。
圖27為另一垂直堆疊式半導體組體之剖視圖，其係將第二半導體元件63電性耦接至圖25之半導體組體。該第二半導體元件63係藉由第一半導體元件61與第二半導體元件63間的增層電路30，而與第一半導體元件61面朝面地相互電性連接。
[實施例3]
圖28-34為本發明第三實施態樣之互連基板製作方法圖，其設有從凹穴顯露之路由電路。
為了簡要說明之目的，上述實施例中任何可作相同應用之敘述皆併於此，且無須再重複相同敘述。
圖28為圖18中的金屬凸層12上形成路由線311之剖視圖。所述路由線311通常由銅製成，且可經由各種技術進行圖案化沉積，如電鍍、無電電鍍、蒸鍍、濺鍍或其組合，或者藉由薄膜沉積而後進行金屬圖案化步驟而形成。
圖29為金屬載板11、金屬凸層12、輔助金屬墊13及路由線311上形成核心層21之剖視圖。核心層21接觸金屬載板11、金屬凸層12、輔助金屬墊13及路由線311，並由下方覆蓋金屬載板11、金屬凸層12、輔助金屬墊13及路由線311，同時於側面方向上環繞且同形披覆金屬凸層12、輔助金屬墊13及路由線311之側壁。
圖30為形成盲孔213以由下方顯露輔助金屬墊13及路由線311選定部位之剖視圖。盲孔213延伸穿過核心層21，並對準輔助金屬墊13及路由線311之選定部位。
圖31為藉由金屬沉積及金屬圖案化製程形成導線315於核心層21上之剖視圖。導線315自輔助金屬墊13及路由線311朝下延伸，並填滿盲孔 213，以形成直接接觸輔助金屬墊13及路由線311之金屬化盲孔317，同時側向延伸於核心層21之第一表面212上。
圖32為藉由移除金屬載板11選定部位而形成一金屬塊111及陣列式金屬柱113之剖視圖。金屬塊111係對準金屬凸層12，並由上方覆蓋金屬凸層12。金屬柱113係對準並電性連接至輔助金屬墊13。
圖33為核心層21上形成加強層41之剖視圖。加強層41覆蓋核心層21之外露第二表面214，並於側面方向上環繞、同形披覆且覆蓋金屬塊111及金屬柱113之側壁。
圖34為移除金屬塊111及金屬凸層12之剖視圖。藉此，可形成一凹穴50，其係由核心層21中之一凹口20及加強層41中之一穿口40所組成。
據此，如圖34所示，已完成之互連基板300包括一系列金屬柱113、一系列輔助金屬墊13、一核心層21、一增層電路30、一加強層41及一凹穴50。於此圖中，該增層電路30包括有路由線311及導線311，其中路由線311是從凹穴50顯露，以提供連接元件用之接觸墊319，而導線315則電性連接至輔助金屬墊13及路由線311。
圖35為半導體組體之剖視圖，其係將第一半導體元件61電性耦接至圖34之互連基板300。第一半導體元件61係設置於互連基板300之凹穴50中，並藉由凸塊81電性耦接至增層電路30之接觸墊319。
圖36為垂直堆疊式半導體組體之剖視圖，其係將第二半導體元件63接置於圖35之半導體組體上。該第二半導體元件63是藉由與金屬柱113接觸之焊球83電性耦接至互連基板300。
圖37為另一垂直堆疊式半導體組體之剖視圖，其係將第二半導體元件63接置於圖35之半導體組體上。該第二半導體元件63係藉由第一半導 體元件61與第二半導體元件63間的增層電路30，而與第一半導體元件61面朝面地相互電性連接。
[實施例4]
圖38-45為本發明第四實施態樣之互連基板製作方法圖，其設有多層結構之增層電路。
為了簡要說明之目的，上述實施例中任何可作相同應用之敘述皆併於此，且無須再重複相同敘述。
圖38為圖1之金屬載板11及金屬凸層12上形成核心層21且於核心層21中形成盲孔213之剖視圖。核心層21接觸金屬載板11及金屬凸層12，並由下方覆蓋金屬載板11及金屬凸層12，同時於側面方向上環繞且同形披覆金屬凸層12之側壁。盲孔213延伸穿過核心層21，並對準金屬載板11之選定部位。
圖39為藉由金屬沉積及金屬圖案化製程形成第一導線316於核心層21上之剖視圖。第一導線316自金屬載板11朝下延伸，並填滿盲孔213，以形成直接接觸金屬載板11之第一金屬化盲孔318，同時側向延伸於核心層21上。
圖40為核心層21及第一導線316上形成介電層322且於介電層322中形成盲孔323之剖視圖。該介電層322通常係藉由層壓或塗佈方式形成，其接觸核心層21及第一導線316，並由下方覆蓋並側向延伸於核心層21及第一導線316上。介電層322通常具有50微米之厚度，且可由環氧樹脂、玻璃環氧樹脂、聚醯亞胺、或其類似物所製成。於設置介電層322後，形成延伸穿過介電層322之盲孔323，以顯露第一導線316之選定部位。
圖41為藉由金屬沉積及金屬圖案化製程形成第二導線326於介電層322上之剖視圖。第二導線326自第一導線316朝下延伸，並填滿盲孔323， 以形成直接接觸第一導線316之第二金屬化盲孔328，同時側向延伸於介電層322上。
於此階段，已製作完成多層結構之增層電路30，其包括第一導線316、介電層322及第二導線326。
圖42為藉由移除金屬載板11選定部位而形成一金屬塊111及陣列式金屬柱113之剖視圖。金屬塊111係對準金屬凸層12，並由上方覆蓋金屬凸層12。金屬柱113係藉由第一金屬化盲孔318電性連接至增層電路30。
圖43為核心層21上形成加強層41之剖視圖。加強層41係由上方覆蓋核心層21，並於側面方向上環繞、同形披覆且覆蓋金屬塊111及金屬柱113之側壁。
圖44為移除金屬塊111及金屬凸層12之剖視圖。藉此，可形成一凹穴50，其係由核心層21中之一凹口20及加強層41中之一穿口40所組成。
圖45為形成盲孔215以從凹穴50顯露第一導線316選定部位之剖視圖。所述盲孔215對準第一導線316之選定部位，並由凹穴50之底表面502延伸入核心層21。因此，第一導線316之顯露部位可作為連接元件用之接觸墊319。
據此，如圖45所示，已完成之互連基板400包括金屬柱113、一核心層21、一增層電路30、一加強層41及一凹穴50。於此圖中，該增層電路30為多層結構，其包括第一導線316、一介電層322及第二導線326。
圖46為半導體組體之剖視圖，其係將第一半導體元件61電性耦接至圖45之互連基板400。第一半導體元件61係設置於互連基板400之凹穴50中，並藉由凸塊81電性耦接至增層電路30之接觸墊319。
圖47為垂直堆疊式半導體組體之剖視圖，其係將第二半導體元件63接置於圖46之半導體組體上。該第二半導體元件63是藉由與金屬柱113接觸之焊球83墊性耦接至互連基板400。
圖48為另一垂直堆疊式半導體組體之剖視圖，其係將第二半導體元件63接置於圖46之半導體組體上。該第二半導體元件63係藉由第一半導體元件61與第二半導體元件63間的增層電路30，而與第一半導體元件61面朝面地相互電性連接。
[實施例5]
圖49為本發明第五實施態樣之互連基板剖視圖。於本實施態樣中，該互連基板500與實施例1所述相似，惟不同處在於，(i)該增層電路30為多層結構，且(ii)金屬柱113延伸超過加強層41之外表面402，並具有未被加強層41覆蓋且由加強層41外表面402凸出之選定部位。
[實施例6]
圖50為本發明第六實施態樣之互連基板剖視圖。於本實施態樣中，該互連基板600與實施例1所述相似，惟不同處在於，(i)該增層電路30為多層結構，且(ii)加強層41之厚度大於金屬柱113厚度，並具有開孔413以顯露金屬柱113之選定部位。
上述互連基板及半導體組體僅為說明範例，本發明尚可透過其他多種實施例實現。此外，上述實施例可基於設計及可靠度之考量，彼此混合搭配使用或與其他實施例混合搭配使用。舉例來說，互連基板可包括多個排列成陣列形狀之凹穴，且每一凹穴中可容置一半導體元件。此外，增層電路亦可包括額外的接觸墊，其係由額外凹穴顯露，用以與額外的半導體元件電性連接。
如上述實施態樣所示，本發明建構出一種獨特之互連基板，其包括一核心層、一增層電路、一加強層、一系列金屬柱及一凹穴，且選擇性地更包括一系列輔助金屬墊。藉由本發明之製法，該加強層/金屬柱與增層電路係形成於核心層之兩相反側上，且加強層與增層電路間不具有黏著劑。為方便下文敘述，將核心層第一表面所面向的方向定義為第一方向，而核心層之相反第二表面所面向的方向定義為第二方向。核心層第一表面上之增層電路具有面向第一方向之外表面，而核心層第二表面上之加強層則具有面向第二方向之外表面。
金屬柱可於凹穴周圍提供垂直電性連接。於一較佳實施態樣中，金屬柱係藉由移除一金屬載板之選定部位而形成，其中該金屬載板上設有一金屬凸層及選擇性的輔助金屬墊，且該移除步驟係於提供核心層於第一方向上覆蓋並接觸金屬載板及金屬凸層後進行。據此，金屬柱即可設置於核心層之第二表面上，並接觸核心層中之選擇性輔助金屬墊或金屬化盲孔。
加強層覆蓋金屬柱之側壁，且其厚度相等於或不同於金屬柱之高度。例如，加強層之外表面可與金屬柱之顯露表面於第二方向上呈實質上共平面。或者，加強層的厚度可能大於或小於金屬柱之高度。於加強層具有較大厚度的態樣中，該加強層中形成有開孔，其由加強層之外表面延伸至金屬柱，以於第二方向上顯露金屬柱之選定部位。於加強層具有較小厚度之另一態樣中，該些金屬柱係於第二方向上延伸超過加強層之外表面，並具有未被加強層覆蓋且凸出於加強層外表面之顯露部位。據此，金屬柱係由加強層之外表面顯露，以提供進行下一級連接之電性接點。較佳為，該加強層是由任何具有足夠機械強度之材料所製成，且其側向延伸至互連基板之外圍邊緣。如此一來，加強層可對互連基板提供機械支撐力，以避免彎翹。
凹穴之深度較佳是大於金屬柱的高度，且加強層與核心層側向環繞該凹穴。更具體地說，於凹穴朝上的方位中，該凹穴之底表面是低於金屬柱之底側。此外，凹穴可藉由移除金屬凸層及金屬載板之對應部位而形成。因此，凹穴包括有加強層中之穿口及核心層中之凹口。於一較佳實施態樣中，凹口之深度是小於核心層之厚度，而穿口之深度則等於加強層之厚度。穿口與凹口可具有相同尺寸，且穿口之側壁可與凹口側壁齊平。然而，於某些態樣中，穿口之尺寸可不同於凹口之尺寸。例如，穿口尺寸可大於凹口尺寸，且穿口是側向延伸超過凹口之邊緣。
於提供核心層前，選擇性的輔助金屬墊可於形成金屬凸層之同時沉積於金屬載板上，其中輔助金屬墊與金屬凸層之材料可為銅、鋁、鎳或其他金屬或合金。由於輔助金屬墊與金屬凸層可具有相同厚度，因此移除金屬凸層後所形成之凹口深度通常是實質上相等於輔助金屬墊之厚度。此外，金屬柱與輔助金屬墊相互接觸處之金屬柱直徑可相等或相異於輔助金屬墊直徑。
增層電路包括有從凹穴顯露之選定部位以及電性連接至金屬柱之金屬化盲孔。據此，增層電路可提供金屬柱與設置於凹穴內之半導體元件間之電性連接，且金屬柱與增層電路間之電性連接未使用焊接材料。於一較佳實施態樣中，增層電路包括導線，其中導線係直接接觸金屬柱或輔助金屬墊，並由金屬柱或輔助金屬墊延伸且填滿核心層中之盲孔，以形成金屬化盲孔，同時側向延伸於核心層之第一表面上，且該些導線具有從凹穴顯露之選定部位，以提供連接元件用之接觸墊。或者，增層電路更可包括路由線，其中路由線係於提供核心層前沉積於金屬凸層上，並電性連接至導線，且於移除金屬凸層後而使路由線從凹穴顯露。據此，從凹穴顯露之路由線可提供連接元件用之接觸墊。
假如需要更多的信號路由，增層電路可進一步包括一或多層之介電層、額外之盲孔於介電層中、以及額外之導線。介電層與導線可連續輪流形成，且需要的話可重覆形成。增層電路之最外側導線可容置導電接點，例如焊球，以與另一電性裝置電性傳輸及機械性連接。
本發明更提供一半導體組體，其中一第一半導體元件設置於互連基板之凹穴中，並藉由從凹穴顯露之接觸墊電性耦接至互連基板。更具體地說，該第一半導體元件可以覆晶方式，藉由接觸墊上之各種連接媒介(如凸塊)，接置於接觸墊上。在此，第一半導體元件可為已封裝或未封裝晶片。例如，第一半導體元件可為裸晶片或晶圓級封裝晶粒等。或者，第一半導體元件可為堆疊式晶片。此外，可進一步選擇性提供一樹脂密封元件，其覆蓋凹穴之底表面，並由凹穴之底表面延伸，且填充凹穴中未被第一半導體元件佔據之至少一部分空間。另外，更可提供一第二半導體元件，其可藉由金屬柱或增層電路最外側導線上之導電接點而電性耦接至互連基板。據此，本發明可提供一種封裝疊加組體，其包括一第一半導體元件於互連基板之凹穴中以及一第二半導體元件於加強層之外表面及第一半導體元件之非主動面上。又，本發明亦提供一種面朝面組體，其包括一第一半導體元件於互連基板之凹穴中以及一第二半導體元件電性連接至第一導體元件，其中第一半導體元件與第二半導體元件係藉由兩者間之增層電路面朝面地相互電性連接。
「覆蓋」一詞意指於垂直及/或側面方向上不完全以及完全覆蓋。例如，在凹穴向上之狀態下，增層電路可於下方覆蓋第一半導體元件，不論另一元件例如凸塊是否位於增層電路與第一半導體元件之間。同樣地，核心層可於第一方向上覆蓋凹穴。
「金屬載板之對應部位」一詞意指於金屬載板之一選定部位，其係於第二方向上覆蓋金屬凸層。例如，在核心層第一表面向下的狀態下，金屬載板之對應部位可由上方完全覆蓋金屬凸層，不論金屬載板之對應部位是否側向延伸超過金屬凸層之外圍邊緣，或者是否側向延伸至與金屬凸層之外圍邊緣齊平。
「對準」一詞意指元件間之相對位置，不論元件之間是否彼此保持距離或鄰接，或一元件***且延伸進入另一元件中。例如，當假想之垂直線與金屬塊及金屬凸層相交時，金屬塊即對準於金屬凸層，不論金屬塊與金屬凸層之間是否具有其他與假想之水平線相交之元件，且不論是否具有另一與金屬塊相交但不與金屬凸層相交、或與金屬凸層相交但不與金屬塊相交之假想垂直線。同樣地，盲孔係對準於金屬柱或輔助金屬墊。
「電性連接」、以及「電性耦接」之詞意指直接或間接電性連接。例如，第一導線直接接觸並且電性連接至金屬柱或輔助金屬墊，而第二導線則與金屬柱或輔助金屬墊保持距離，並且藉由第一導線，而電性連接至金屬柱或輔助金屬墊。
「第一方向」及「第二方向」並非取決於互連基板或半導體組體之定向，凡熟悉此項技藝之人士即可輕易瞭解其實際所指之方向。例如，核心層之第一表面係面朝第一方向，而核心層之第二表面係面朝第二方向，此與互連基板或半導體組體是否倒置無關。因此，該第一及第二方向係彼此相反且垂直於側面方向。再者，在凹穴向上之狀態，第一方向係為向下方向，第二方向係為向上方向；在凹穴向下之狀態，第一方向係為向上方向，第二方向係為向下方向。
本發明之互連基板具有許多優點。舉例來說，可利用凹口之深度以降低金屬柱之最小高度，藉此得以設置更多的金屬柱。增層電路可提供 具有簡單電路圖案之信號路由，或具有複雜電路圖案之可撓性多層信號路由。由於半導體元件是藉由凸塊接置於互連基板之增層電路上，而不是直接藉由增層製程電性連接，故此簡化的作法有利於低製作成本。藉由此方法製備成的互連基板係為可靠度高、價格低廉、且非常適合大量製造生產。
本發明之製作方法具有高度適用性，且係以獨特、進步之方式結合運用各種成熟之電性及機械性連接技術。此外，本發明之製作方法不需昂貴工具即可實施。因此，相較於傳統技術，此製作方法可大幅提升產量、良率、效能與成本效益。
在此所述之實施例係為例示之用，其中該些實施例可能會簡化或省略本技術領域已熟知之元件或步驟，以免模糊本發明之特點。同樣地，為使圖式清晰，圖式亦可能省略重覆或非必要之元件及元件符號。
100‧‧‧互連基板
113‧‧‧金屬柱
20‧‧‧凹口
21‧‧‧核心層
212‧‧‧第一表面
213‧‧‧盲孔
214‧‧‧第二表面
30‧‧‧增層電路
302、402‧‧‧外表面
31‧‧‧金屬層
31’‧‧‧被覆層
315‧‧‧導線
317‧‧‧金屬化盲孔
319‧‧‧接觸墊
40‧‧‧穿口
41‧‧‧加強層
50‧‧‧凹穴
502‧‧‧底表面
503‧‧‧側壁

Claims (10)

  1. 一種具有凹穴之互連基板，其適用於可堆疊式半導體組體，該互連基板包括：一核心層，其具有一第一表面及一相反第二表面；一增層電路，其設置於該核心層之該第一表面上，並具有背向該核心層之該第一表面之一外表面；一加強層，其設置於該核心層之該第二表面上，並具有背向該核心層之該第二表面的一外表面；一系列金屬柱，其封埋於該加強層中，且由該加強層之該外表面顯露，並藉由該核心層中的金屬化盲孔電性連接至該增層電路；以及一凹穴，其包含該加強層中之一穿口及該核心層中之一凹口，該穿口與該凹口相互對準，且該凹穴之深度大於該些金屬柱之高度，並具有一底表面及側壁，該底表面背向該增層電路之該外表面，而該些側壁由該底表面延伸至該加強層之該外表面，其中該增層電路具有一系列接觸墊，且該些接觸墊係由該底表面顯露。
  2. 如申請專利範圍第1項所述之互連基板，更包括一系列輔助金屬墊，其被該核心層側向覆蓋，且電性耦接至該些金屬柱及該些金屬化盲孔，並位於該些金屬柱與該些金屬化盲孔之間。
  3. 如申請專利範圍第2項所述之互連基板，其中，該些輔助金屬墊之厚度係實質上相等於該凹口之深度。
  4. 如申請專利範圍第1項所述之互連基板，其中，該些金屬柱延伸超過該加強層之該外表面，且具有未被該加強層覆蓋之一選定部位。
  5. 如申請專利範圍第1項所述之互連基板，其中，該加強層之厚度大於該些金屬柱之高度，且該加強層更包括開孔，其由該加強層之該外表面朝該核心層延伸，且每一該些金屬柱具有從該開孔顯露之一選定部位。
  6. 一種垂直堆疊式半導體組體，其包括：如申請專利範圍第1項所述之該互連基板；一第一半導體元件，其設置於該凹穴中，並藉由從該凹穴之該底表面顯露的該些接觸墊，電性耦接至該互連基板；以及一第二半導體元件，其設置於該增層電路之該外表面或該加強層之該外表面上，該第二半導體元件藉由該增層電路或該些金屬柱，電性耦接至該互連基板。
  7. 如申請專利範圍第6項所述之垂直堆疊式半導體組體，更包括一樹脂密封元件，其覆蓋該底表面，並由該底表面延伸且填充該凹穴中未被該第一半導體元件佔據之至少一部分空間。
  8. 一種具有凹穴之互連基板製作方法，該互連基板適用於可堆疊式半導體組體，且該製作方法包括：於一金屬載板之一表面上形成一金屬凸層；形成一核心層，其覆蓋該金屬凸層及該金屬載板之剩餘表面，且該核心層具有背向該金屬載板之一第一表面及鄰近該金屬載板之一相反第二表面；移除該金屬載板之一部分，以形成一系列金屬柱及一金屬塊，其中該金屬塊係對準於該金屬凸層；由該核心層之該第一表面形成一增層電路，該第一增層電路具有背向該核心層之該第一表面的一外表面；形成一加強層，其覆蓋該核心層之該第二表面及該金屬塊與該些金屬柱之側壁，該加強層具有背向該核心層之該第二表面的一外表面；以及移除該金屬塊及該金屬凸層，以形成一凹穴，該凹穴包含一穿口及一凹 口，該穿口位於該加強層中，而該凹口位於該核心層中，同時該凹穴具有一底表面及側壁，該些側壁係由該底表面延伸至該加強層之該外表面；其中，該些增層電路之一系列接觸墊由該凹穴之該底表面顯露，且該些金屬柱由該加強層之該外表面顯露，並藉由該核心層之金屬化盲孔，電性連接至該增層電路。
  9. 如申請專利範圍第8項所述之製作方法，更包括：於形成該核心層前，形成一系列輔助金屬墊於該金屬載板之該表面上，其中該核心層亦覆蓋該些輔助金屬墊，且該些金屬柱形成於該些輔助金屬墊上。
  10. 如申請專利範圍第9項所述之製作方法，其中，該些輔助金屬墊之厚度係實質上相等於該凹口之深度。
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