CN108695238B - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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CN108695238B
CN108695238B CN201710223496.2A CN201710223496A CN108695238B CN 108695238 B CN108695238 B CN 108695238B CN 201710223496 A CN201710223496 A CN 201710223496A CN 108695238 B CN108695238 B CN 108695238B
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layer
forming
conductive
contact hole
barrier seed
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CN108695238A (zh
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张海洋
张城龙
蒋鑫
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to US15/945,883 priority patent/US10373911B2/en
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Abstract

一种半导体器件及其形成方法，其中方法包括：提供基底和位于基底上的介质层，所述基底内具有底层金属层；在所述介质层中形成贯穿介质层的互联层开口，所述互联层开口暴露出底层金属层，所述互联层开口包括接触孔和位于接触孔上的沟槽；在所述接触孔中形成第一导电层，自底层金属层至第一导电层顶部表面的方向上，第一导电层的材料具有第一电导率；形成第一导电层后，在所述沟槽中形成第二导电层，在平行于基底顶部表面的方向上，第二导电层的材料具有第二电导率，第一电导率大于第二电导率。所述方法使半导体器件的电学性能提高。

Description

半导体器件及其形成方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体器件及其形成方法。
背景技术
随着半导体集成电路工艺技术的不断进步，当半导体器件缩小至深亚微米的范围时，半导体器件之间的高性能、高密度连接需要通过互联结构实现。互联结构中易形成寄生电阻和寄生电容，从而出现寄生效应，导致金属连线传递的时间延迟，人们面临着如何克服由于连接长度的急速增长而带来的RC(R指电阻，C指电容)延迟显著增加的问题。
为了克服互联中的寄生效应，在大规模集成电路后段工艺互联的集成工艺中，一方面，寄生电容正比于互联层绝缘介质的相对介电常数K，因此使用低K材料尤其是超低介电常数(Ultra-low dielectric constant，ULK)的材料代替传统的SiO2介质材料已成为满足高速芯片的发展的需要，另一方面，由于铜具有较低的电阻率、优越的抗电迁移特性和高的可靠性，能够降低金属的互连电阻，进而减小总的互连延迟效应，现已由常规的铝互连改变为低电阻的铜互连。
然而，现有技术形成的半导体器件的性能较差。
发明内容
本发明解决的问题是提供一种半导体器件及其形成方法，以提高半导体器件的电学性能。
为解决上述问题，本发明提供一种半导体器件的形成方法，包括：提供基底和位于基底上的介质层，所述基底内具有底层金属层；在所述介质层中形成贯穿介质层的互联层开口，所述互联层开口暴露出底层金属层，所述互联层开口包括接触孔和位于接触孔上的沟槽；在所述接触孔中形成第一导电层，自底层金属层至第一导电层顶部表面的方向上，第一导电层的材料具有第一电导率；形成第一导电层后，在所述沟槽中形成第二导电层，在平行于基底顶部表面的方向上，第二导电层的材料具有第二电导率，第一电导率大于第二电导率。
可选的，所述第一导电层的材料为碳纳米管，所述碳纳米管的延伸方向平行于自底层金属层至第一导电层顶部表面的方向。
可选的，形成所述第一导电层的方法包括：在所述沟槽和所述接触孔中、以及介质层上形成第一导电材料层；去除介质层上的第一导电材料层；去除介质层上的第一导电材料层后，去除所述沟槽中的第一导电材料层，形成所述第一导电层。
可选的，形成所述第一导电材料层的工艺为催化化学气相沉积法；所述半导体器件的形成方法还包括：在形成所述第一导电材料层之前，在所述沟槽和所述接触孔的内壁、以及介质层上形成催化剂层；形成所述第一导电材料层后，第一导电材料层位于催化剂层表面；在去除介质层上的第一导电材料层的过程中，去除介质层上的催化剂层。
可选的，所述催化剂层的材料为钴纳米粒子、铁纳米粒子或镍纳米粒子。
可选的，还包括：在形成所述催化剂层之前，在所述沟槽和所述接触孔的内壁、以及介质层上形成催化基质层；形成所述催化剂层后，催化剂层位于催化基质层表面；在去除介质层上的第一导电材料层的过程中，去除介质层上的催化剂层和催化基质层。
可选的，所述催化基质层的材料包括铜。
可选的，形成所述催化基质层的方法包括：在所述沟槽和所述接触孔的内壁、以及介质层上形成初始催化基质层；对所述初始催化基质层进行退火处理，使初始催化基质层形成催化基质层。
可选的，当所述催化基质层的材料为铜时，所述初始催化基质层的材料为Cu3N。
可选的，形成所述初始催化基质层的工艺包括原子层沉积工艺。
可选的，还包括：在形成所述催化基质层之前，在所述沟槽和所述接触孔的内壁、以及介质层上形成阻挡种子结构；形成所述催化基质层后，催化基质层位于阻挡种子结构表面；在去除介质层上的第一导电材料层的过程中，去除介质层上的催化剂层、催化基质层和阻挡种子结构。
可选的，所述阻挡种子结构包括位于所述沟槽和接触孔的内壁的第一阻挡种子层、以及位于第一阻挡种子层表面的第二阻挡种子层，第二阻挡种子层位于第一阻挡种子层和催化基质层之间。
可选的，所述第一阻挡种子层的材料为钽；所述第二阻挡种子层的材料为氮化钽；或者，所述第一阻挡种子层的材料为钛，所述第二阻挡种子层的材料为氮化钛。
可选的，去除所述介质层上的第一导电材料层的工艺为平坦化工艺；去除所述沟槽中的第一导电材料层的工艺为刻蚀工艺。
可选的，所述刻蚀工艺为干法刻蚀工艺；所述干法刻蚀工艺采用的气体包括O2、CO2、CO和SO2中的一种或几种的组合。
可选的，所述第二导电层的材料包括金属。
本发明还提供一种半导体器件，包括：基底，所述基底内具有底层金属层；位于所述基底上的介质层；贯穿所述介质层的互联层开口，所述互联层开口暴露出底层金属层，所述互联层开口包括接触孔和位于接触孔上的沟槽；位于所述接触孔中的第一导电层，自底层金属层至第一导电层顶部表面的方向上，第一导电层的材料具有第一电导率；位于所述沟槽中的第二导电层，在平行于基底顶部表面的方向上，第二导电层的材料具有第二电导率，第一电导率大于第二电导率。
可选的，所述第一导电层的材料为碳纳米管，所述碳纳米管的延伸方向平行于自底层金属层至第一导电层顶部表面的方向；所述第二导电层的材料包括金属。
可选的，还包括：阻挡种子结构，所述阻挡种子结构位于所述第一导电层和所述介质层之间、以及所述第二导电层和所述介质层之间。
可选的，所述阻挡种子结构包括位于所述沟槽和接触孔的内壁的第一阻挡种子层、以及位于第一阻挡种子层表面的第二阻挡种子层，第二阻挡种子层位于第一阻挡种子层和第一导电层之间、以及第一阻挡种子层和第二导电层之间。
与现有技术相比，本发明的技术方案具有以下优点：
本发明技术方案提供的半导体器件的形成方法中，在接触孔中形成第一导电层，所述第一导电层用于连接底层金属层和第二导电层，且第一导电层用于在平行于自底层金属层至第一导电层顶部表面的方向上进行电流传导。在沟槽中形成第二导电层，第二导电层用于在平行于基底表面的方向上进行电流传导。自底层金属层至第一导电层顶部表面的方向上，第一导电层的材料具有第一电导率，在平行于基底顶部表面的方向上，第二导电层的材料具有第二电导率。由于第一电导率大于第二电导率，第一电导率较大，因此使得在第一导电层传导电流的过程中，第一导电层中的电流密度降低。进而改善了第一导电层中的电流拥挤效应。
进一步，所述第一导电层的材料为碳纳米管，所述碳纳米管的延伸方向平行于自底层金属层至第一导电层顶部表面的方向。由于碳纳米管沿着其延伸方向的电导率较高，因此使第一电导率进一步增加。进一步改善了第一导电层中电流拥挤效应。
本发明技术方案提供的半导体器件中，自底层金属层至第一导电层顶部表面的方向上，第一导电层的材料具有第一电导率，在平行于基底顶部表面的方向上，第二导电层的材料具有第二电导率。由于第一电导率大于第二电导率，第一电导率较大，因此使得在第一导电层传导电流的过程中，第一导电层中的中电流密度降低。进而改善了第一导电层中电流拥挤效应。
附图说明
图1是一种半导体器件的结构示意图；
图2至图12是本发明一实施例中半导体器件形成过程的结构示意图。
具体实施方式
正如背景技术所述，现有技术形成的半导体器件的性能较差。
图1是一种半导体器件的结构示意图，半导体器件包括：基底100，所述基底100内具有底层金属层110；位于所述基底100上的介质层120；贯穿所述介质层120的互联层开口，所述互联层开口暴露出底层金属层110，所述互联层开口包括接触孔和位于接触孔上的沟槽；位于所述互联层开口中的导电层130。
然而，上述半导体器件的电学性能较差，经研究发现，原因在于：
所述接触孔中的导电层130用于电学连接底层金属层110和沟槽中的导电层。所述接触孔中的导电层130在平行于底层金属层110至导电层130顶部表面的方向上进行电流传导。所述接触孔中导电层130中的电流流过的横截面积小于沟槽中导电层130中的电流流过的横截面积。
在此基础上，随着半导体器件特征尺寸的减小，接触孔中导电层130在传导电流的过程中，接触孔中导电层130的电流密度过大，导致接触孔中导电层130的电流拥挤效应较为严重。
为了解决上述问题，本发明提供一种半导体器件的形成方法，包括：提供基底和位于基底上的介质层，所述基底内具有底层金属层；在所述介质层中形成贯穿介质层的互联层开口，所述互联层开口暴露出底层金属层，所述互联层开口包括接触孔和位于接触孔上的沟槽；在所述接触孔中形成第一导电层，自底层金属层至第一导电层顶部表面的方向上，第一导电层的材料具有第一电导率；形成第一导电层后，在所述沟槽中形成第二导电层，在平行于基底顶部表面的方向上，第二导电层的材料具有第二电导率，第一电导率大于第二电导率。
所述方法中，在接触孔中形成第一导电层，所述第一导电层用于连接底层金属层和第二导电层，且第一导电层用于在平行于自底层金属层至第一导电层顶部表面的方向上进行电流传导。在沟槽中形成第二导电层，第二导电层用于在平行于基底表面的方向上进行电流传导。自底层金属层至第一导电层顶部表面的方向上，第一导电层的材料具有第一电导率，在平行于基底顶部表面的方向上，第二导电层的材料具有第二电导率。由于第一电导率大于第二电导率，第一电导率较大，因此使得在第一导电层传导电流的过程中，第一导电层中的电流密度降低。进而改善了第一导电层中的电流拥挤效应。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图2至图12是本发明一实施例中半导体器件形成过程的结构示意图。
参考图2，提供基底200和位于基底200上的介质层230，所述基底200内具有底层金属层210。
所述基底200包括半导体衬底和位于半导体衬底上的金属介质层(未图示)，所述底层金属层210位于金属介质层中。
所述半导体衬底中还可以具有半导体结构，所述半导体结构为PMOS晶体管、NMOS晶体管、CMOS晶体管、电容器、电阻器或电感器。
所述底层金属层210用于和所述半导体衬底中的半导体结构及待形成的第一导电层相连。
所述底层金属层210的材料为铜或铜铝合金等导电材料。
所述介质层230的材料为低K介质材料(低K介质材料指相对介电常数大于等于2.6、小于3.9的介质材料)或超低K介质材料(超低K介质材料指相对介电常数小于2.6的介质材料)。所述介质层230的材料为低K介质材料或超低K介质材料时，介质层230的材料为SiOH、SiCOH、FSG(掺氟的二氧化硅)、BSG(掺硼的二氧化硅)、PSG(掺磷的二氧化硅)、BPSG(掺硼磷的二氧化硅)、氢化硅倍半氧烷(HSQ，(HSiO1.5)n)或甲基硅倍半氧烷(MSQ，(CH3SiO1.5)n)。本实施例中，所述介质层230的材料为超低K介质材料，所述超低K介质材料为SiCOH。
接着，在所述介质层230中形成贯穿介质层230的互联层开口，所述互联层开口暴露出底层金属层210，所述互联层开口包括接触孔和位于接触孔上的沟槽。
下面参考图3至图8介绍形成互联层开口的方法。
参考图3，在所述介质层230上形成掩膜层240，所述掩膜层240中具有沟槽图形开口241。
图4为掩膜层240的立体示意图，所述掩膜层240为单层结构或叠层结构，掩膜层240的材料为氮化钛或氮化钽。所述掩膜层240中具有一个或多个分立排列的沟槽图形开口241，所述沟槽图形开口241定义出后续形成的沟槽的位置和形状。本实施例中，以所述沟槽图形开口241的数量为两个作为示例，在实际工艺中，可以根据具体情况设计沟槽图形开口241的数量。
参考图5，图5为图3基础上的示意图，形成覆盖所述掩膜层240和所述沟槽图形开口241(参考图3)的平坦层250。
所述平坦层250的材料为有机涂层材料、抗反射涂层材料或无定型碳。形成所述平坦层250的工艺为旋涂工艺或化学气相沉积工艺。
继续参考图5，在所述平坦层250上形成具有接触孔图形开口261的光刻胶层260，接触孔图形开口261位于沟槽图形开口241(参考图3)上。
所述光刻胶层260的材料为光刻胶。
图6为光刻胶层260的立体示意图，所述光刻胶层260中具有接触孔图形开口261，所述接触孔图形开口261定义出后续形成的接触孔的位置和形状。
在一个实施例中，接触孔图形开口261的孔径比沟槽图形开口241的宽度大，使得后续形成的接触孔的宽度可以由沟槽图形开口241的宽度决定，使得后续形成的接触孔的长度可以由接触孔图形开口261的孔径决定。所述接触孔的宽度指的是平行于沟槽图形开口241宽度方向上的尺寸，所述接触孔的长度为平行于基底200顶部表面且垂直于沟槽图形开口241宽度方向上的尺寸。即后续形成的接触孔的宽度最大限度的利用了沟槽图形开口241的宽度尺寸，有利于后续在接触孔中填充导电层。
在其它实施例中，接触孔图形开口的孔径小于或者等于沟槽图形开口的宽度。
参考图7，图7为在图5基础上的示意图，以所述光刻胶层260和掩膜层240为掩膜刻蚀部分厚度的介质层230，在所述介质层230中形成初始接触孔。
本实施例中，在刻蚀部分厚度的介质层230之前，还包括步骤：沿接触孔图形开口261刻蚀平坦层250，使介质层230顶部表面被暴露出来。
具体的，以所述光刻胶层260和掩膜层240为掩膜，采用各向异性干法刻蚀工艺刻蚀部分厚度的介质层230以形成初始接触孔，如各向异性等离子体刻蚀工艺或反应离子刻蚀工艺。
在后续以掩膜层240为掩膜刻蚀介质层230的过程中，会继续沿初始接触孔刻蚀初始接触孔底部的介质层230。
接着，参考图8，去除所述光刻胶层260(参考图7)和平坦层250(参考图7)；去除所述光刻胶层260和平坦层250后，以所述掩膜层240为掩膜刻蚀介质层230直至暴露出底层金属层210表面，形成互联层开口270。
所述互联层开口270包括接触孔271和位于接触孔271上的沟槽272。
所述接触孔271的延伸方向平行于自底层金属层210至介质层230的方向。所述沟槽272的延伸方向平行于基底200的顶部表面。
接着，在所述接触孔271中形成第一导电层，自底层金属层210至第一导电层顶部表面的方向上，第一导电层的材料具有第一电导率。
形成所述第一导电层的方法包括：在所述沟槽272和所述接触孔271中、以及介质层230上形成第一导电材料层；去除介质层230上的第一导电材料层；去除介质层230上的第一导电材料层后，去除所述沟槽272中的第一导电材料层，形成第一导电层。
参考图9，在所述沟槽272和所述接触孔271中、以及介质层230上形成第一导电材料层290。
本实施例中，所述第一导电材料层290的材料为碳纳米管，所述碳纳米管的延伸方向平行于自底层金属层210至第一导电材料层290顶部表面的方向。
通过激光烧蚀法、催化化学气相沉积法(CCVD)或电弧法形成第一导电材料层290。
本实施例中，形成第一导电材料层290的工艺以催化化学气相沉积法为示例进行说明。
本实施例中，还包括：在形成所述第一导电材料层290之前，在所述沟槽272和所述接触孔271的内壁、以及介质层230上形成催化剂层(未图示)；形成所述第一导电材料层284后，第一导电材料层284位于催化剂层表面。
所述催化化学气相沉积法的过程包括：采用过渡金属(如Fe、Co或Ni等)作为催化剂层的材料，在700摄氏度～1200摄氏度的条件下，使得碳源气体离解成自由碳原子沉积在催化剂层上，从而形成碳纳米管材料的第一导电材料层290。
本实施例中，所述催化剂层的材料为钴纳米粒子、铁纳米粒子或镍纳米粒子，好处在于：催化性能好，催化效率高。
形成所述催化剂层的工艺为分子束外延生长工艺或溅射沉积工艺。
本实施例中，还包括：在形成所述催化剂层之前，在所述沟槽272和所述接触孔271的内壁、以及介质层230上形成催化基质层282；形成所述催化剂层后，催化剂层位于催化基质层282表面。
所述催化基质层282的材料包括铜。
所述催化基质层282的作用包括：优化催化基质层282的生长，使催化基质层282分布更加均匀。
本实施例中，形成所述催化基质层282的方法包括：在所述沟槽272和所述接触孔271的内壁、以及介质层230上形成初始催化基质层(未图示)；对所述初始催化基质层进行退火处理，使初始催化基质层形成催化基质层282。
当所述催化基质层282的材料为铜时，所述初始催化基质层的材料为Cu3N。
形成所述初始催化基质层的工艺包括原子层沉积工艺。
在其它实施例中，形成所述催化基质层282的工艺为沉积工艺，如溅射工艺。
本实施例中，还包括：在形成所述催化基质层282之前，在所述沟槽272和所述接触孔271的内壁、以及介质层230上形成阻挡种子结构281；形成所述催化基质层282后，催化基质层282位于阻挡种子结构281表面。
所述阻挡种子结构281的作用包括：阻挡催化基质层282和后续第二导电层扩散；作为催化基质层282生长的种子层。
所述阻挡种子结构281包括位于所述沟槽272和接触孔271内壁的第一阻挡种子层、以及位于第一阻挡种子层表面的第二阻挡种子层，第二阻挡种子层位于第一阻挡种子层和催化基质层282之间。
所述第一阻挡种子层的材料为钽；所述第二阻挡种子层的材料为氮化钽；或者，所述第一阻挡种子层的材料为钛，所述第二阻挡种子层的材料为氮化钛。
在其它实施例中，不形成阻挡种子结构。
本实施例中，在形成第一导电材料层290、催化剂层、催化基质层282和阻挡种子结构281之前，保留掩膜层240，用于在后续的平坦化工艺或刻蚀工艺中保护介质层230的顶部表面。相应的，第一导电材料层290、催化剂层、催化基质层282和阻挡种子结构281还位于掩膜层240上。
在其它实施例中，在形成第一导电材料层、催化剂层、催化基质层和阻挡种子结构之前，去除掩膜层。
参考图10，去除介质层230上的第一导电材料层290。
去除介质层230上的第一导电材料层290的工艺为平坦化工艺。
本实施例中，在去除介质层230上的第一导电材料层290的过程中，去除介质层230上的催化剂层、催化基质层282和阻挡种子结构281。
本实施例中，采用平坦化工艺平坦化第一导电材料层290、催化剂层、催化基质层282和阻挡种子结构281直至暴露出掩膜层240的顶部表面。
参考图11，去除介质层230上的第一导电材料层290后，去除所述沟槽272中的第一导电材料层290，在接触孔271中形成第一导电层291。
去除所述沟槽272中的第一导电材料层290的工艺为刻蚀工艺。
在一个实施例中，所述刻蚀工艺为干法刻蚀工艺，所述干法刻蚀工艺采用的气体包括O2、CO2、CO和SO2中的一种或几种的组合。
本实施例中，所述第一导电层291的材料为碳纳米管，所述碳纳米管的延伸方向平行于自底层金属层210至第一导电层291顶部表面的方向。
所述第一导电层291用于在平行于自底层金属层110至第一导电层291顶部表面的方向上进行电流传导。
自底层金属层210至第一导电层291顶部表面的方向上，第一导电层291的材料具有第一电导率。
参考图12，形成第一导电层291后，在所述沟槽272中形成第二导电层300，在平行于基底200顶部表面的方向上，第二导电层300的材料具有第二电导率，第一电导率大于第二电导率。
所述第二导电层300的材料包括金属，如铜。
第二导电层300用于在平行于基底200表面的方向上进行电流传导。
形成所述第二导电层300的方法包括：在所述沟槽272中和介质层230上形成第二导电材料层(未图示)；去除介质层230上的第二导电材料层，形成所述第二导电层300。
本实施例中，去除介质层230上的第二导电材料层的工艺为平坦化工艺，如化学机械研磨工艺。在去除介质层230上的第二导电材料层的过程中，去除掩膜层240(参考图11)。
本实施例中，第一导电层291中电流流过的横截面积小于第二导电层300中电流流过的横截面积。
本实施例中，由于第一电导率大于第二电导率，第一电导率较大，因此使得在第一导电层291传导电流的过程中，第一导电层291中的电流密度降低，进而改善了第一导电层291中电流拥挤效应。
相应的，本发明还提供一种采用上述方法形成的半导体器件，请参考图12，包括：基底200，所述基底200内具有底层金属层210；位于所述基底200上的介质层230；贯穿所述介质层230的互联层开口270(参考图8)，所述互联层开口270暴露出底层金属层210，所述互联层开口270包括接触孔271和位于接触孔271上的沟槽272；位于所述接触孔271中的第一导电层291，自底层金属层210至第一导电层291顶部表面的方向上，第一导电层291的材料具有第一电导率；位于所述沟槽272中的第二导电层300，在平行于基底200顶部表面的方向上，第二导电层300的材料具有第二电导率，第一电导率大于第二电导率。
所述第一导电层291的材料为碳纳米管，所述碳纳米管的延伸方向平行于自底层金属层210至第一导电层291顶部表面的方向；所述第二导电层300的材料包括金属。
所述半导体器件还包括：阻挡种子结构281，所述阻挡种子结构281位于所述第一导电层291和所述介质层230之间、以及所述第二导电层300和所述介质层230之间。
所述阻挡种子结构281包括位于所述沟槽272和接触孔271的内壁的第一阻挡种子层、以及位于第一阻挡种子层表面的第二阻挡种子层，第二阻挡种子层位于第一阻挡种子层和第一导电层291之间、以及第一阻挡种子层和第二导电层300之间。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (15)

1.一种半导体器件的形成方法，其特征在于，包括：
提供基底和位于基底上的介质层，所述基底内具有底层金属层；
在所述介质层中形成贯穿介质层的互联层开口，所述互联层开口暴露出底层金属层，所述互联层开口包括接触孔和位于接触孔上的沟槽；
在所述沟槽和所述接触孔的内壁、以及介质层上形成阻挡种子结构；所述阻挡种子结构作为催化基质层生长的种子层；
在所述沟槽和所述接触孔的内壁、以及介质层上形成的所述阻挡种子结构表面，形成催化基质层；所述催化基质层的材料包括铜；
在所述催化基质层表面形成催化剂层；
在所述催化剂层表面形成第一导电材料层，并仅去除介质层上的催化剂层、催化基质层和阻挡种子结构，以及去除沟槽中的第一导电材料层，保留沟槽中的阻挡种子结构及催化基质层，形成第一导电层，自底层金属层至第一导电层顶部表面的方向上，第一导电层的材料具有第一电导率；
形成第一导电层后，在所述沟槽中形成第二导电层，在平行于基底顶部表面的方向上，第二导电层的材料具有第二电导率，第一电导率大于第二电导率。
2.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述第一导电层的材料为碳纳米管，所述碳纳米管的延伸方向平行于自底层金属层至第一导电层顶部表面的方向。
3.根据权利要求1所述的半导体器件的形成方法，其特征在于，形成所述第一导电材料层的工艺为催化化学气相沉积法。
4.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述催化剂层的材料为钴纳米粒子、铁纳米粒子或镍纳米粒子。
5.根据权利要求1所述的半导体器件的形成方法，其特征在于，形成所述催化基质层的方法包括：在所述沟槽和所述接触孔的内壁、以及介质层上形成初始催化基质层；对所述初始催化基质层进行退火处理，使初始催化基质层形成催化基质层。
6.根据权利要求5所述的半导体器件的形成方法，其特征在于，所述初始催化基质层的材料为Cu3N。
7.根据权利要求5所述的半导体器件的形成方法，其特征在于，形成所述初始催化基质层的工艺包括原子层沉积工艺。
8.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述阻挡种子结构包括位于所述沟槽和接触孔的内壁的第一阻挡种子层、以及位于第一阻挡种子层表面的第二阻挡种子层，第二阻挡种子层位于第一阻挡种子层和催化基质层之间。
9.根据权利要求8所述的半导体器件的形成方法，其特征在于，所述第一阻挡种子层的材料为钽；所述第二阻挡种子层的材料为氮化钽；或者，所述第一阻挡种子层的材料为钛，所述第二阻挡种子层的材料为氮化钛。
10.根据权利要求2所述的半导体器件的形成方法，其特征在于，去除所述介质层上的第一导电材料层的工艺为平坦化工艺；去除所述沟槽中的第一导电材料层的工艺为刻蚀工艺。
11.根据权利要求10所述的半导体器件的形成方法，其特征在于，所述刻蚀工艺为干法刻蚀工艺；所述干法刻蚀工艺采用的气体包括O2、CO2、CO和SO2中的一种或几种的组合。
12.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述第二导电层的材料包括金属。
13.一种半导体器件，其特征在于，包括：
基底，所述基底内具有底层金属层；
位于所述基底上的介质层；
贯穿所述介质层的互联层开口，所述互联层开口暴露出底层金属层，所述互联层开口包括接触孔和位于接触孔上的沟槽；
位于所述沟槽和所述接触孔的内壁上的阻挡种子结构，所述阻挡种子结构作为催化基质层生长的种子层；
位于所述沟槽和所述接触孔的内壁的所述阻挡种子结构表面的催化基质层，所述催化基质层的材料包括铜；
在所述催化基质层表面形成催化剂层；
位于所述接触孔中的第一导电层，自底层金属层至第一导电层顶部表面的方向上，第一导电层的材料具有第一电导率；
位于所述沟槽中的第二导电层，在平行于基底顶部表面的方向上，第二导电层的材料具有第二电导率，第一电导率大于第二电导率。
14.根据权利要求13所述的半导体器件，其特征在于，所述第一导电层的材料为碳纳米管，所述碳纳米管的延伸方向平行于自底层金属层至第一导电层顶部表面的方向；所述第二导电层的材料包括金属。
15.根据权利要求13所述的半导体器件，其特征在于，所述阻挡种子结构包括位于所述沟槽和接触孔的内壁的第一阻挡种子层、以及位于第一阻挡种子层表面的第二阻挡种子层，第二阻挡种子层位于第一阻挡种子层和第一导电层之间、以及第一阻挡种子层和第二导电层之间。
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