CN217405435U

CN217405435U - Shielded gate depletion mode power MOSFET

Info

Publication number: CN217405435U
Application number: CN202220429579.3U
Authority: CN
Inventors: 周仲建; 王新; 张帅
Original assignee: Chengdu Fujin Power Semiconductor Technology Development Co ltd
Current assignee: Chengdu Fujin Power Semiconductor Technology Development Co ltd
Priority date: 2022-03-02
Filing date: 2022-03-02
Publication date: 2022-09-09
Anticipated expiration: 2032-03-02

Abstract

The utility model discloses a shielded gate depletion type power MOSFET belongs to semiconductor technology field. The cell area is used as a function area and is positioned at the upper part of the semiconductor epitaxial layer; the cell region comprises a shielding grid and a control grid which are arranged in a groove structure, a dielectric isolation layer is arranged between the shielding grid and the control grid, grid oxide layers are arranged on two sides of the control grid, and a first conductive type conductive channel is arranged on the outer side of the grid oxide layer. The utility model adopts the groove shielding grid structure to manufacture the depletion type MOSFET, utilizes the charge balance effect of the shielding grid to improve the breakdown voltage of the device, and simultaneously, the channel in the vertical direction increases the channel quantity in unit area, and reduces the on-resistance of the device; meanwhile, the shielding grid structure also greatly reduces the grid-drain capacitance CGD of the device and improves the switching speed of the device.

Description

Shielded gate depletion mode power MOSFET

Technical Field

The invention relates to a depletion mode power MOSFET, in particular to a shielded gate depletion mode power MOSFET.

Background

Power MOSFETs are generally classified into enhancement type and depletion type according to the gate driving method. Since the depletion type MOSFET is a normally-on device, the device is in a conducting state between the drain and the source when no voltage is applied to the gate, and the device conduction channel gradually narrows until completely turned off when a voltage lower than the source is applied to the gate. Due to the unique performance of the depletion type MOSFET, the depletion type MOSFET has incomparable advantages in the practical application of circuits, and the depletion type MOSFET is widely applied to solid-state relays, "normally open" switches, linear operational amplifiers, constant current sources, constant voltage sources, switching power supplies and the like at present.

The conventional depletion type MOSFET is mainly manufactured by a planar process (for example, patent application No. CN 201410060184.0), and the main method is to pre-form a channel on the silicon surface by implanting arsenic ions, which has the advantage of uniform distribution of arsenic ions on the silicon surface. Because the conducting channels are distributed on the silicon surface, when a medium-low voltage device is manufactured, the density of the conducting channels cannot be further improved due to the limitation of a cellular structure, and the on-resistance and the current passing capacity of the device are obviously influenced. In addition, the depletion type MOSFET is manufactured by adopting a planar process, a well region is usually manufactured first, and then a polysilicon gate is manufactured.

In order to increase the channel density of medium-low voltage depletion type MOSFETs, thereby reducing the on-resistance and improving the current passing capability thereof, manufacturers have adopted a trench structure to fabricate a depletion type MOSFET (for example, patent application nos. CN 201410404340.0 and CN 201821564557.8). When channel ion doping is carried out, a large number of ions with the same doping type as that of the drift region are necessarily gathered at the bottom of the groove, so that when the device is in an off state, the high-concentration doping of the part can greatly reduce the breakdown voltage of the whole device.

In order to solve the problem of the influence of the trench bottom weak point of the trench depletion type MOSFET on the device breakdown voltage, manufacturers add a region opposite to the channel conductivity type at the trench bottom, and use the charge balance principle to improve the device breakdown voltage (for example, patent application No. CN 201811195273.0). Because the added special area adopts a doping mode, the cell size cannot be further reduced due to the problems of doping photoetching precision and doping transverse diffusion.

Disclosure of Invention

The utility model discloses aim at solving the above-mentioned problem that exists among the prior art, provide a shielding grid depletion type power MOSFET, can improve the problem of compromising of depletion type MOSFET between breakdown voltage and on resistance by a wide margin, reduce device bars simultaneously and leak electric capacity, improve device switching speed.

In order to realize the purpose of the utility model, the technical scheme of the utility model is as follows:

the shielded gate depletion type power MOSFET comprises a drain electrode metal layer, a semiconductor substrate layer of a first conductivity type, a semiconductor epitaxial layer of the first conductivity type, a dielectric layer and a source electrode metal layer, and is characterized in that a cellular region is positioned at the upper part of the semiconductor epitaxial layer as a functional region; the cell region comprises a shielding grid and a control grid which are arranged in a groove structure, a dielectric isolation layer is arranged between the shielding grid and the control grid, grid oxide layers are arranged on two sides of the control grid, and a first conductive type conductive channel is arranged on the outer side of the grid oxide layer.

In one embodiment, the shielding grid has the same potential as the source metal layer.

In one embodiment, the shielding gate has the same potential as the control gate.

In one embodiment, the shielding grid is a floating electrode.

In one embodiment, the thickness of the dielectric isolation layer is greater than or equal to 0, and when the thickness of the dielectric isolation layer is 0, the shielding gate and the control gate are connected together and have the same potential.

In one embodiment, the cell region further includes a semiconductor body region of the second conductivity type and a heavily doped source region of a semiconductor of the first conductivity type.

In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

In one embodiment, the first conductivity type is P-type and the second conductivity type is N-type.

In one embodiment, the trench structure is formed by etching on a semiconductor epitaxial layer.

In one embodiment, the material of the semiconductor includes, but is not limited to, silicon.

To sum up, the utility model has the advantages of it is following:

1. the utility model adopts a groove shielding grid structure to manufacture a depletion type MOSFET, and utilizes the charge balance effect of the shielding grid, so that the breakdown voltage of the device can be improved under the condition of not changing the doping concentration of the epitaxial layer, or the doping concentration of the epitaxial layer is increased under the condition of keeping the breakdown voltage unchanged, thereby reducing the on-resistance of the device;

2. the utility model increases the channel width of unit area through the conductive channel arranged in the vertical direction, reduces the on-resistance of the device, and increases the current passing capacity;

3. the utility model discloses a slot shielding bars structure reduced device bars electric capacity CGD that leaks by a wide margin, improved device switching speed, avoided forming the breakdown voltage that high concentration region influences the device bottom the slot simultaneously.

Drawings

Fig. 1 is a schematic structural diagram of a shielded gate depletion mode power MOSFET of the present invention;

in the figure:

1. the structure comprises a drain electrode metal layer, 2, a semiconductor substrate layer, 3, a semiconductor epitaxial layer, 4, a dielectric layer, 5, a source electrode metal layer, 6, a thick oxide layer, 7, a shielding gate, 8, a control gate, 9, a dielectric isolation layer, 10, a gate oxide layer, 11, a conducting channel, 12, a semiconductor body region, 13 and a semiconductor heavily doped source region.

Detailed Description

In order to explain the present invention more clearly, the present invention will be further described with reference to the preferred embodiments and the accompanying drawings. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention. The terms "first," "second," and the like in the description and claims of the present invention and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

Example 1

The utility model provides a shielded gate depletion type power MOSFET adopts slot shielded gate structure preparation depletion type MOSFET, utilizes the charge balance effect of shielded gate, can improve device breakdown voltage in the condition that does not change epitaxial layer doping concentration, perhaps increases epitaxial layer doping concentration under the unchangeable condition of breakdown voltage and reduces device on-resistance with this. As shown in fig. 1, the shielded gate depletion mode power MOSFET sequentially comprises, from bottom to top: the semiconductor device comprises a drain metal layer 1, a first conductive type semiconductor substrate layer 2, a first conductive type semiconductor epitaxial layer 3, a dielectric layer 4 and a source metal layer 5. The cell region is located on the upper portion of the semiconductor epitaxial layer 3 as a functional region of the depletion type power MOSFET.

Specifically, the cell region includes: a thick oxide layer 6, a polysilicon shielding gate 7, a polysilicon control gate 8 and a dielectric isolation layer 9 between the shielding gate 7 and the control gate 8, which are contained in the trench structure, are formed on the semiconductor epitaxial layer 3 through etching; a gate oxide layer 10 positioned on both sides of the control gate 8; a conductive channel 11 of the first conductivity type, a semiconductor body 12 of the second conductivity type and a heavily doped source region 13 of the semiconductor of the first conductivity type located outside the gate oxide layer 10.

The thick oxide layer 6 is used to support the voltage in the formed high electric field region, and is typically formed by oxidation or deposition. Preferably, the polysilicon shield gate 7 is located below the polysilicon control gate 8.

Preferably, the conductive channel 11 is vertically oriented and is located between the gate oxide 10 and the semiconductor body 12. The conducting channel arranged in the vertical direction increases the channel width of a unit area, reduces the on-resistance of the device and increases the current passing capacity.

Preferably, the first conductivity type semiconductor is N-type, the second conductivity type semiconductor is P-type, and the depletion MOSFET thus fabricated is an N-channel device.

The compromise between the breakdown voltage and the on-resistance of the shielding grid 7 depletion type MOSFET in the embodiment is greatly improved, and meanwhile, the switching speed of the device can be greatly improved due to the lower grid-drain capacitance CGD.

Example 2

As another embodiment of the present invention, the difference from embodiment 1 is that the first conductivity type is P-type, the second conductivity type is N-type, and the depletion MOSFET manufactured at this time is a P-channel device.

Example 3

As another embodiment of the present invention, it is preferable that the shield gate 7 is electrically connected to the source metal region 5, thereby realizing the same potential.

Example 4

Unlike embodiment 3, it is preferable that the shield gate 7 and the control gate 8 are electrically connected to each other, thereby achieving the same potential.

Example 5

Unlike embodiment 3 and embodiment 4, it is preferable that the shield grid 7 is a floating electrode and is not connected to any other electrode.

Example 6

As another embodiment of the present invention, it is preferable that the thickness of the dielectric isolation layer 9 between the shielding gate 7 and the control gate 8 is 0, and the shielding gate 7 and the control gate 8 are connected to form a whole, thereby realizing the same potential.

Semiconductor materials mentioned in the present disclosure include, but are not limited to, silicon.

While the present invention has been described in detail and with reference to the accompanying drawings, it is not to be considered as limited to the scope of the invention. Various modifications and changes may be made by those skilled in the art without inventive step within the scope of the appended claims.

The above is only the preferred embodiment of the present invention, not to the limitation of the present invention in any form, all the technical matters of the present invention all fall into the protection scope of the present invention to any simple modification and equivalent change of the above embodiments.

Claims

1. The shielded gate depletion type power MOSFET comprises a drain electrode metal layer (1), a semiconductor substrate layer (2) of a first conductivity type, a semiconductor epitaxial layer (3) of the first conductivity type, a dielectric layer (4) and a source electrode metal layer (5), and is characterized in that a cellular region serving as a functional region is positioned at the upper part of the semiconductor epitaxial layer (3); the cell region comprises a shielding grid (7) and a control grid (8) which are arranged in a groove structure, a medium isolation layer (9) is arranged between the shielding grid (7) and the control grid (8), grid oxide layers (10) are arranged on two sides of the control grid (8), and a first conductive type conductive channel (11) is arranged on the outer side of each grid oxide layer (10).

2. Shielded gate depletion mode power MOSFET according to claim 1, characterized in that the potential of the shield gate (7) is the same as the potential of the source metal layer (5).

3. Shielded gate depletion mode power MOSFET according to claim 1, characterized in that the shield gate (7) has the same potential as the control gate (8).

4. The shielded gate depletion mode power MOSFET of claim 1 wherein the shielded gate (7) is a floating electrode.

5. The shielded gate depletion mode power MOSFET of claim 1 wherein the dielectric isolation layer (9) has a thickness of 0 or more, and the shield gate (7) and the control gate (8) are connected together at the same potential when the dielectric isolation layer (9) has a thickness of 0.

6. The shielded gate depletion mode power MOSFET of claim 1 wherein the cell region further comprises a semiconductor body region (12) of the second conductivity type and a heavily doped source region (13) of the first conductivity type.

7. The shielded gate depletion mode power MOSFET of claim 6 wherein the first conductivity type is N-type and the second conductivity type is P-type.

8. The shielded gate depletion mode power MOSFET of claim 6 wherein the first conductivity type is P-type and the second conductivity type is N-type.

9. The shielded gate depletion mode power MOSFET of claim 1 wherein the trench structure is formed by etching over a semiconductor epitaxial layer (3).

10. The shielded gate depletion mode power MOSFET of any of claims 1 through 9, wherein the semiconductor material includes, but is not limited to, silicon.