CN205490496U - Matrix type keyboard operation discernment and coding circuit - Google Patents

Abstract

The utility model provides a matrix type keyboard operation discernment and coding circuit comprises matrix type keyboard, a shift register, the 2nd shift register, state code register, encoder. The circuit is via scanning pulse, the shift pulse who satisfies specific timing requirements, the control of latching the pulse, and the location of will operate the single bond, the state operation being maintain in key combination operation, keyboard converts active state sign indicating number and the invalid state sign indicating number of same binary system length to, invalid key that effective key of corresponding through the back output of encoder code and each active state sign indicating number number or export corresponds with all invalid state sign indicating numbers number, different single bond operation, key combination operation, keyboards is kept the state operation and is only embodied not the same at the status codes, the keyboard scanning circuit structure need not modifyd to if necessary increase/decrease keys operating function or adjustment button operating function, and it can only to need to change the encoder according to the corresponding relation between the status codes after the increase and decrease and the key number. The utility model circuit need not be compile and operating program, the reliable operation.

Description

A kind of matrix keyboard operation identifies and coding circuit

Technical field

This utility model relates to the scanning circuit of a kind of keyboard, and especially a kind of matrix keyboard operation identifies and coding circuit.

Background technology

Along with the development of embedded technology, the current commonly used microcontroller of each electronic product is as control core, keyboard As main input equipment, it is widely used.

Current keyboard scan is mainly controlled by microcontroller, needs to be carried out by the program in operation microcontroller, runs into Interference, causes program to run fast, and scanning imaging system is by cisco unity malfunction.

The patent of invention " fast scanning and positioning method of a kind of matrix keyboard " of Application No. CN201010153560.2 uses key The mode of dish down trigger enters the Scan orientation process of keyboard, uses the method that keyboard scan step is repeated several times to judge that button is No effectively, and the key assignments obtained is carried out condition adjudgement；If multiple repairing weld state is identical, then it is in steady statue, key assignments Effectively；If multiple repairing weld state is different, key assignments is invalid.Single key stroke or Macintosh operation need individually to judge, singly-bound in this way Operation, then enter singly-bound tupe；Macintosh operation in this way, then enter Macintosh tupe.Method solution described in this patent Determine the keyboard shake caused due to the mechanical property of keyboard self and cause the wrong Problem-Error such as key, continuous touching, and to group Close key and the support issue of repeat key.But described method single key stroke needs to process respectively with Macintosh operation；Do not account for key Plate-like state maintains a period of time to arrive the rear keyboard operation function just performing effectively operation；Increase and decrease button operation function or adjustment are pressed During key operation function, need to revise keyboard scan finder structure.

Summary of the invention

In order to solve the above-mentioned technical problem that existing keyboard scan localization method exists, this utility model provides a kind of matrix form key Dish operation identifies and coding circuit, matrix keyboard, the first shift register, the second shift register, conditional code deposit Device, encoder form.

Described a kind of matrix keyboard operation identifies and coding circuit is carried out synchronizing control by scanning impulse, shift pulse and latch pulse System.

Described matrix keyboard has X row, Y row, is provided with N bit keyboard status signal output；Described N bit keyboard state Signal is level signal；Described N=X+Y.Described matrix keyboard is provided with sampling pulse input.

Described first shift register has N parallel-by-bit input, N parallel-by-bit outfan and serial output terminal；Described second moves Bit register has serial input terminal, N parallel-by-bit outfan.

The N parallel-by-bit input of described first shift register is connected to N bit keyboard status signal output；Second displacement is posted The serial input terminal of storage is connected to the serial output terminal of the first shift register；First shift register, the second shift register Shift pulse input be connected to shift pulse, the presetting pulse input of the first shift register is connected to scanning impulse. The presetting pulse of described first shift register carries out input lock for the N parallel-by-bit of the first shift register inputs data Deposit.

Described conditional code depositor is 2 × N position binary register；N bit data input in conditional code depositor is connected to The N parallel-by-bit outfan of the first shift register, additionally N bit data input is connected to the N position of the second shift register also Row outfan；The reception pulse input end of described conditional code depositor is connected to latch pulse.

Described encoder have 2 × N position coding input end, described 2 × N position coding input end be connected to conditional code depositor 2 × N bit data outfan.

The sequential of described scanning impulse, shift pulse and latch pulse meets claimed below: in one cycle, and scanning impulse has 1 pulse, shift pulse has N number of pulse, and latch pulse has 1 pulse；Described scanning impulse, shift pulse and latch arteries and veins Punching goes round and begins again according to 1 scanning impulse, 1 latch pulse, the order of N number of shift pulse；Described scanning impulse and latch The cycle of pulse is 20～100ms.

Described first shift register, the second shift register shift pulse edge effective；The reception of described conditional code depositor Porch is effective；The presetting pulse edge of described first shift register is effective.

Described first shift register, the second shift register shift pulse edge effective；The reception of described conditional code depositor Porch is effective；When the presetting pulse high level of described first shift register is effective, described scanning impulse is positive pulse；Institute When stating the presetting pulse Low level effective of the first shift register, described scanning impulse is negative pulse.

The conditional code of 2 × N bit data outfan output, 2 × N position of described conditional code depositor；Described conditional code is by effective shape State code and disarmed state code composition；The key number of described encoder output is made up of effective key number and invalid key number；Described effective status Code is produced by effective keyboard operation or state, correspondence output corresponding effectively key number when encoder inputs each effective status code； Described disarmed state code is produced by invalid keyboard operation or state, and it is invalid that encoder inputs all corresponding output during all disarmed state codes Key number.

Described encoder has M position key outfan, and the selection of M value should meet 2^MMore than or equal to effective key number and invalid key number Quantity sum.

Described a kind of matrix keyboard operation identifies and coding circuit also includes keyboard state change pulse generation unit, is used for sentencing Whether the key number of disconnected matrix keyboard output changes, when the key number of matrix keyboard output changes, and run-out key plate-like State change pulse.

Described keyboard state change pulse generation unit by M position delay buffer, M XOR gate and or door form；M prolongs position Buffer is for carrying out signal delay respectively to the M position key number of matrix keyboard output late；The input of M XOR gate is respectively The input of M position delay buffer, output signal；The output of M XOR gate is respectively connecting to or the input of door；Or door Outfan output keyboard state change pulse.

Described matrix keyboard is enabled effective row three state buffer by X row-Y row key-press matrix, low level, high level enable has Effect row three state buffer, trailing edge latch effective row status register, rising edge latches effective column-shaped state depositor composition；All The line of key-press matrix is respectively connecting to the outfan of row three state buffer, and the alignment of all key-press matrixs is respectively connecting to row tri-state The outfan of buffer；All inputs of row three state buffer and row three state buffer are connected to low level；All key-press matrixs Line be respectively connecting to the input of row status register, the alignment of all key-press matrixs is respectively connecting to row status register Input；The outfan of described row status register and the outfan of row status register collectively constitute the output of keyboard state signal End.

Described low level enables effective row three state buffer, high level enables the enable control input of effective row three state buffer even It is connected to sampling pulse；Described trailing edge latches effective row status register, the reception arteries and veins of the rising edge effective column-shaped state depositor of latch Rush input and be connected to sampling pulse.

The operation of described a kind of matrix keyboard identifies and coding circuit also includes being made up of agitator, enumerator, pulsqe distributor Circuit；The circuit that described scanning impulse, shift pulse, latch pulse are made up of agitator, enumerator, pulsqe distributor produces Raw；Described pulsqe distributor is ROM memory.

The cycle of described sampling pulse is not more than the cycle of scanning impulse.It is generally selected scanning impulse, shift pulse, latch pulse One as sampling pulse.

Described N position, 2 × N position, M position refer both to binary digit data.

The beneficial effects of the utility model are: the location that will operate single key stroke, Macintosh operation, keyboard maintenance state, by Meet scanning impulse that specific time sequence requires, shift pulse, latch pulse control to be converted into the conditional code of same binary length, The mode using Unified coding processes, and the operation of single key stroke, Macintosh, keyboard maintain state operation to be only embodied in conditional code The most ibid；If needing increase and decrease button operation function or adjust button operation function, it is not necessary to amendment keyboard scanning circuit Structure, only need to be according to the corresponding relation change encoder between conditional code and the key number after increase and decrease, i.e. re-write read only memory Storage content.Described utility model circuit does not use the microcontroller such as single-chip microcomputer, ARM, need not run program, Reliable operation.

Accompanying drawing explanation

Fig. 1 is that a kind of matrix keyboard operation identifies and coding circuit theory diagram；

Fig. 2 is the matrix keyboard circuit diagram of this utility model embodiment；

Fig. 3 is the Scan orientation circuit diagram of this utility model embodiment；

Fig. 4 is the first shift-register circuit figure of this utility model embodiment；

Fig. 5 is the pulse sequence figure of this utility model embodiment；

Fig. 6 is the impulse circuit schematic diagram of this utility model embodiment；

Fig. 7 is the circuit diagram of the keyboard state change pulse generation unit of this utility model embodiment；

Fig. 8 is the waveform correlation schematic diagram that the keyboard of this utility model embodiment effectively operates.

Detailed description of the invention

Below in conjunction with accompanying drawing, the utility model is described in further detail.

Fig. 1 is that a kind of matrix keyboard operation identifies and coding circuit theory diagram, matrix keyboard the 400, first displacement post Storage the 100, second shift register 200, conditional code depositor 500, encoder 300 form.

Fig. 2 is the circuit diagram of the matrix keyboard 400 of this utility model embodiment, have 2 row, 2 row, totally 4 buttons, By button S1, button S2, button S3, button S4 be connected to the pull-up resistor R1 of power supply+VCC, pull-up resistor R2, pull-up resistor R3, pull-up resistor R4, and row three state buffer 401, row three state buffer 402, row Status register Device 403, row status register 404 form.2 outfans Y1, Y2 of row three state buffer 401 are respectively connecting to 2 Line, 2 outfans Y3, Y4 of row three state buffer 402 are respectively connecting to 2 alignments；Row three state buffer 401 He All input X1～X4 of row three state buffer 402 are connected to low level.

2 inputs D41, D42 of row status register 403 are respectively connecting to 2 lines, row status register 404 2 inputs D43, D44 are respectively connecting to 2 alignments；2 outfans Q41, Q42 of row status register 403 are defeated Trip status signal I1, I2,2 outfans Q43, Q44 of row status register 404 export row status signal I3, I4； 2 outfans of row status register 403 and 2 outfans of row status register 404 collectively constitute 4 bit keyboard state letters Number outfan, exports keyboard state signal I1, I2, I3, I4.

In embodiment, the enable input EN1 Low level effective of row three state buffer 401, the enable of row three state buffer 402 Input EN2 high level is effective；EN1 and EN2 is connected to the sampling pulse CK outfan of agitator 500.Row state is posted Storage 403 is connected to the sampling of agitator 500 with receive pulse input end CLK3, CLK4 of row status register 404 Pulse CK outfan, row status register 403 carries out data latch, row status register at the trailing edge of sampling pulse CK 404 carry out data latch at the rising edge of sampling pulse CK.

When row three state buffer 401 and row three state buffer 402 use the three state buffer of same model, such as, use three simultaneously During state buffer 74HC241, the enable input of 74HC241 is effective for high level, therefore, at sampling pulse CK outfan And between the enable input EN1 of row three state buffer 401, need to increase a not gate.Similarly, when row Status register Device 403 and row status register 404 use the data register of same model, and such as, row status register 403 and column-shaped state are posted When storage 404 all uses double D trigger 74HC74 to form data register, the triggering input of 74HC74 has for rising edge Effect, therefore, between the reception pulse input end CLK3 of sampling pulse CK outfan and row status register 403, needs Increase a not gate.

First shift register the 100, second shift register 200 in Fig. 1, conditional code depositor 500, encoder 300 Composition Scan orientation circuit, embodiment circuit diagram is as shown in Figure 3.The status signal of embodiment matrix keyboard circuit output has 4, therefore, first shift register the 100, second shift register 200 is all 4 binary shift registers, its In, the first shift register 100 has parallel input, parallel output and Serial output function, and the second shift register 200 has There are serial input, parallel output function；4 parallel input terminal L0～L3 of the first shift register 100 are sequentially connected to I1, I2, I3, I4, the serial that the serial input terminal D2 of the second shift register 200 is connected to the first shift register 100 is defeated Go out to hold Q13.Shift pulse input CLK1, CLK2 of first shift register the 100, second shift register 200 are equal Being connected to shift pulse CP2, the presetting pulse input CLK0 of the first shift register 100 is connected to scanning impulse CP1.

Conditional code depositor 500 requires to deposit 8 bit binary data, 4 companies in its 8 bit data input D57～D50 Being connected to parallel output terminal Q13～Q10 of the first shift register 100, other 4 are connected to the second shift register 200 Parallel output terminal Q23～Q20；In embodiment, D57～D54 be connected to Q23～Q20, D53～D50 be connected to Q13～ Q10.The reception pulse input end CLK5 of conditional code depositor 500 is connected to latch pulse CP3.

8 input A7～A0 of encoder 300 be connected to conditional code depositor 500 8 data output end Q57～ Q50.Encoder 300 output is scanned through positioning 4 the binary system keys number determined.

In Fig. 3 embodiment, the second shift register 200 can select to be made up of various medium-scale integration shift registers, or It is made up of edge triggered flip flop；When being formed the second shift register 200 by edge triggered flip flop, preferably triggered by the D of edging trigger Device forms.Conditional code depositor 500 is made up of edge triggered flip flop, is preferably made up of the d type flip flop of edging trigger, such as, It is made up of double D trigger 74HC74,4D trigger 74HC175,8D trigger 74HC273.

Fig. 4 is the circuit diagram of the first shift register 100 of this utility model embodiment, the lowest by 4 set, reset function The effective d type flip flop of level 101～104,8 NAND gate 105～112 compositions.In embodiment, d type flip flop 101～104 Selecting double D trigger 74HC74, it is effective that it triggers rising edge of a pulse.Scanning impulse CP1 by 8 NAND gate 105～ 112 control the set of d type flip flop 101～104, reset function.As a example by d type flip flop 101, scanning impulse CP1 is low During level, NAND gate 105, NAND gate 106 export high level, and the set of d type flip flop 101, reset function are invalid；Scanning When pulse CP1 is high level and L0=0, NAND gate 105 is output asNAND gate 106 is output as L0, i.e. D touches Send out device 101 set function is invalid, reset function effective, make Q10=0；Scanning impulse CP1 is high level and L0=1 Time, NAND gate 105 is output asNAND gate 106 is output as L0, i.e. the set function of d type flip flop 101 effectively, Reset function is invalid, makes Q10=1.The operation principle of d type flip flop 102～104, as d type flip flop 101, works as scanning When pulse CP1 is high level, Q10=L0, Q11=L1, Q12=L2, Q13=L3；When scanning impulse CP1 is low electricity At ordinary times, all connect due to triggering pulse input end CLK10, CLK11, CLK12, CLK13 of d type flip flop 101～104 Being connected to CP2, therefore, at the rising edge of each shift pulse CP2, the first shift register 100 moves once position, i.e. Q13 =Q12, Q12=Q11, Q11=Q10, Q10=0.

In Fig. 3 embodiment, encoder 300 is read only memory.Address input end A7～A0 of read only memory is encoder The input of 300, coding outfan C3～C0 that data output end D3～D0 is encoder 300 of read only memory.

The operation of a kind of matrix keyboard identifies and the operation principle of coding circuit is as follows:

Scan orientation circuit scanning impulse CP1, shift pulse CP2, latch pulse CP3 control under work, relevant Pulse sequence figure is as shown in Figure 5.

In embodiment, the sequential of CP1, CP2, CP3 meets claimed below: in one cycle, and CP1 has 1 pulse, CP2 has 4 pulses, and CP3 has 1 pulse；Each pulse is according to 1 CP1 pulse, 1 CP3 pulse, 4 CP2 arteries and veins The order of punching is gone round and begun again.

CP1, CP2, CP3 pulse meeting timing requirements can be produced by various pulsqe distributors, and Fig. 6 is this utility model The impulse circuit schematic diagram of embodiment, is made up of agitator 801, enumerator 802, pulsqe distributor 803.In Fig. 5 time Clock CP is produced by agitator, and CP delivers to enumerator 802 and counts, and enumerator 802 is 12 system Counters, its 12 states (numerical value) of result P are followed successively by P0 → P11, as shown in Figure 5.Pulsqe distributor 803 in embodiment is adopted Realize with ROM memory, hereon referred to as pulse distribution ROM memory.The address input of pulse distribution ROM memory Being connected to the counting output of enumerator 802,3 bit data outfans of pulse distribution ROM memory are output as CP1 arteries and veins respectively Punching, CP2 pulse, CP3 pulse.The write content of pulse distribution ROM memory is shown in Table 1.

Table 1 pulse distribution ROM memory tables of data

ROM memory address in table 1, i.e. enumerator output at least 4 binary codes.Generally, enumerator If 802 use binary addition rule, then corresponding 4 binary codes 0000～1011 of P0～P11 order, i.e. ROM deposits Memory address range is 0000～1011, and the storage content of address 0000～1011 is content corresponding for P0～P11 in table 1.

Pulse distribution ROM memory needs 3 bit data outputs.If the address input of pulse distribution ROM memory has R Position, when matrix keyboard has N bit keyboard status signal to export, the selection of R needs to meet 2^RMore than or equal to 2 × (N+ 2)。

Agitator 801 is multivibrator.CP1 scanning impulse, the cycle of CP3 latch pulse are 20～100ms. CP1, CP2, CP3 can also be operated the circuit outside identification and coding circuit by a kind of matrix keyboard or device provides.

In Fig. 2,4 buttons of matrix keyboard arrange with the matrix form of 2 × 2, and all of line all passes through upper with alignment Pull-up resistor is connected to power supply+VCC.Matrix keyboard is controlled by sampling pulse CK, uses reversal process to obtain keyboard state signal I4、I3、I2、I1.Such as, the keyboard state signal not having key to press is 1111, and the keyboard state signal that S1 presses is 1010, S1, the keyboard state signal that S2 presses simultaneously is 0010.4 binary codes of keyboard state signal are referred to as key assignments. Sampling pulse CK can select any one in scanning impulse CP1, shift pulse CP2, latch pulse CP3, preferably will Shift pulse CP2 is simultaneously as sampling pulse CK.

Sampling pulse CK controls to carry out matrix keyboard the method for sampling reading key assignments: at the low electricity of sampling pulse CK Flat, control all line output low levels by row three state buffer 401, row three state buffer 402 exports the open row of high-impedance state Line；Sampled by row status register 404 at the rising edge of sampling pulse CK and read high 2 as key assignments of alignment state；? The high level of sampling pulse CK, controls all alignment output low levels, row three state buffer by row three state buffer 402 The 401 open lines of output high-impedance state；Sampling pulse CK trailing edge by row status register 403 sample reading line state Low 2 as key assignments；Said process goes round and begins again, 4 of row status register 404, row status register 403 output Key assignments is always the last state of matrix keyboard.

Knowable to sampling pulse CK controls matrix keyboard is carried out the method that key assignments is read in sampling, row three state buffer 401 exists When the low level of sampling pulse CK enables effective, require that row status register 404 enters at the rising edge of sampling pulse CK simultaneously Row data latch, row three state buffer 402 enables effectively at the high level of sampling pulse CK, row status register 403 is taking The trailing edge of sample pulse CK carries out data latch.In turn, if row three state buffer 401 is electric at the height of sampling pulse CK When flat enable is effective, require that row status register 404 carries out data latch, row tri-state at the trailing edge of sampling pulse CK simultaneously Buffer 402 enables effectively in the low level of sampling pulse CK, row status register 403 is at the rising edge of sampling pulse CK Carry out data latch.

During above-mentioned sampling pulse CK controls sampling reading key assignments, row status register 403, row status register 404 moment precisely row three state buffer 402 and the row three state buffers 401 carrying out sampling are carried out the moment of state reversion, just Often the row status register 403 under work or row status register 404 can correctly be sampled.If requiring have in certain sequential Allowance, then can postpone being connected to the row three state buffer 402 sampling pulse CK with row three state buffer 401, side Method makes sampling pulse CK be then connected to row three state buffer 401 and row three state buffer 402 through RC delay circuit EN1, EN2, determined by RC delay circuit time delay, determines that the principle of the time delay of RC delay circuit is, postpones Sampling pulse CK phase place less than 90 °；Or sampling pulse CK is then connected to row after the buffering of several gate circuits Three state buffer 401 and EN1, EN2 of row three state buffer 402, time delay now is the total of described several gate circuit Decay time.

First shift register 100 status signal under the control of scanning impulse CP1, to matrix keyboard 400 output I1, I2, I3, I4 carry out data latch, and the now output of the first shift register 100 is referred to as now state key assignments；Second displacement is posted A upper periodic scanning pulses CP1 via the control of 4 CP2 pulses, was latching to the first displacement in a upper cycle by storage 200 The output of depositor 100 is displaced to the second shift register 200 outfan, and therefore, now the second shift register 200 is defeated Go out state key assignments before referred to as.

Existing state key assignments that first shift register 100 is exported by the latch pulse CP3 after scanning impulse CP1, the second displacement The front state key assignments of depositor 200 output is latched in the outfan of conditional code depositor 500, and the output of conditional code depositor 500 is same Sample is front state key assignments and existing state key assignments.

The equal edge of shift pulse of first shift register the 100, second shift register 200 is effective, and therefore, CP2 can be Positive pulse, it is also possible to be negative pulse；The reception porch of conditional code depositor 500 is effective, and therefore, CP3 can be positive arteries and veins Punching, it is also possible to be negative pulse.The presetting pulse of the first shift register 100 be edge effective time, scanning impulse CP1 is permissible It is positive pulse, it is also possible to be negative pulse.The presetting pulse of the first shift register 100 be high level effective time, it is desirable to scanning arteries and veins Rushing CP1 is positive pulse；When the presetting pulse of the first shift register 100 is Low level effective, it is desirable to scanning impulse CP1 is Negative pulse；In embodiment, the presetting pulse of the first shift register 100 is that high level is effective, so, scanning impulse CP1 Use positive pulse.

In embodiment, 4 existing state key assignments and 4 front state key assignments of the output of conditional code depositor 500 data output end collectively constitute 8 conditional codes.8 described conditional codes are used for current state and the mode of operation of recognition matrix formula keyboard.Such as, this enforcement In example, the conditional code pressed without key is 11111111；The conditional code of S1 key singly-bound push is 11111010；S1 key singly-bound The conditional code pressed and maintain is 10101010；The conditional code of S1 key singly-bound release operation is 10101111；S2 key singly-bound is pressed The conditional code of operation is 11110110；The conditional code of S4 key singly-bound push is 11110101；S2+S1 combination operation S1 push, represents after first pressing S2, maintains the state pressed to press the operation of S1, the conditional code of this operation again at S2 It is 01100010.

Encoder 300 is for being converted to key number by conditional code.In embodiment, it is provided with 6 effective keyboard operations and state, bag Include:

The singly-bound push of operation 0: button S1, key number is 0000；

The singly-bound push of operation 1: button S2, key number is 0001；

The singly-bound push of operation 2: button S3, key number is 0010；

Operation 3: button S3 singly-bound press after maintenance state, key number is 0011；

Operation 4: after button S4 singly-bound is pressed, then the Macintosh operation of the S2 that pushes button, key number is 0100；

The singly-bound release operation of operation 5: button S1, key number is 0101.

The conditional code obtained according to above-mentioned regulation and key number are shown in coding schedule 2:

Table 2 coding schedule

Keyboard operation	Conditional code (address)	Key number (storage data)
			S1 singly-bound is pressed	11111010	0000
S2 singly-bound is pressed	11110110	0001
			S3 singly-bound is pressed	11111001	0010
Maintenance pressed by S3 singly-bound	10011001	0011
			S4+S2 combination operation	01010100	0100
S1 singly-bound discharges	10101111	0101
			Other operation or states	********	1111

Encoder 300 is combinational logic circuit, designs circuit, meets the logical relation of table 2.

The encoder 300 of embodiment is preferably made up of read only memory 301.Read only memory 301 has 8 bit address, and totally 2⁸ Individual 4 binary storage cells.6 effective keyboard operations have 6 effective status codes, corresponding 6 effective keys with state Number；Using conditional code as address A7～A0 of read only memory 301, in the memory element corresponding with 6 effective status code-phase In, using corresponding key number as storage data write.The conditional code produced outside 6 effective keyboard operations and state is invalid Other operations in conditional code, i.e. table 2 or state produced be disarmed state code；In other memory element, all write Invalid key number, invalid key number is a value outside 6 effective keys number, and in embodiment, invalid key number is 1111.

Read only memory 301 always works at data output state.When read only memory 301 has sheet selected control system, data output During dash-control function, the output of its sheet selected control system, data should be made dash-control to be in effective status.

Key number in embodiment is 4 binary codes.The number of bits of key number can increase as required, or reduces, this Time, only need to select the read only memory 301 matched with this.If the selection that the number of bits of key number is M, M value 2 should be met^MQuantity sum more than or equal to effective key number with invalid key number.When matrix keyboard has N bit keyboard status signal defeated When going out, read only memory 301 needs the input of 2 × N bit address, and M-bit data exports.

If needing increase and decrease button operation function or adjust button operation function, table 2 only need to be revised as required, will amendment After content re-write the storage content of read only memory 301.

The edge of the latch pulse CP3 that conditional code depositor 500 carries out the moment of data latch is referred to as state latch edge, real Execute the rising edge for CP3 in example.In embodiment, when matrix keyboard S1 singly-bound is pressed, latch through CP1, CP3 two-stage After, from the beginning of the state latch edge of CP3, to the state latch edge of next CP3, outfan C3～C0 is defeated for coding Go out key number 0000；When matrix keyboard S2 singly-bound is pressed, after CP1, CP3 two-stage latches, from the state latch of CP3 Along starting, to the state latch edge of next CP3, run-out key number 0001；After matrix keyboard first presses S4, then Pressing S2, encoder 300 is pressed at S2 Macintosh, after CP1, CP3 two-stage latches, from the state latch edge of CP3 Start, to the state latch edge of next CP3, run-out key number 0100；When matrix keyboard S1 singly-bound discharges, pass through After CP1, CP3 two-stage latches, from the beginning of the state latch edge of CP3, to the state latch edge of next CP3, output Key number 0101；It can therefore be seen that when identify be effective button operation of matrix keyboard time, encoder 300 has at this The state latch of the CP3 after effect button operation is along starting, to the state latch edge of next CP3, and output duration It it is effective key number of a CP3 periodic width.

In embodiment, when matrix keyboard S3 singly-bound is pressed, encoder 300 is pressed at S3 singly-bound, through CP1, CP3 After two-stage latches, from the beginning of the state latch edge of CP3, to the state latch edge of next CP3, run-out key number 0010；Start on the state latch edge of ensuing CP3, press maintenance state to S3 singly-bound and terminate, through CP1, CP3 Till CP3 state latch edge after two-stage latch, encoder 300 run-out key number 0011；It can therefore be seen that when identification When being the maintenance state of matrix keyboard, encoder 300 exports the persistent period of effective key number and the persistent period of this maintenance state Adapt.

When outside the state of keyboard or operation are for 6 effective keyboard operations described in table 2 and state, encoder 300 is defeated Go out invalid key number 1111.Either exporting effective key number, or output invalid key number, encoder 300 changes output content Moment is the state latch edge of CP3；In embodiment, encoder 300 changes the rising edge that the moment is CP3 of output content.

The cycle of CP3 is the scan period of matrix keyboard.The keyboard scan cycle is when more than 20ms, it is possible to be effectively shielded from The impact of keyboard shake；The keyboard scan cycle, when below 100ms, is unlikely to omit keyboard operation；Therefore, CP3 Cycle should control 20～100ms.

Fig. 7 is the circuit diagram of the keyboard state change pulse generation unit of this utility model embodiment.It is matrix form key when identify During effective button operation of dish, the state latch of the encoder 300 CP3 after this effective button operation is along starting, to next Till the state latch edge of individual CP3, output duration is effective key number of a CP3 periodic width.Receive described matrix The device of formula keyboard output, needs the output of moment inquiry matrix keyboard, obtains key number.The period distances of inquiry is necessarily less than The cycle of CP3.

Whether circuit shown in Fig. 7 changes for the key number of judgment matrix formula keyboard output, when the key number of matrix keyboard output When changing, exporting keyboard state change pulse, the reception device receiving matrix formula keyboard for auxiliary moment configuration keyboard exports Key number, such as, using keyboard state change pulse as receive device interrupt request singal.

Circuit shown in Fig. 7 by delay buffer 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605, Or door 606 forms.Delay buffer 601 is made up of 4 edge triggered flip flops only with Trigger Function, 4 edge triggered flip flops The input that triggers be the reception pulse input end of delay buffer 601, be connected to CP3；Delay buffer 601 is at CP3 State latch along carrying out data latch.

Delay buffer 601 is for carrying out respectively at delay 4 bit data C3 of the coding outfan of encoder 300～C0 Reason.4 data input pin D63～D60 of delay buffer 601 be connected to encoder 300 coding outfan C3～ C0, the data that 4 data output end Q63～Q60 of delay buffer 601 export accordingly are C31～C01；C31～C01 After the first-level buffer of delay buffer 601, its signal postpones a CP3 pulse period than C3～C0, and Fig. 8 show The waveform correlation schematic diagram that the keyboard of this utility model embodiment effectively operates.The T1 being located at CP3 pulse is interval, matrix form key Taking inventory and the most effectively operating, the effectively operation of embodiment includes: S1 singly-bound is pressed, S2 singly-bound is pressed, S3 singly-bound is pressed, The S1 of S4+S1 combination operation presses, the S2 of S4+S2 combination operation presses, the release of S1 singly-bound.Once effectively operate Rising edge after CP3 pulse T1 interval in next state latch edge, i.e. Fig. 8, the coding of encoder 300 output C3～C0 changes；Interval at T2, encoder 300 exports efficient coding C3～C0 of a CP3 pulse period；? T3, T4 and afterwards interval, coding C3～C0 of encoder 300 output changes again and enters maintenance state, this maintenance State is probably such as S1 singly-bound and presses maintenance state below, exports invalid key number, it is also possible to S3 singly-bound is pressed below Maintenance state, exports effective key number, until the most effectively operating.

D6 pulse in Fig. 8 schematically illustrates coding C3～C0 of encoder 300 output and is in maintenance state, does not become Change, still change, side circuit does not exist described D6 pulse.As shown in Figure 8, D6 pulse is low level, Coding C3～C0 schematically illustrating encoder 300 output is in maintenance state, is not changed in；D6 pulse is high level, Schematically illustrate encoder 300 and export efficient coding C3～C0 in a cycle.Q6 reflection in Fig. 8 is C31～C01 Situation of change, it is clear that Q6 postpones a CP3 pulse period than D6.Equally, side circuit does not exist described Q6 arteries and veins Punching.

In Fig. 8, coding C3～C0 of encoder 300 output is in maintenance state, is not changed in, still changes, Really by 4 delay buffers 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door 606 logic circuits formed complete.4 XOR gates encode 1 phase in outfan C3～C0 respectively with encoder 300 Correspondence, input is respectively the input of 4 delay buffers 601, output signal.Such as, two input letters of XOR gate 602 Number be respectively C0 and C01, C01 than C0 postpone a CP3 pulse period, therefore, when C0 changes, XOR gate The positive pulse of 602 1 CP3 pulse period width of output；When C0 is a CP3 pulse period change width signal, different Or door 602 exports the positive pulse of 2 CP3 pulse period width.XOR gate 603, XOR gate 604, XOR gate 605 are respectively Judging whether C1～C3 changes, principle is with to judge whether C0 changes identical.XOR gate 602, XOR gate 603, XOR gate 604, the outfan of XOR gate 605 are respectively connecting to or the input of door 606, or door 606 is for comprehensive descision Whether C0～C3 changes, as long as C0～C3 changes, or door 606 i.e. exports keyboard state change pulse F, should Pulse is positive pulse.

In embodiment, delay buffer 601 selects the 8D trigger 74HC273 that rising edge triggers.

Delay buffer 601 can also use other schemes, such as, uses RC circuit, utilizes 4 RC circuit the most right C0～C3 postpones；If the time delay of RC circuit is less than a CP3 pulse period, then encoder 300 exports one During the efficient coding C3 in individual cycle～C0, start and export efficient coding C3～C0 to terminate at output efficient coding C3～C0 All producing a keyboard state change pulse, the width of keyboard state change pulse is equal to RC circuit delay time；If RC The time delay of circuit be more than or equal to a CP3 pulse period, then encoder 300 export a cycle efficient coding C3～ During C0, producing a keyboard state change pulse when exporting efficient coding C3～C0 and starting, this pulse width is more than or equal to 2 The individual CP3 pulse period.Require, less than 2 CP3 pulse periods, fail to report in order to avoid producing the time delay of RC circuit.

In described utility model circuit, by single key stroke, Macintosh operation, the location of keyboard maintenance state operation, by full 3 Pulse Width Control that foot specific time sequence requires are converted into the conditional code of same binary length, use the mode of Unified coding to carry out Process, single key stroke, Macintosh operation, keyboard maintain state operation be only embodied in conditional code the most ibid；If needing increase and decrease Button operation function or adjust button operation function, it is not necessary to amendment keyboard scanning circuit structure, only need to be according to increase and decrease after State code table updates encoder 300, i.e. re-writes the storage content of renewal read only memory.Described utility model circuit Do not use the microcontroller such as single-chip microcomputer, ARM, program, reliable operation need not be run.

Claims (8)

1. matrix keyboard operation identifies and coding circuit, it is characterised in that by matrix keyboard, the first shift register, Second shift register, conditional code depositor, encoder form；

Described matrix keyboard has X row, Y row, is provided with N bit keyboard status signal output；Described N bit keyboard status signal For level signal；Described N=X+Y；

Described first shift register has N parallel-by-bit input, N parallel-by-bit outfan and serial output terminal；Described second displacement is posted Storage has serial input terminal, N parallel-by-bit outfan；

The N parallel-by-bit input of described first shift register is connected to N bit keyboard status signal output；Second shift register Serial input terminal be connected to the serial output terminal of the first shift register；First shift register, the shifting of the second shift register Digit pulse input is connected to shift pulse, and the presetting pulse input of the first shift register is connected to scanning impulse；

Described conditional code depositor is 2 × N position binary register；N bit data input in conditional code depositor is connected to first The N parallel-by-bit outfan of shift register, additionally to be connected to the N parallel-by-bit of the second shift register defeated for N bit data input Go out end；The reception pulse input end of described conditional code depositor is connected to latch pulse；

Described encoder has 2 × N position coding input end, described 2 × N position coding input end to be connected to 2 × N position of conditional code depositor Data output end；Described encoder has M position key outfan.

A kind of matrix keyboard operation the most according to claim 1 identifies and coding circuit, it is characterised in that: described encoder For read only memory.

A kind of matrix keyboard operation the most according to claim 1 identifies and coding circuit, it is characterised in that: also include by shaking Swing device, enumerator, the circuit of pulsqe distributor composition；Described scanning impulse, shift pulse, latch pulse are by agitator, meter Number device, the circuit of pulsqe distributor composition produce.

A kind of matrix keyboard operation the most according to claim 3 identifies and coding circuit, it is characterised in that: described pulse divides Orchestration is ROM memory.

A kind of matrix keyboard operation the most according to claim 1 identifies and coding circuit, it is characterised in that: also include keyboard State change pulse generation unit.

A kind of matrix keyboard operation the most according to claim 5 identifies and coding circuit, it is characterised in that: described keyboard shape State change pulse generation unit by M position delay buffer, M XOR gate and or door form；M position delay buffer is for right The M position key number of matrix keyboard output carries out signal delay respectively；The input of M XOR gate is respectively M position delay buffer Input, output signal；The output of M XOR gate is respectively connecting to or the input of door；Or the outfan run-out key plate-like of door State change pulse.

A kind of matrix keyboard operation the most according to claim 1 identifies and coding circuit, it is characterised in that: described matrix form Keyboard is enabled effective row three state buffer by X row-Y row key-press matrix, low level, high level enables effective row Three-State Device, trailing edge latch effective row status register, rising edge latches effective column-shaped state depositor composition；The row of all key-press matrixs Line is respectively connecting to the outfan of row three state buffer, and the alignment of all key-press matrixs is respectively connecting to the output of row three state buffer End；All inputs of row three state buffer and row three state buffer are connected to low level；The line of all key-press matrixs connects respectively Being connected to the input of row status register, the alignment of all key-press matrixs is respectively connecting to the input of row status register；Described The outfan of row status register collectively constitutes keyboard state signal output part with the outfan of row status register.

A kind of matrix keyboard operation the most according to claim 7 identifies and coding circuit, it is characterised in that: described low level Enable effective row three state buffer, the enable of the high level effective row three state buffer of enable controls input and is connected to sampling pulse； Described trailing edge latches effective row status register, the reception pulse input end of the rising edge effective column-shaped state depositor of latch is connected to Sampling pulse.