CN108598162A - Enhanced GaN HEMT and preparation method with polarization matching barrier layer - Google Patents
Enhanced GaN HEMT and preparation method with polarization matching barrier layer Download PDFInfo
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- CN108598162A CN108598162A CN201810436768.1A CN201810436768A CN108598162A CN 108598162 A CN108598162 A CN 108598162A CN 201810436768 A CN201810436768 A CN 201810436768A CN 108598162 A CN108598162 A CN 108598162A
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- 230000004888 barrier function Effects 0.000 title claims abstract description 141
- 230000010287 polarization Effects 0.000 title claims abstract description 116
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 186
- 239000011241 protective layer Substances 0.000 claims description 32
- 238000005530 etching Methods 0.000 claims description 17
- 230000012010 growth Effects 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 235000012431 wafers Nutrition 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 10
- 239000002253 acid Substances 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000000407 epitaxy Methods 0.000 claims description 4
- 238000005036 potential barrier Methods 0.000 claims description 2
- 230000003628 erosive effect Effects 0.000 claims 2
- 229910002601 GaN Inorganic materials 0.000 description 47
- 230000005533 two-dimensional electron gas Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910015844 BCl3 Inorganic materials 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000034655 secondary growth Effects 0.000 description 2
- 230000002269 spontaneous effect Effects 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The present invention discloses a kind of enhanced GaN HEMT with polarization matching barrier layer, is followed successively by substrate, buffer layer, channel layer and Al from the bottom to topxInyGa1‑x‑yN barrier layers, the AlxInyGa1‑x‑yThere is isolated area at N barrier layers edge, the Al of active area within isolated areaxInyGa1‑x‑yActive electrode, drain electrode and gate electrode on N barrier layers, the AlxInyGa1‑x‑yN barrier layers are more than the polarization mismatch barrier layer of channel layer by polarization intensity and polarization intensity matches barrier layer with the matched polarization of channel layer and is combined into, and the polarization matching barrier layer is located in gate electrode orthographic projection lower zone.With high threshold voltage and low raceway groove conducting resistance, preparation method stablizes repeatable and high uniformity.
Description
Technical field
The invention belongs to HEMT devices preparation field more particularly to a kind of available high threshold voltages
And threshold voltage stabilization, can bear high gate voltage, raceway groove conducting resistance it is low have polarization matching barrier layer enhanced GaN
HEMT and preparation method.
Background technology
GaN high electron mobility transistor device（GaN HEMT）It is to be based on gallium nitride（GaN）The high electronics of material moves
Shifting rate transistor（HEMT）, it is mainly used in microwave radio and electronic power switch field.The structure of traditional GaN HEMT be by
Under supreme be followed successively by substrate, buffer layer, channel layer and AlxInyGa1-x-yN barrier layers, AlxInyGa1-x-yN barrier layers edge have every
From area, the Al of active area within isolated areaxInyGa1-x-yActive electrode, drain electrode and gate electrode on N barrier layers.
Undoped tri-nitride only can be obtained highdensity two-dimensional electron gas with itself distinctive polarity effect, because
This GaN HEMT device is normally on device, also known as depletion device, and in terminal applies especially electronic power switch field, lead to
Often require normally-off device, also known as enhancement device.To obtain enhanced GaN HEMT, voltage or application are not applied in gate electrode
The two-dimensional electron gas of base part should exhaust under the conditions of negative voltage, and apply the item that positive voltage is higher than threshold voltage in gate electrode
Conducting charge is generated under part, realizes break-over of device.The technological difficulties that the enhanced GaN HEMT of high-performance are industries are steadily obtained,
Desired technology requires to include：1）High threshold voltage；2）Low raceway groove conducting resistance；3）Preparation method stablizes repeatable and uniformity
It is high.The prior art is broadly divided into following three kinds：1）In AlxInyGa1-x-yRegion is specified above N barrier layers（The grid subsequently prepared
Base part）Grow p-type GaN cap or p-type AlGaN cap layers, the enhancement device grid leakage current that this method obtains it is larger and
It cannot bear high voltage（1.5 ~ 2 V of threshold voltage）；2）In AlxInyGa1-x-yN barrier layers specify region（The grid subsequently prepared
Base part）Ion implanting is carried out to exhaust the two-dimensional electron gas in raceway groove, the enhancement device threshold value that this method obtains
Voltage is unstable at high temperature；3）In AlxInyGa1-x-yN barrier layers specify region（Below the gate electrode subsequently prepared）It carries out
Dry etching, by AlxInyGa1-x-yN barrier layers largely or entirely etch away, and then in the area deposition dielectric and make
Standby gate electrode, the enhancement device threshold voltage obtained using this method can be in by dielectric layer and interface and dielectric layer
Dislocation charge influences.
Invention content
The present invention is to provide a kind of available high threshold voltage to solve the above-mentioned technical problem present in the prior art
And threshold voltage stabilization, can bear high gate voltage, raceway groove conducting resistance it is low have polarization matching barrier layer enhanced GaN
HEMT。
Technical solution of the invention is：It is a kind of have polarization matching barrier layer enhanced GaN HEMT, by down toward
On be followed successively by substrate, buffer layer, channel layer and AlxInyGa1-x-yN barrier layers, the AlxInyGa1-x-yN barrier layers edge have every
From area, the Al of active area within isolated areaxInyGa1-x-yActive electrode, drain electrode and gate electrode, described on N barrier layers
AlxInyGa1-x-yThe polarization that N barrier layers are more than channel layer by polarization intensity mismatches barrier layer and polarization intensity and channel layer
The polarization matching barrier layer matched is combined into, and the polarization matching barrier layer is located in gate electrode orthographic projection lower zone.
A kind of preparation method of the above-mentioned enhanced GaN HEMT that there is polarization to match barrier layer, successively in accordance with the following steps
It carries out：
A. epitaxial growth has substrate, buffer layer, channel layer and AlxInyGa1-x-yThe GaN HEMT wafers of N barrier layers,
AlxInyGa1-x-yN barrier layers are that polarization mismatches barrier layer；
B. barrier layer medium protective layer prepared above is mismatched in polarization；
C. dry etching is carried out after medium protective layer coated thereon photoresist, photoetching development and terminates in polarization mismatching gesture
Barrier layer forms figure in medium protective layer after removing photoresist；
D. use medium protective layer as mask, mismatching barrier layer portion region to polarization according to figure carries out dry etching, carves
It is consistent with polarization mismatch barrier layer to lose depth；
E. by the wafer secondary epitaxy growth polarization matching barrier layer after above-mentioned etching, thickness mismatches barrier layer with polarization
It is identical；
F. the method for utilizing wet etching, in BOE or HF acid solutions outside stripping media protective layer and its diauxic growth of top
Prolong layer；
G. device isolation region, source electrode, drain electrode and gate electrode are prepared, polarization matching barrier layer is located under gate electrode orthographic projection
In square region, that is, the enhanced GaN HEMT with polarization matching barrier layer are made.
A kind of preparation method of the above-mentioned enhanced GaN HEMT that there is polarization to match barrier layer, successively in accordance with the following steps
It carries out：
A. epitaxial growth has substrate, buffer layer, channel layer and AlxInyGa1-x-yThe GaN HEMT wafers of N barrier layers,
AlxInyGa1-x-yN barrier layers are polarization matching barrier layers；
B. barrier layer medium protective layer prepared above is matched in polarization；
C. dry etching is carried out after medium protective layer coated thereon photoresist, photoetching development and terminates in polarization matching potential barrier
Layer, forms figure in medium protective layer after removing photoresist；
D. it uses medium protective layer as mask, dry etching, etching is carried out to polarization matching barrier layer portion region according to figure
Depth is consistent with polarization matching barrier layer；
E. the wafer secondary epitaxy growth polarization after above-mentioned etching is mismatched into barrier layer, thickness matches barrier layer with polarization
It is identical；
F. the method for utilizing wet etching, in BOE or HF acid solutions outside stripping media protective layer and its diauxic growth of top
Prolong layer；
G. device isolation region, source electrode, drain electrode and gate electrode are prepared, polarization matching barrier layer is located under gate electrode orthographic projection
In square region, that is, the enhanced GaN HEMT with polarization matching barrier layer are made.
Compared with prior art, the present invention having the following advantages that：
（1）By polarizing, matched principle can get high threshold voltage（2.5V）；
（2）Polarization matching barrier layer below gate electrode can bear high gate voltage, without introducing dielectric layer, therefore threshold voltage not by
The influence of dielectric layer dislocation charge, it is highly stable；
（3）When the applied positive voltage of gate electrode is higher than threshold voltage, two dimension electricity is generated in polarization matching barrier layer lower channels
Sub- gas is connect with the two-dimensional electron gas of exterior domain, and the electron mobility under electrons transport property especially high electric field is better than
GaN body materials effectively reduce raceway groove conducting resistance.
（4）Preparation method is stablized, repeatable and high uniformity.
Description of the drawings
Fig. 1 is the structural schematic diagram of Example 1 and Example 2 of the present invention.
Fig. 2 is that the polarization of the embodiment of the present invention 1 matching barrier layer mismatches barrier layer to the energy band diagram of channel layer with polarization.
Fig. 3 is the transfer curve comparison diagram of the embodiment of the present invention and existing depletion type GaN HEMT.
Specific implementation mode
Embodiment 1：
The present invention's has the enhanced GaNHEMT of polarization matching barrier layer as shown in Figure 1：It is same as the prior art from the bottom to top
It is followed successively by substrate 1, buffer layer 2, GaN channel layers 3 and AlxInyGa1-x-yN barrier layers 4, AlxInyGa1-x-y4 edge of N barrier layers has
Isolated area 5, the Al of active area within isolated area 5xInyGa1-x-yActive electrode 6, drain electrode 7 and gate electrode 8 on N barrier layers 4,
With the prior art except that AlxInyGa1-x-yThe polarization that N barrier layers 4 are more than GaN channel layers 3 by polarization intensity mismatches gesture
Barrier layer 4-1（Al0.2Ga0.8N）With polarization intensity barrier layer 4-2 is matched with the matched polarization of GaN channel layers 3（In0.2Al0.8N）It spells
At polarization matching barrier layer 4-2 is located in 8 orthographic projection lower zone of gate electrode, can be less than or equal under 8 orthographic projection of gate electrode
Square region.
AlxInyGa1-x-yThe polarization intensity P of Ntotal(AlxInyGa1-x-yN) it is spontaneous polarization PSP(AlxInyGa1-x-yN) and
Piezoelectric polarization PPZ (AlxInyGa1-x-yN) the sum of two parts：
PSP (Al x InyGa1-x-y N) = xPSP(AlN) + yPSP(InN) + (1-x-y)PSP(GaN) + 0.0191x(1-x-y) + 0.0378y(1-x-y) + 0.0709xy,
PPZ (Al x InyGa1-x-y N) = xPPZ(AlN) + yPPZ(InN) + (1-x-y) PPZ(GaN),
Wherein, PSP (AlN)、PSP(InN) and PSP(GaN) be respectively AlN, InN, GaN spontaneous polarization strength, PPZ
(AlN)、PPZ(InN) and PPZ(GaN) be respectively AlN, InN, GaN piezoelectric polarization intensity.Polarization matching needs to meet
AlxInyGa1-x-yThe total polarization intensity of N barrier layers and AlxInyGa1-x-yThe total polarization intensity of N-channel layer is consistent or close（Not
It is less than 5% with degree, and mismatch degree is the smaller the better）.
Preparation method is as follows：
A. according to the prior art, epitaxial growth has Al0.2Ga0.8The GaN HEMT wafers of N barrier layers, from the bottom to top successively
For substrate 1, buffer layer 2, GaN channel layers 3 and Al0.2Ga0.8N barrier layers 4, Al0.2Ga0.84 thickness of N barrier layers is 25 nm, is pole
Change the polarization mismatch barrier layer 4-1 that intensity is more than GaN channel layers 3；
B. barrier layer 4-1 is mismatched above with PECVD method deposition medium protective layers SiO in polarization2；
C. fluoro-gas is utilized after medium protective layer coated thereon photoresist, photoetching development（CF4、CHF3、 C2F4、C2F6、
SF6Deng）To the medium protective layer SiO in the regions matching barrier layer 4-2 of subsequently polarizing in the etching apparatus such as RIE or ICP2It is done
Method etches, and mismatches barrier layer 4-1 in polarization using the different natural terminations of different materials etching gas, in medium after removing photoresist
Being formed on protective layer has the figure in the regions polarization matching barrier layer 4-2；The regions polarization matching barrier layer 4-2 should be less than or be equal to
8 orthographic projection region of gate electrode；
D. using above-mentioned patterned medium protective layer as mask, chlorine-containing gas is utilized（Cl2、BCl3Deng）In RIE or ICP etc.
Barrier layer 4-1 is mismatched to the polarization in the regions polarization matching barrier layer 4-2 in etching apparatus and carries out dry etching, and is rested on
GaN channel layers 3, i.e. etching depth are consistent with polarization mismatch barrier layer 4-1 depth；
E. the wafer after above-mentioned etching is placed in MOCVD reaction chambers, carries out diauxic growth In0.2Al0.8N barrier layer 4-2,
Its polarization intensity is matched with GaN channel layers 3, and thickness is identical as polarization mismatch barrier layer 4-1 thickness；
F. the method for utilizing wet etching removes the medium protective layer and thereon in previous step in the solution such as BOE or HF acid
The secondary growth epitaxial layer of side so far there is the enhanced GaN HEMT epitaxial structures preparation of polarization matching barrier layer to finish；
G. device isolation region 5, source electrode 6, drain electrode 7 and gate electrode 8, polarization matching barrier layer 4-2 are prepared according to prior art
In 8 orthographic projection lower zone of gate electrode, that is, the enhanced GaN HEMT with polarization matching barrier layer are made.
Embodiment 2：
The present invention's has the enhanced GaNHEMT of polarization matching barrier layer as shown in Figure 1：It is same as the prior art from the bottom to top
It is followed successively by substrate 1, buffer layer 2, GaN channel layers 3 and AlxInyGa1-x-yN barrier layers 4, AlxInyGa1-x-y4 edge of N barrier layers has
Isolated area 5, the Al of active area within isolated area 5xInyGa1-x-yActive electrode 6, drain electrode 7 and gate electrode 8 on N barrier layers 4,
With the prior art except that AlxInyGa1-x-yThe polarization that N barrier layers 4 are more than GaN channel layers 3 by polarization intensity mismatches gesture
Barrier layer 4-1（Al0.3Ga0.7N）With polarization intensity barrier layer 4-2 is matched with the matched polarization of GaN channel layers 3（In0.2Al0.8N）It spells
At polarization matching barrier layer 4-2 is located in 8 orthographic projection lower zone of gate electrode, can be less than or equal under 8 orthographic projection of gate electrode
Square region.
Preparation method is as follows：
A. according to the prior art, epitaxial growth has In0.2Al0.8The GaN HEMT wafers of N barrier layers, from the bottom to top successively
For substrate 1, buffer layer 2, GaN channel layers 3 and In0.2Al0.8N barrier layers 4, In0.2Al0.84 thickness of N barrier layers is 25 nm, is
Polarization intensity matches the polarization matching barrier layer 4-2 of GaN channel layers 3；
B. in polarization matching barrier layer 4-2 above with PECVD method deposition medium protective layers SiO2；
C. fluoro-gas is utilized after medium protective layer coated thereon photoresist, photoetching development（CF4、CHF3、 C2F4、C2F6、
SF6Deng）The medium protective layer SiO in the regions barrier layer 4-1 is mismatched to subsequently polarizing in the etching apparatus such as RIE or ICP2It carries out
Dry etching, and barrier layer 4-2 is matched in polarization using the different natural terminations of different materials etching gas, in medium after removing photoresist
The figure that there is polarization to mismatch the regions barrier layer 4-1 is formed on protective layer；The regions polarization matching barrier layer 4-2 should be less than or wait
In 8 orthographic projection region of gate electrode；
D. using above-mentioned patterned medium protective layer as mask, chlorine-containing gas is utilized（Cl2、BCl3Deng）In RIE or ICP etc.
The polarization matching barrier layer 4-2 for mismatching the regions barrier layer 4-1 in etching apparatus to polarization carries out dry etching, and rests on
GaN channel layers 3, i.e. etching depth are consistent with polarization matching barrier layer 4-2 depth；
E. the wafer after above-mentioned etching is placed in MOCVD reaction chambers, carries out diauxic growth Al0.3Ga0.7N barrier layer 4-1,
Its polarization intensity is more than GaN channel layers 3, and thickness is identical as polarization matching barrier layer 4-2 thickness；
F. the method for utilizing wet etching removes the medium protective layer and thereon in previous step in the solution such as BOE or HF acid
The secondary growth epitaxial layer of side so far there is the enhanced GaN HEMT epitaxial structures preparation of polarization matching barrier layer to finish；
G. device isolation region 5, source electrode 6, drain electrode 7 and gate electrode 8, polarization matching barrier layer 4-2 are prepared according to prior art
In 8 orthographic projection lower zone of gate electrode, that is, the enhanced GaN HEMT with polarization matching barrier layer are made.
The polarization of the embodiment of the present invention 1 matching barrier layer mismatches barrier layer to energy band diagram such as Fig. 2 institutes of channel layer with polarization
Show.The polarity effect that polarization mismatches barrier layer makes the interface between barrier layer and channel layer form Quantum Well, and has two
Dimensional electron gas generates, as depletion type；And polarize and match barrier layer because consistent with channel layer polarization intensity, there is no amounts for interface
Sub- trap is as enhanced also without two-dimensional electron gas.Further, simulation calculating is carried out by simulation software and compares source-drain voltage
VdsDepletion type GaN HEMT and the transfer characteristic curve of the embodiment of the present invention 1 are as shown in Figure 3 in the case of=10 V.Depletion type GaN
The threshold voltage of HEMT is -3 V, i.e., gate electrode needs negative voltage of the application absolute value more than 3 V that could turn off device；This hair
The threshold voltage of bright embodiment 1 is the high voltage that 2.5 V and gate electrode can bear 8 V or more, and drain current densities are close to 500
MA/mm shows that raceway groove conducting resistance is relatively low.
Claims (3)
1. a kind of enhanced GaN HEMT with polarization matching barrier layer, are followed successively by substrate from the bottom to top（1）, buffer layer（2）、
Channel layer（3）And AlxInyGa1-x-yN barrier layers（4）, the AlxInyGa1-x-yN barrier layers（4）There is isolated area at edge（5）, every
From area（5）Within active area AlxInyGa1-x-yN barrier layers（4）Upper active electrode（6）, drain electrode（7）And gate electrode（8）,
It is characterized in that：The AlxInyGa1-x-yN barrier layers（4）Channel layer is more than by polarization intensity（3）Polarization mismatch barrier layer
（4-1）With polarization intensity and channel layer（3）Matched polarization matches barrier layer（4-2）It is combined into, the polarization matches barrier layer（4-
2）Positioned at gate electrode（8）In orthographic projection lower zone.
2. a kind of preparation method for the enhanced GaN HEMT that there is polarization to match barrier layer as described in claim 1, feature
It is to carry out in accordance with the following steps successively：
A. epitaxial growth has substrate（1）, buffer layer（2）, channel layer（3）And AlxInyGa1-x-yN barrier layers（4）GaN
HEMT wafers, AlxInyGa1-x-yN barrier layers（4）It is that polarization mismatches barrier layer（4-1）；
B. barrier layer is mismatched in polarization（4-1）Medium protective layer prepared above；
C. dry etching is carried out after medium protective layer coated thereon photoresist, photoetching development and terminates in polarization mismatching gesture
Barrier layer（4-1）, figure is formed after removing photoresist in medium protective layer；
D. it uses medium protective layer as mask, barrier layer is mismatched to polarization according to figure（4-1）Subregion carries out dry method quarter
Erosion, etching depth mismatch barrier layer with polarization（4-1）Unanimously；
E. by the wafer secondary epitaxy growth polarization matching barrier layer after above-mentioned etching（4-2）, thickness and polarization mismatch gesture
Barrier layer（4-1）It is identical；
F. the method for utilizing wet etching, in BOE or HF acid solutions outside stripping media protective layer and its diauxic growth of top
Prolong layer；
G. device isolation region is prepared（5）, source electrode（6）, drain electrode（7）And gate electrode（8）, polarization matching barrier layer（4-2）Position
In gate electrode（8）In orthographic projection lower zone, that is, the enhanced GaN HEMT with polarization matching barrier layer are made.
3. a kind of preparation method for the enhanced GaN HEMT that there is polarization to match barrier layer as described in claim 1, feature
It is to carry out in accordance with the following steps successively：
A. epitaxial growth has substrate（1）, buffer layer（2）, channel layer（3）And AlxInyGa1-x-yN barrier layers（4）GaN
HEMT wafers, AlxInyGa1-x-yN barrier layers（4）It is polarization matching barrier layer（4-2）；
B. barrier layer is matched in polarization（4-2）Medium protective layer prepared above；
C. dry etching is carried out after medium protective layer coated thereon photoresist, photoetching development and terminates in polarization matching potential barrier
Layer（4-2）, figure is formed after removing photoresist in medium protective layer；
D. it uses medium protective layer as mask, barrier layer is matched to polarization according to figure（4-2）Subregion carries out dry method quarter
Erosion, etching depth match barrier layer with polarization（4-2）Unanimously；
E. the wafer secondary epitaxy growth polarization after above-mentioned etching is mismatched into barrier layer（4-1）, thickness with polarization match gesture
Barrier layer（4-2）It is identical；
F. the method for utilizing wet etching, in BOE or HF acid solutions outside stripping media protective layer and its diauxic growth of top
Prolong layer；
G. device isolation region is prepared（5）, source electrode（6）, drain electrode（7）And gate electrode（8）, polarization matching barrier layer（4-2）Position
In gate electrode（8）In orthographic projection lower zone, that is, the enhanced GaN HEMT with polarization matching barrier layer are made.
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| KR101008272B1 (en) * | 2008-09-25 | 2011-01-13 | 전자부품연구원 | Normally off nitride high electron mobility transistor and method for manufacturing thereof |
| CN104201202A (en) * | 2014-09-17 | 2014-12-10 | 电子科技大学 | Gallium-nitride-based heterostructure field effect transistor with composite barrier layers |
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| KR101008272B1 (en) * | 2008-09-25 | 2011-01-13 | 전자부품연구원 | Normally off nitride high electron mobility transistor and method for manufacturing thereof |
| CN104201202A (en) * | 2014-09-17 | 2014-12-10 | 电子科技大学 | Gallium-nitride-based heterostructure field effect transistor with composite barrier layers |
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| CN111463260A (en) * | 2020-03-10 | 2020-07-28 | 芜湖启迪半导体有限公司 | Vertical high electron mobility field effect transistor and preparation method thereof |
| CN111463260B (en) * | 2020-03-10 | 2022-09-13 | 安徽长飞先进半导体有限公司 | Vertical high electron mobility field effect transistor and preparation method thereof |
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