CN102646705A - Metal insulated semi-conductor (MIS) grid GaN base enhancing high electro mobility transistor (HEMT) device and manufacture method - Google Patents
Metal insulated semi-conductor (MIS) grid GaN base enhancing high electro mobility transistor (HEMT) device and manufacture method Download PDFInfo
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Abstract
The invention discloses a metal insulated semi-conductor (MIS) grid GaN base enhancing high electro mobility transistor (HEMT) device and a manufacture method, which mainly solve the problems that the existing GaN base enhancing device is low in threshold voltage, poor in controllability and low in reliability. The device comprises a substrate (1), a transition layer (2), a GaN main buffering layer (3) and an N-type AlGaN main barrier layer (4). A source (9) and a drain (10) are arranged on two sides of the top end of the N-type AlGaN main barrier layer (4), a grid (13) is arranged in the middle of the top end of the source (9) and the drain (10), a groove (5) is etched in the middle of the GaN main buffering layer (3), the bottom of the groove is a 0001 polarity plane, a lateral side of the groove is a non-0001 plane, and an inner wall of the groove extends outwards to form a GaN auxiliary buffering layer (6), a AlGaN auxiliary barrier layer (7) and a medium layer (8). The grid (13) is deposited on the medium layer (8). The MIS grid GaN base enhancing HEMT device and the manufacture method have the advantages of being high in threshold voltage, good in regulation performance, high in current density, good in pinching-off performance, simple and mature in manufacture process and good in repeatability and can be used for high temperature high power application situations and digital circuits.
Description
Technical field
The invention belongs to microelectronics technology, relate to semiconductor device, a kind of specifically MIS grid GaN base enhancement mode HEMT device and manufacture method can be used for the high temperature high power application scenario and constitute the digital circuit elementary cell.
Background technology
Along with the development of modern weapons equipment and Aero-Space, nuclear energy, the communication technology, automotive electronics, Switching Power Supply, to the demands for higher performance of semiconductor device.Typical case's representative as semiconductor material with wide forbidden band; Characteristics such as the GaN sill has that energy gap is big, the electronics saturation drift velocity high, critical disruptive field intensity is high, thermal conductivity is high, good stability, corrosion-resistant, radioresistance can be used for making high temperature, high frequency and high-power electronic device.In addition, GaN also has good characteristic electron, can form the AlGaN/GaN heterostructure of modulation doping with AlGaN, and this structure at room temperature can obtain to be higher than 1500cm
2The electron mobility of/Vs, and up to 3 * 10
7The peak value velocity of electrons and 2 * 10 of cm/s
7The saturated electrons speed of cm/s, and obtain the two-dimensional electron gas density higher than second generation compound semiconductor heterostructure, being described as is the ideal material of development microwave power device.Therefore, the high electron mobility transistor (HEMT) based on the AlGaN/GaN heterojunction has extraordinary application prospect aspect the microwave high power device.
Because the advantageous advantage of AlGaN/GaN heterojunction, the development of the growth of AlGaN/GaN heterojunction material and AlGaN/GaN HEMT device is all the time in occupation of main status that the GaN electronic device is studied.Yet the major part work to the research of GaN base electron device concentrates on depletion-mode AlGaN/GaN HEMT device for over ten years; This is because the existence of strong polarization charge in the AlGaN/GaN heterostructure; Make the enhancement device of making based on GaN become very difficult, so the research of high-performance AlGaN/GaN enhancement mode HEMT have very important significance.
AlGaN/GaN enhancement mode HEMT has broad application prospects.At first; It is the ideal material of development microwave power device that the GaN sill is described as; And enhancement device in circuit such as microwave power amplifier and low noise amplifier owing to reduced negative voltage source; Thereby greatly reduce the complexity and the cost of circuit, and AlGaN/GaN enhancement mode HEMT device has good circuit compatibility property at microwave high power device and circuit.Simultaneously, the development of enhancement device makes the digital circuit of the integrated depletion type/enhancement device of monolithic become possibility.And in the power application facet of opening the light, AlGaN/GaN enhancement mode HEMT also has very big application prospect.Thereby the research of high-performance AlGaN/GaN enhancement mode HEMT device has obtained great attention.
At present, no matter be domestic or in the world, the reports about AlGaN/GaN enhancement mode HEMT are arranged all much.Because P type Mg doping process technology is still immature; Mg activation energy height in the GaN sill and ionization rate is low; Cause the device hole concentration low and mobility is big; Therefore current in the world to the research of AlGaN/GaN enhancement mode HEMT not on P type Mg mixes this method, but adopted other new technology, at present report mainly contain following several kinds technological:
1.F ion implantation technique; Promptly based on the plasma injection technique of fluoride CF4, people such as the Yong Cai of Hong Kong University of Science and Thchnology have successfully developed the enhancement mode HEMT device based on the F ion implantation technique, and this device is through injecting the F ion in the AlGaN barrier layer under AlGaN/GaN HEMT grid; Because the strong elecrtonegativity of F ion; F ion in the barrier layer can provide stable negative electrical charge, thereby can effectively exhaust the strong two-dimensional electron gas of channel region, when the F number of ions in the AlGaN barrier layer reaches some; The two-dimensional electron gas at grid lower channel place exhausts fully, thereby realizes enhancement mode HEMT device.But the F injection technique inevitably can be introduced the damage of material, and the controllability of device threshold voltage is not high.This device at room temperature the thin layer carrier concentration up to 1.3 * 10
13Cm
-2, mobility is 1000cm
2/ Vs, threshold voltage reaches 0.9V, and maximum drain current reaches 310mA/mm.Referring to document Yong Cai; Yugang Zhou, Kevin J.Chen and Kei May Lau, " High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment "; IEEE Electron Device Lett; Vol.26, No.7, JULY 2005.
2. nonpolar or semi-polarity GaN material is realized enhancement device; People such as Masayuki Kuroda successfully use a face (1120) the n-AlGaN/GaN HEMT on r face (1102) sapphire to realize the enhancing of device; Because nonpolar or semi-polarity material is owing to lack polarity effect; Therefore its two-dimensional electron gas is very little even do not have, so have enhanced characteristic based on the AlGaN/GaN HEMT device of nonpolar or semi-polarity material.The threshold voltage of its report is-0.5V, mixes concentration through reduction and can further increase device threshold voltage, but its device property and bad, its electron mobility has only 5.14cm
2/ Vs, room temperature lower block resistance is very big.And its grid leak TV university is little to have reached 1.1 * 10 when Vgs=-10V
-5A/mm.Referring to document Masayuki Kuroda, Hidetoshi Ishida, Tetsuzo Ueda; And Tsuyoshi Tanaka; " Nonpolar (11-20) plane AlGaN/GaN heterojunction field effect transistors on (1-102) plane sapphire ", Journal of Aplied Phisics, Vol.102; No.9, November 2007.
3. thin barrier layer technology; 1996; People such as M.Asif Khan have at first realized AlGaN/GaN enhancement mode HEMT device with the thin barrier layer technology of AlGaN of 10nm, and thin barrier layer AlGaN/GaN enhancement mode HEMT device is owing to the barrier layer thickness attenuate, and its polarity effect weakens; The raceway groove place two-dimensional electron gas that is caused by polarity effect reduces, thereby realizes moving to right of device threshold voltage.But the result that they obtain is unsatisfactory, and its peak value mutual conductance has only 23mS/mm.Referring to document M.Asif Khan, Q.Chen, C.J.Sun; J.W.Yang; And M.Blasingame, " Enhancement and depletion mode GaN/AlGaN heterostructure field effect transistors ", Appl.Phys.Lett.Vol.68; No.4, January 1996.
4. groove gate technique, people such as W.B.Lanford utilize the groove gate technique to make the enhancement device that threshold voltage reaches 0.47V through MOCVD, and this device architecture comprises from bottom to top: the SiC substrate; Nucleating layer, the GaN that 2um is thick, the AlGaN that 3nm is thick; The n-AlGaN that 10nm is thick, the AlGaN that 10nm is thick.After ohm annealing; Directly do not evaporate the grid metal electrode; But earlier under 700 ℃ nitrogen atmosphere, carry out rapid thermal annealing then with groove of dry method ICP-RIE method etching, making Ni/Au Schottky contacts gate electrode on recessed grid window afterwards at growth area of grid in advance.The groove gate technique passes through the barrier layer etching certain depth under the grid; Make the attenuation of grid lower barrierlayer, 2DEG concentration reduces under the grid thereby make, and the carrier concentration of source-drain area keeps higher value constant; So both can realize the enhanced characteristic of device, can guarantee certain current density again.Its epitaxial growth of enhancement device that utilizes the groove gate technique to realize is controlled easily, but its control is relatively poor, and etching process can form damage.Referring to document W.B.Lanford, T.Tanaka, Y.Otoki and I.Adesida; " Recessed-gate enhancement-mode GaN HEMT with high threshold voltage ", Electronics Letrers, Vol.41; No.7, March 2005.
5.AlGaN/GaN cutting MIS grid HFET structure, people such as Tohru Oka utilize cutting MIS grid HFET structure to realize the threshold voltage up to 5.2V, and this epitaxial layer structure is from bottom to up: Si substrate, resilient coating, the Al behind the 800nm
0.05Ga
0.95The N resilient coating, the GaN channel layer that 40nm is thick, the Al that 34nm is thick
0.25Ga
0.75N, the AlN barrier layer that 1nm is thick, the GaN cap layer that 1nm is thick.In the device technology manufacture process, the barrier layer warp under the grid window is based on SiCl
4/ Cl
2The whole etchings of inductively coupled plasma ICP after, at 500 ℃ N
2Under the atmosphere through after five minutes the annealing through plasma-reinforced chemical vapor deposition PECVD etching one bed thickness be the SiN of 20nm as gate medium, also be passivation layer simultaneously, and then deposit W Base Metal is as the grid metal.Form the MIS gate device like this,, thereby do not have two-dimensional electron gas because the grid lower area does not have heterogeneous junction structure; Therefore can realize high threshold enhancement mode; But this structure also exists in certain problem, because heterojunction has all been etched away under the grid, causes device mobility low; Current density is lower, and conducting resistance is big.List of references Tohru Oka; To mohiro Nozawa; " AlGaN/GaN Recessed MIS-Gate HFET With High-Threshold-Voltage Normally-Off Operation for Power Electronics Applications ", IEEE Electron Device Lett, VOL.29; NO.7, JULY 2008.
In sum, AlGaN/GaN enhancement mode HEMT device mainly adopts based on the groove gate technique with based on the formation of fluorine ion injection technique in the world at present, and all there is following deficiency in it:
The one, threshold voltage and current density exist this those long relations that disappear, and be difficult to accomplish the coexistence of high threshold voltage and high current density, and the control of threshold voltage are relatively poor;
The 2nd, it still is that the fluorine ion injection all can cause damage to material that etching forms the groove grid; Though annealedly can eliminate certain damage; But residual damage still can impact device performance and reliability, and the repeatability of present this technology is also not high simultaneously;
The 3rd, it is long to adopt high-grade process equipment such as electron-beam direct writing to make short grid when forming the short channel device towards microwave applications, and technology difficulty is bigger.
Summary of the invention
The objective of the invention is to overcome the defective of above-mentioned prior art; From the optimization angle of device vertical structure a kind of MIS of metal-insulator semiconductor (MIS) grid GaN base enhancement type high electron mobility transistor HEMT device and manufacture method are proposed; To reduce technology difficulty, avoid the damage that causes in the device fabrication process, increase the threshold voltage of device; The controllability of enhance device threshold voltage, the reliability of raising device.
For realizing above-mentioned purpose; Device of the present invention comprises: substrate, transition zone, GaN host buffer layer, N type AlGaN master barrier layer, both sides, N type AlGaN master barrier layer top are source electrode, drain electrode, and the centre is a gate electrode, it is characterized by: be etched with groove in the middle of the GaN host buffer layer; The bottom surface of this groove is 0001 polar surface; The groove side is non-0001, and the inwall of this groove extension successively has GaN resilient coating, AlGaN barrier layer and dielectric layer, and gate electrode is deposited on the dielectric layer.
The main two-dimensional electron gas 2DEG of the formation at the interface raceway groove of said GaN host buffer layer and AlGaN master's barrier layer, this raceway groove is positioned at the both sides of groove; GaN resilient coating and AlGaN barrier layer interface of extension forms time two-dimensional electron gas 2DEG raceway groove in the groove.
The horizontal level of said two-dimensional electron gas 2DEG raceway groove is lower than the horizontal level of main two-dimensional electron gas 2DEG raceway groove.
Said main barrier layer mixes for the N type, and doping content is 6 * 10
19Cm
-3
For realizing above-mentioned purpose, the MIS of metal-insulator semiconductor (MIS) grid GaN base enhancement mode HEMT device of the present invention and manufacture method comprise the steps:
(1) in reative cell, substrate surface is carried out preliminary treatment;
(2) epitaxial growth AlGaN/GaN epitaxial loayer on substrate, wherein GaN thickness is 1um～3um, the Al that the N type mixes
xGa
1-xThe N barrier layer thickness is 14nm～30nm, and wherein the molar content x of Al element is 20%-35%;
(3) deposit one deck mask dielectric layer on epitaxial loayer carries out photoetching again, and adopts wet etching method that the dielectric layer on the epitaxial loayer is carried out etching, and shape is grown into the groove of 0.5um on epitaxial loayer;
(4) make grooved area by lithography, and adopt reactive ion etching RIE method that the AlGaN/GaN epitaxial loayer in the grooved area is carried out etching, etching depth is 35nm～140nm;
(5) the mask dielectric layer outside the reservation groove; Epitaxial loayer after the etching is passed through metal organic chemical vapor deposition MOCVD reative cell; Along the 20nm～100nm that grows on the groove floor direction vertically upward thick GaN layer and the thick AlGaN layer of 14nm～30nm, along thick GaN layer and the thick AlGaN layer of 7nm～15nm of groove side surface direction growth 10nm～50nm;
(6) remove the mask dielectric layer;
(7) on the material surface of removing the mask dielectric layer, adopting chemical vapor deposition CVD or physical vapor deposition PVD method deposition thickness is the gate dielectric layer of 20nm～60nm;
(8) on gate dielectric layer, make source, drain region earlier by lithography, etch source, ornamental perforated window mouth again;
(9) on the material surface after the photoetching, adopt the metal of electron beam evaporation technique evaporation ohmic contact, and through after peeling off, annealing, formation source, drain contact electrode;
(10) photoetching gate region on gate medium, and adopt electron beam evaporation technique evaporation gate metal, after peeling off, form the MIS of metal-insulator semiconductor (MIS) grid;
(11) photoetching has formed the device surface of source, leakage, grid, obtains the thickening electrode pattern, and adopts electron beam evaporation technique to add thick electrode, accomplishes element manufacturing.
The present invention has following advantage:
1) has good enhancement mode characteristic and high threshold voltage.
The present invention is owing to AlGaN/GaN heterojunction boundary in the device architecture that adopts is a nonplanar structure; Groove floor is 0001 polar surface; And the groove side is non-0001; Reduce even eliminated polarity effect along non-0001 AlGaN/GaN heterojunction of extension on the groove side surface direction, the two-dimensional electron gas that this heterojunction boundary place is formed is very low, even does not have two-dimensional electron gas; Therefore have only grid is applied sufficiently high positive voltage; Could be on the groove side surface direction induce abundant two-dimensional electron gas in non-0001 heterojunction raceway groove of extension, and apply can in the inferior GaN resilient coating of groove side, form higher horizontal drift electric field than high gate voltage, electronics is conducted electricity via the main 2DEG channel layer of groove both sides, the two-dimensional electron gas raceway groove of groove side and the inferior 2DEG channel layer on the groove floor; Realize the enhancement mode working method of device, and obtained high threshold voltage.
2) threshold voltage has good control.
Device of the present invention is because in the implementation procedure of technology; Can utilize GaN resilient coating of different technological conditions extension different-thickness on the groove side surface direction; And the difference of the electric field strength in this resilient coating that GaN time different buffer layer thicknesses causes has determined the threshold voltage of device to a great extent; Therefore can regulate and control the threshold voltage of device in the design as required through GaN buffer layer thickness of change,, make equating under the grid voltage such as increasing GaN buffer layer thickness; Electric field strength in GaN resilient coating reduces, thereby improves device threshold voltage.
3) has high current density.
Because the AlGaN barrier layer of device groove inwall of the present invention and the AlGaN barrier layer beyond the groove are not to grow simultaneously; AlGaN barrier layer beyond the groove adopts N type even N+ type to mix; Not only can reduce the ohmic contact resistance of device greatly; And can reduce the series resistance of source electrode and drain electrode greatly, therefore improved the current density of device.
4) has good pinch-off behavior.
Device of the present invention is because when grid voltage is zero, and GaN resilient coating of groove side can block electrons flowing in raceway groove, so can realize extremely low off-state current.
5) grid of the present invention can reduce the grid Leakage Current, and can obtain higher grid swing when improve puncture voltage owing to adopt the MIS of metal-insulator semiconductor (MIS) grid.
6) technology is simple, ripe, good reproducibility, and device reliability is high.
Processing step in the device manufacture method of the present invention all is relatively ripe both at home and abroad at present, and technological process is also simple relatively, and cost is low, and the depletion-mode AlGaN/GaN HEMT device preparation technology with ripe is compatible fully.In addition, the present invention has adopted dry etching method to carry out groove grid etching, and in follow-up high temperature secondary growth, the surface damage that can form etching is to a certain extent repaired, to reduce the influence of etching injury to device performance and reliability.Compare with groove grid lithographic method commonly used both at home and abroad at present, the more effective material damage of having avoided etching to cause of the present invention's ability, device reliability is higher.
Description of drawings
Fig. 1 is MIS grid GaN base enhancement mode HEMT device of the present invention and manufacture method;
Fig. 2 is that the present invention prepares MIS grid GaN base enhancement mode HEMT device and manufacture method.
Embodiment
With reference to Fig. 1, MIS grid GaN base enhancement mode HEMT device of the present invention comprises: substrate 1, AlN transition zone 2, GaN host buffer layer 3, N type Al
xGa
1-xN master's barrier layer 4, groove 5, GaN resilient coating 6, Al
xGa
1-xN barrier layer 7, dielectric layer 8, source electrode 9, drain electrode 10 and grid 13; AlN transition zone 2 extensions are on substrate 1; GaN host buffer layer 3 is on the AlN transition zone; N type Al
xGa
1-xN master's barrier layer 4 is on GaN host buffer layer 3, and 0≤x≤1, and doping content is 6 * 10
19Cm
-3The both sides, top of N type AlGaN master barrier layer 4 are source electrode 9, drain electrode 10, and the centre is a grid 13; N type Al
xGa
1-xN master's barrier layer 4 tops are dielectric layer 8, and thickness of dielectric layers is 20nm～60nm; Groove 5 is etched in the centre of GaN host buffer layer 3, and depth of groove is 35nm～140nm, and the groove floor after the etching is a GaN host buffer layer 3, and it is 0001 polar surface, and the groove side is non-0001; GaN time resilient coating 6 is positioned on the groove 5; Al
xGa
1-xN time barrier layer 7 is positioned at resilient coating 6 tops GaN time; Being 20nm～100nm on the direction that the thickness of GaN resilient coating 6 makes progress in groove 5 bottom surfaces, is 10nm～50nm on the horizontal direction of groove 5 sidewalls; Al
xGa
1-xBeing 14nm～30nm on the direction that the thickness of N barrier layer 7 makes progress in groove 5 bottom surfaces, is 7nm～15nm on the horizontal direction of groove 5 sidewalls; Al
xGa
1-xN time barrier layer 7 tops are dielectric layer 8; Gate electrode 13 is on dielectric layer 8; GaN host buffer layer 3 and Al
xGa
1-xThe main two-dimensional electron gas 2DEG of the formation at the interface raceway groove 11 of N master's barrier layer 4, this raceway groove 11 is positioned at the both sides of groove 5; GaN the resilient coating 6 and the Al of extension in the groove
xGa
1-xN time barrier layer 7 interfaces form time two-dimensional electron gas 2DEG raceway groove 12, and the horizontal level of inferior two-dimensional electron gas 2DEG raceway groove 12 is lower than the horizontal level of main two-dimensional electron gas 2DEG raceway groove 11.
With reference to Fig. 2, the present invention makes the method for MIS grid GaN base enhancement mode HEMT device, provides following three kinds of embodiment.
Embodiment 1
The making transition zone is AlN, and GaN host buffer layer thickness is 1um, Al
0.35Ga
0.65N master's barrier layer thickness is 14nm, and the recess etched degree of depth is 35nm, and GaN resilient coating thickness on groove floor makes progress direction is 20nm, thickness is 10nm on the horizontal direction of groove side, Al
0.35Ga
0.65N time barrier layer is 14nm for thickness on groove floor makes progress direction, and thickness is 7nm on the horizontal direction of groove side, and gate dielectric layer thickness is the MIS grid GaN base enhancement mode HEMT device of 20nm, the steps include:
Step 1 places the reative cell of MOCVD equipment to the C surface sapphire substrate, and the vacuum degree of reative cell is evacuated to 1 * 10
-2Under the Torr, down Sapphire Substrate is heat-treated with surfaces nitrided the mixed gas protected of hydrogen and ammonia, heating-up temperature is 1050 ℃, and pressure is 20Torr, and hydrogen flowing quantity is 1500sccm, and ammonia flow is 1500sccm.
Step 2, adopting MOCVD technology epitaxial growth thickness on Sapphire Substrate is the AlN transition zone of 150nm, like Fig. 2 (a).
The process conditions that extension AlN transition zone adopts are: temperature is 980 ℃, and pressure is 20Torr, and hydrogen flowing quantity is 300sccm, and ammonia flow is 1500sccm, and the aluminium source flux is 30sccm.
Step 3, adopting MOCVD technology epitaxial growth thickness on transition zone is the GaN host buffer layer of 1um, like Fig. 2 (b).
The process conditions that extension adopts are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the gallium source flux is 220sccm.
Step 4, adopting MOCVD technology epitaxial thickness on the host buffer layer is the N type doped with Al of 14nm
0.35Ga
0.65N master's barrier layer is through feeding silane SiH in growth course
4Realize that doping content is 6 * 10
19Cm
-3The N type mix, on the AlN transition zone, formed the AlGaN/GaN heterojunction like this, rely on GaN one side at the AlGaN/GaN heterojunction boundary and just formed main two-dimensional electron gas 2DEG, the epitaxial slice structure of formation such as Fig. 2 (c).
The process conditions that extension adopts are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 10sccm, and the gallium source flux is 40sccm.
Step 5 after above-mentioned epitaxial wafer cleaned, utilizes plasma-reinforced chemical vapor deposition PECVD technology at surface deposition layer of sin mask dielectric layer, like Fig. 2 (d).
Step 6, in deposit on the epitaxial wafer surface of mask dielectric layer, at first carry out positive-glue removing, soft baking; Through the exposure and the required notch window of formation etching of developing, adopt wet etching method to carve at last and remove the SiN mask dielectric layer under the notch window, and remove remaining photoresist on the SiN mask dielectric layer again with acetone.
Step 7 makes notch window by lithography to the epitaxial wafer after removing photoresist, and adopts the AlGaN/GaN heterojunction under the reactive ion etching RIE equipment etched recesses window, and forming the bottom surface is 0001 polar surface, and the side is non-0001 groove structure, like Fig. 2 (e).
It is the chlorine Cl of 15sccm that etching adopts flow
2, power is 200W, and pressure is 10mT, and etching depth is 35nm.
Step 8 is removed the positive glue after the etching with acetone, and the epitaxial wafer surface is cleaned.
Step 9 is evacuated to 1 * 10 with the vacuum degree of reative cell
-2Under the Torr, down the epitaxial wafer after cleaning is heat-treated the mixed gas protected of hydrogen and ammonia, heating-up temperature is 1000 ℃, and pressure is 20Torr, and hydrogen flowing quantity is 1500sccm, and ammonia flow is 1500sccm.
Step 10; Repeating step three, at GaN resilient coating of groove inwall diauxic growth different-thickness, promptly Grown GaN time buffer layer thickness is 20nm on the groove floor vertical direction; Grown GaN time buffer layer thickness is 10nm on the horizontal direction of groove side, like Fig. 2 (f).
Step 11 adopts the Al of MOCVD technology diauxic growth different-thickness on GaN resilient coating
0.35Ga
0.65N barrier layer, the Al that promptly on the groove floor vertical direction, grows
0.35Ga
0.65N barrier layer thickness is 14nm, the Al that on the horizontal direction of groove side, grows
0.35Ga
0.65N barrier layer thickness is 7nm; Rely on GaN one side at the interface of inferior AlGaN barrier layer and time GaN resilient coating like this and just formed inferior two-dimensional electron gas 2DEG; And the horizontal level that has guaranteed inferior two-dimensional electron gas 2DEG is lower than the horizontal level of main two-dimensional electron gas 2DEG, like Fig. 2 (g).
The process conditions of growth are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 10sccm, and the gallium source flux is 40sccm.
Step 12 is at diauxic growth Al
0.35Ga
0.65On the epitaxial wafer behind N barrier layer, utilize the SiN dielectric layer of plasma-reinforced chemical vapor deposition PECVD method deposition thickness for 20nm, this dielectric layer covers time barrier layer and groove inwall, like Fig. 2 (h).
The process conditions of this dielectric layer of deposit are: ammonia flow is 2.5sccm, and nitrogen flow is 900sccm, and silane flow rate is 200sccm, and temperature is 300 ℃, and pressure is 900mT, and power is 25W.
Step 13, the SiN dielectric film of removal source and drain areas
At first, positive-glue removing, soft baking on the SiN dielectric layer;
Then, through exposure and development formation source, drain region;
At last, adopt wet etching method to remove the SiN dielectric film of source and drain areas.
Step 14 is carried out positive-glue removing, soft baking to the epitaxial wafer of the SiN dielectric layer of having removed source, drain region, and through exposure and development acquisition source ornamental perforated window mouth.
Step 15 utilizes plasma degumming machine to remove the photoresist thin layer that source, ornamental perforated window mouth are not developed clean, can improve the rate of finished products of metal-stripping.
Step 10 six adopts four layers of metal ohmic contact of electron beam evaporation instrument deposit Ti/Al/Ni/Au, and wherein the thickness of Ti is 30nm, and the thickness of Al is 180nm, and the thickness of Ni is 40nm, and the thickness of Au is 60nm.
The process conditions of deposit are: vacuum degree is less than 2.0 * 10
-6Pa, power are 200W, and evaporation rate was not more than for 3 dust/seconds.
Step 10 seven is soaked 20min with the epitaxial wafer behind the evaporated metal in acetone soln, carry out ultrasonic cleaning then, and dries up with ultra-pure water flushing and nitrogen, and this step is fallen the metal-stripping beyond source, the ornamental perforated window mouth.
Step 10 eight is carried out the ohmic contact annealing of 30s with the epitaxial wafer behind the stripping metal in temperature is 850 ℃ nitrogen atmosphere, formation source, drain contact electrode are like Fig. 2 (i).
Step 10 nine is carried out positive-glue removing, soft baking on the epitaxial wafer that forms source, drain contact electrode, through the exposure and the acquisition grid window that develops.
Step 2 ten adopts electron beam evaporation instrument deposit Ni/Au double layer of metal to the epitaxial wafer that makes the grid window by lithography, and the thickness of Ni is 30nm, and the thickness of Au is 200nm; Subsequently epitaxial wafer is immersed in and carries out metal-stripping in the stripper, wash 2min with ultra-pure water, and dry up, finally obtain gate electrode, like Fig. 2 (j) with nitrogen.
Step 2 11, photoetching have formed the epitaxial wafer of source, leakage, grid structure, obtain the thickening electrode pattern, adopt electron beam evaporation technique to add thick electrode, accomplish element manufacturing as shown in Figure 1.
Embodiment 2
The making transition zone is AlN, and GaN host buffer layer thickness is 2um, Al
0.27Ga
0.73N master's barrier layer thickness is 24nm, and the recess etched degree of depth is 80nm, and GaN resilient coating thickness on groove floor makes progress direction is 50nm, thickness is 25nm on the horizontal direction of groove side, Al
0.27Ga
0.73N time barrier layer is 24nm for thickness on groove floor makes progress direction, and thickness is 12nm on the horizontal direction of groove side, and gate dielectric layer thickness is the MIS grid GaN base enhancement mode HEMT device of 40nm, the steps include:
Step 1 is identical with the step 1 of embodiment 1.
Step 2 is identical with the step 2 of embodiment 1.
Step 3, adopting MOCVD technology epitaxial growth thickness on transition zone is the GaN host buffer layer of 2um, like Fig. 2 (b).
The process conditions that extension adopts are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the gallium source flux is 220sccm.
Step 4, adopting MOCVD technology epitaxial thickness on the host buffer layer is the N type doped with Al of 24nm
0.27Ga
0.73N master's barrier layer is through feeding silane SiH in growth course
4Realize that doping content is 6 * 10
19Cm
-3The N type mix, on the AlN transition zone, formed the AlGaN/GaN heterojunction like this, rely on GaN one side at the AlGaN/GaN heterojunction boundary and just formed main two-dimensional electron gas 2DEG, the epitaxial slice structure of formation such as Fig. 2 (c).
The process conditions that extension adopts are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 10sccm, and the gallium source flux is 40sccm.
Step 5 is identical with the step 5 of embodiment 1.
Step 6 is identical with the step 6 of embodiment 1.
Step 7 makes notch window by lithography to the epitaxial wafer after removing photoresist, and adopts the AlGaN/GaN heterojunction under the reactive ion etching RIE equipment etched recesses window, and forming the bottom surface is 0001 polar surface, and the side is non-0001 groove structure, like Fig. 2 (e).
It is the chlorine Cl of 15sccm that etching adopts flow
2, power is 200W, and pressure is 10mT, and etching depth is 80nm.
Step 8 is identical with the step 8 of embodiment 1.
Step 9 is identical with the step 9 of embodiment 1.
Step 10; Repeating step three, at GaN resilient coating of groove inwall diauxic growth different-thickness, promptly Grown GaN time buffer layer thickness is 50nm on the groove floor vertical direction; Grown GaN time buffer layer thickness is 25nm on the horizontal direction of groove side, like Fig. 2 (f).
Step 11 adopts the Al of MOCVD technology diauxic growth different-thickness on GaN resilient coating
0.27Ga
0.73N barrier layer, the Al that promptly on the groove floor vertical direction, grows
0.27Ga
0.73N barrier layer thickness is 24nm, the Al that on the horizontal direction of groove side, grows
0.27Ga
0.73N barrier layer thickness is 12nm; Rely on GaN one side at the interface of inferior AlGaN barrier layer and time GaN resilient coating like this and just formed inferior two-dimensional electron gas 2DEG; And the horizontal level that has guaranteed inferior two-dimensional electron gas 2DEG is lower than the horizontal level of main two-dimensional electron gas 2DEG, like Fig. 2 (g).
The process conditions of growth are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 10sccm, and the gallium source flux is 40sccm.
Step 12 is at diauxic growth Al
0.27Ga
0.73On the epitaxial wafer behind N barrier layer, utilize the SiN dielectric layer of plasma-reinforced chemical vapor deposition PECVD method deposition thickness for 40nm, this dielectric layer covers time barrier layer and groove inwall, like Fig. 2 (h).
The process conditions of this dielectric layer of deposit are: ammonia flow is 2.5sccm, and nitrogen flow is 900sccm, and silane flow rate is 200sccm, and temperature is 300 ℃, and pressure is 900mT, and power is 25W.
Step 13 is identical with the step 13 of embodiment 1.
Step 14 is identical with the step 14 of embodiment 1.
Step 15 is identical with the step 15 of embodiment 1.
Step 16, same with the step 10 six phase of embodiment 1.
Step 17 is identical with the step 10 seven of embodiment 1.
Step 18 is identical with the step 10 eight of embodiment 1.
Step 19 is identical with the step 10 nine of embodiment 1.
Step 20 is identical with the step 2 ten of embodiment 1.
Step 21 is identical with the step 2 11 of embodiment 1.
Embodiment 3
The making transition zone is AlN, and GaN host buffer layer thickness is 3um, Al
0.2Ga
0.8N master's barrier layer thickness is 30nm, and the recess etched degree of depth is 140nm, and GaN resilient coating thickness on groove floor makes progress direction is 100nm, thickness is 50nm on the horizontal direction of groove side, Al
0.2Ga
0.8N time barrier layer is 30nm for thickness on groove floor makes progress direction, and thickness is 15nm on the horizontal direction of groove side, and gate dielectric layer thickness is the MIS grid GaN base enhancement mode HEMT device of 60nm, the steps include:
Steps A is identical with the step 1 of embodiment 1.
Step B is identical with the step 2 of embodiment 1.
Step C, adopting MOCVD technology epitaxial growth thickness on transition zone is the GaN host buffer layer of 3um, like Fig. 2 (b).
The process conditions that extension adopts are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the gallium source flux is 220sccm.
Step D, adopting MOCVD technology epitaxial thickness on the host buffer layer is the N type doped with Al of 30nm
0.2Ga
0.8N master's barrier layer is through feeding silane SiH in growth course
4Realize that doping content is 6 * 10
19Cm
-3The N type mix, on the AlN transition zone, formed the AlGaN/GaN heterojunction like this, rely on GaN one side at the AlGaN/GaN heterojunction boundary and just formed main two-dimensional electron gas 2DEG, the epitaxial slice structure of formation such as Fig. 2 (c).
The process conditions that extension adopts are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 10sccm, and the gallium source flux is 40sccm.
Step e is identical with the step 5 of embodiment 1.
Step F is identical with the step 6 of embodiment 1.
Step G makes notch window by lithography to the epitaxial wafer after removing photoresist, and adopts the AlGaN/GaN heterojunction under the reactive ion etching RIE equipment etched recesses window, and forming the bottom surface is 0001 polar surface, and the side is non-0001 groove structure, like Fig. 2 (e).
It is the chlorine Cl of 15sccm that etching adopts flow
2, power is 200W, and pressure is 10mT, and etching depth is 140nm.
Step H is identical with the step 8 of embodiment 1.
Step I is identical with the step 9 of embodiment 1.
Step J; Repeating step three, at GaN resilient coating of groove inwall diauxic growth different-thickness, promptly Grown GaN time buffer layer thickness is 100nm on the groove floor vertical direction; Grown GaN time buffer layer thickness is 50nm on the horizontal direction of groove side, like Fig. 2 (f).
Step K adopts the Al of MOCVD technology diauxic growth different-thickness on GaN resilient coating
0.35Ga
0.65N barrier layer, the Al that promptly on the groove floor vertical direction, grows
0.2Ga
0.8N barrier layer thickness is 30nm, the Al that on the horizontal direction of groove side, grows
0.2Ga
0.8N barrier layer thickness is 15nm; Rely on GaN one side at the interface of inferior AlGaN barrier layer and time GaN resilient coating like this and just formed inferior two-dimensional electron gas 2DEG; And the horizontal level that has guaranteed inferior two-dimensional electron gas 2DEG is lower than the horizontal level of main two-dimensional electron gas 2DEG, like Fig. 2 (g).
The process conditions of growth are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 10sccm, and the gallium source flux is 40sccm.
Step L is at diauxic growth Al
0.2Ga
0.8On the epitaxial wafer behind N barrier layer, utilize the SiN dielectric layer of plasma-reinforced chemical vapor deposition PECVD method deposition thickness for 60nm, this dielectric layer covers time barrier layer and groove inwall, like Fig. 2 (h).
The process conditions of this dielectric layer of deposit are: ammonia flow is 2.5sccm, and nitrogen flow is 900sccm, and silane flow rate is 200sccm, and temperature is 300 ℃, and pressure is 900mT, and power is 25W.
Step M is identical with the step 12 of embodiment 1.
Step N is identical with the step 13 of embodiment 1.
Step O is identical with the step 14 of embodiment 1.
Step P is identical with the step 15 of embodiment 1.
Step Q, same with the step 10 six phase of embodiment 1.
Step R is identical with the step 10 seven of embodiment 1.
Step S is identical with the step 10 eight of embodiment 1.
Step T is identical with the step 10 nine of embodiment 1.
Step U is identical with the step 2 ten of embodiment 1.
Step v is identical with the step 2 11 of embodiment 1.
The foregoing description several preferred embodiments only of the present invention; Do not constitute any restriction of the present invention; Obviously to those skilled in the art, after having understood content of the present invention and principle, can be under the situation that does not deviate from the principle and scope of the present invention; Carry out various corrections and change on form and the details according to the method for the invention, but these are based on correction of the present invention with change still within claim protection range of the present invention.
Claims (5)
1. the MIS of metal-insulator semiconductor (MIS) grid GaN base enhancement type high electron mobility transistor HEMT device; Comprise: substrate (1), transition zone (2), GaN host buffer layer (3), N type AlGaN master barrier layer (4), N type AlGaN master barrier layer (4) both sides, top are source electrode (9) and drain electrode (10); The centre is gate electrode (13); It is characterized in that be etched with groove (5) in the middle of the GaN host buffer layer (3), the bottom surface of this groove is 0001 polar surface; The groove side is non-0001, and the inwall of this groove extension successively has GaN resilient coating (6), AlGaN barrier layer (7) and dielectric layer (8); Gate electrode (13) is deposited on the dielectric layer (8).
2. device according to claim 1 is characterized in that, the main two-dimensional electron gas 2DEG of the formation at the interface raceway groove (11) of GaN host buffer layer (3) and AlGaN master's barrier layer (4), and this raceway groove (11) is positioned at the both sides of groove (5); GaN the resilient coating (6) of extension forms time two-dimensional electron gas 2DEG raceway groove (12) with AlGaN barrier layer (7) interface in the groove.
3. device according to claim 1 is characterized in that, the horizontal level of inferior two-dimensional electron gas 2DEG raceway groove (12) is lower than the horizontal level of main two-dimensional electron gas 2DEG raceway groove (11).
4. device according to claim 1 is characterized in that, main barrier layer (4) mixes for the N type, and doping content is 6 * 10
19Cm
-3
5. the manufacture method of the MIS of metal-insulator semiconductor (MIS) grid GaN base enhancement type high electron mobility transistor HEMT device may further comprise the steps:
(1) in reative cell, substrate surface is carried out preliminary treatment;
(2) epitaxial growth AlGaN/GaN epitaxial loayer on substrate, wherein GaN thickness is 1um～3um, the Al that the N type mixes
xGa
1-xThe N barrier layer thickness is 14nm～30nm, and wherein the molar content x of Al element is 20%-35%;
(3) deposit one deck mask dielectric layer on epitaxial loayer carries out photoetching again, and adopts wet etching method that the dielectric layer on the epitaxial loayer is carried out etching, and shape is grown into the groove of 0.5um on epitaxial loayer;
(4) make grooved area by lithography, and adopt reactive ion etching RIE method that the AlGaN/GaN epitaxial loayer in the grooved area is carried out etching, etching depth is 35nm～140nm;
(5) the mask dielectric layer outside the reservation groove; Epitaxial loayer after the etching is passed through metal organic chemical vapor deposition MOCVD reative cell; Along the 20nm～100nm that grows on the groove floor direction vertically upward thick GaN layer and the thick AlGaN layer of 14nm～30nm, along thick GaN layer and the thick AlGaN layer of 7nm～15nm of groove side surface direction growth 10nm～50nm;
(6) remove the mask dielectric layer;
(7) on the material surface of removing the mask dielectric layer, adopting chemical vapor deposition CVD or physical vapor deposition PVD method deposition thickness is the gate dielectric layer of 20nm～60nm;
(8) on gate dielectric layer, make source, drain region earlier by lithography, etch source, ornamental perforated window mouth again;
(9) on the material surface after the photoetching, adopt the metal of electron beam evaporation technique evaporation ohmic contact, and through after peeling off, annealing, formation source, drain contact electrode;
(10) photoetching gate region on gate medium, and adopt electron beam evaporation technique evaporation gate metal, after peeling off, form the MIS of metal-insulator semiconductor (MIS) grid;
(11) photoetching has formed the device surface of source, leakage, grid, obtains the thickening electrode pattern, and adopts electron beam evaporation technique to add thick electrode, accomplishes element manufacturing.
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