CN111463260A - Vertical high electron mobility field effect transistor and preparation method thereof - Google Patents
Vertical high electron mobility field effect transistor and preparation method thereof Download PDFInfo
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7788—Vertical transistors
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Abstract
The invention discloses a vertical high-electron-mobility field effect transistor and a preparation method thereof. The invention provides a vertical high electron mobility field effect transistor, which comprises: a substrate; a current blocking layer disposed on one side of the substrate, the current blocking layer having a conductive via therein; the channel layer is arranged on one side, far away from the substrate, of the current blocking layer; the barrier layer is arranged on one side, away from the current blocking layer, of the channel layer, first two-dimensional electron gas is formed at the contact interface of the barrier layer and the channel layer, the first two-dimensional electron gas is formed on one side of the channel layer, a groove is formed in the barrier layer, and the distance between the bottom of the groove and the channel layer is not more than 5 nm; the passivation layer is arranged on one side of the barrier layer away from the channel layer; and a semiconductor layer disposed in the recess, a second two-dimensional electron gas being formed at an interface of the semiconductor layer and the channel layer, the second two-dimensional electron gas being formed at one side of the semiconductor layer. Thus, normally-off characteristics of the vertical high electron mobility field effect transistor can be easily realized.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a vertical high-electron-mobility field effect transistor and a preparation method thereof.
Background
With the improvement of the technological level, the third generation semiconductor material represented by gallium nitride (GaN) is widely used for preparing high-frequency, high-temperature and high-power electronic devices due to its advantages of large forbidden band width, high critical breakdown field strength, high electron saturation drift rate, high thermal conductivity and the like, and is also used in high-tech fields such as mobile communication, radar base stations, aerospace and the like. For example, gallium nitride (GaN) -based High Electron Mobility Transistor (HEMT) devices have characteristics of high reverse blocking voltage, low forward on-resistance, high operating frequency and the like due to the AlGaN/GaN heterojunction forming a two-dimensional electron gas with a high concentration at the heterojunction interface, and thus have wide application in high current, low power consumption and high voltage switching devices. For AlGaN/GaN devices, High Electron Mobility Transistor (HEMT) devices having enhancement (normally-off) characteristics have a wider range of applications than those having depletion (normally-on) characteristics.
However, the vertical high electron mobility field effect transistor and the method for fabricating the same still need to be improved.
Disclosure of Invention
The present invention is based on the discovery and recognition by the inventors of the following facts and problems:
the existing gallium nitride (GaN) -based High Electron Mobility Transistor (HEMT) device is mainly a lateral device, electrons injected from a source electrode can reach a drain electrode through a gallium nitride (GaN) buffer layer in an off state to form a leakage channel, and an excessive buffer layer leakage current can cause the device to break down in advance, so that the advantage of high withstand voltage of gallium nitride (GaN) materials cannot be fully exerted, thereby limiting the application of the gallium nitride (GaN) -based High Electron Mobility Transistor (HEMT) device in the aspect of high voltage. Compared to lateral gallium nitride (GaN) -based high electron mobility field effect transistor (HEMT) devices, vertical gallium nitride (GaN) -based high electron mobility field effect transistor (HEMT) devices have the following advantages: the withstand voltage of the device is not limited by the transverse size any more, the device mainly bears the withstand voltage through the longitudinal distance between the grid and the drain, the transverse size of the device can be designed to be very small, and the area of a chip can be saved; meanwhile, a p-n junction formed between the p-type GaN current blocking layer and the n-type GaN buffer layer can effectively block electrons injected from the source electrode, so that leakage current of the buffer layer of the device is inhibited. In addition, in a gallium nitride (GaN) -based high electron mobility field effect transistor (HEMT) device, although high carrier concentration and electron mobility help to provide very low series resistance, the HEMT device also has the characteristic of a normally-on device, and a negative pressure source needs to be introduced in practical circuit application to turn off the device, so that the HEMT device has potential safety hazards and increases the complexity and cost of the circuit.
For a lateral device, the technical means of a high electron mobility field effect transistor (HEMT) that can achieve enhancement (normally-off) characteristics at present mainly include: (1) a p-GaN gate structure; (2) fluorine ion implantation technology; (3) etching technology of grid grooves; (4) a cascade mode. However: in the technical means (1), a p-type GaN layer is inserted between an AlGaN/GaN heterojunction material and a grid, and an energy band of an AlGaN barrier layer is pulled high through the p-type GaN layer, so that two-dimensional electron gas (2DEG) is exhausted, and an enhanced high electron mobility field effect transistor (HEMT) is realized, but the p-type doped GaN is limited by the current manufacturing process, so that the activation rate of p-type doping in GaN is low, the two-dimensional electron gas (2DEG) in a channel cannot be completely exhausted, and the threshold voltage of a device is not high enough; in the technical means (2), CF is used4The plasma is used for processing the AlGaN barrier layer below the grid, F entering the AlGaN barrier layer can trap electrons to form electronegative F ions, depletion effect is generated on two-dimensional electron gas (2DEG) in a channel, and the enhanced high electron mobility field effect transistor (HEMT) is realized, however, F ions are injected into the AlGaN barrier layer, on one hand, material damage can be caused to the AlGaN barrier layer, on the other hand, the distribution of the F ions is difficult to control due to the thin barrier layer, and the electron concentration and the mobility in the channel can be reduced due to the fact that the thin barrier layer is close to the two-dimensional electron gas (2DEG) in the channel; in technical means (3), use is made ofThe groove gate structure realizes an enhanced high electron mobility field effect transistor (HEMT), groove etching can effectively exhaust two-dimensional electron gas (2DEG) in a region below a gate, threshold voltage is improved, but the groove etching needs to accurately control etching depth and reduce etching damage caused by plasma treatment, and the process requirement is strict; in the technical means (4), an enhanced high electron mobility field effect transistor (HEMT) can be prepared by adopting a cascade structure. However, the topology structure of the enhancement mode high electron mobility field effect transistor (HEMT) implemented by using the cascade structure is complex, three devices are required, and limited by the current technology, the three devices cannot be integrated on a chip on a process level, so that the three devices need to be interconnected by a substrate and a metal wire, the product cost is increased, and additional internal parasitic parameters are introduced. Likewise, for vertical devices, these aforementioned drawbacks are also present.
Therefore, if a new vertical high electron mobility field effect transistor and a manufacturing method thereof can be provided, the conductive channel of the 2DEG can be simply and completely blocked, the barrier layer and the like cannot be damaged, the operation is simple and convenient, the production cost is low, the breakdown voltage is high, and the voltage withstanding performance is good, so that the problems can be solved to a great extent.
In one aspect, the present invention provides a vertical high electron mobility field effect transistor. According to an embodiment of the present invention, the vertical type high electron mobility field effect transistor includes: a substrate; a current blocking layer disposed on one side of the substrate, the current blocking layer having a conductive via therein; the channel layer is arranged on one side, far away from the substrate, of the current blocking layer; a barrier layer disposed on a side of the channel layer away from the current blocking layer, a first two-dimensional electron gas being formed at an interface where the barrier layer and the channel layer are in contact, the first two-dimensional electron gas being formed on the side of the channel layer, the barrier layer having a groove therein, a distance between a bottom of the groove and the channel layer being not more than 5 nm; the passivation layer is arranged on one side, far away from the channel layer, of the barrier layer, covers the side wall, facing the inside of the groove, of the barrier layer, and does not cover the bottom of the groove; a semiconductor layer disposed in the groove, a second two-dimensional electron gas formed at an interface of the semiconductor layer and the channel layer, the second two-dimensional electron gas being formed at one side of the semiconductor layer. Therefore, in the vertical high electron mobility field effect transistor, the first two-dimensional electron gas can be blocked by the passivation layer and the second two-dimensional electron gas through the conductive channel formed by the conductive through hole, and the normally-off characteristic can be realized more simply and conveniently, the vertical high electron mobility field effect transistor has better service performance, higher breakdown voltage, better voltage resistance and higher reliability and stability, and the vertical high electron mobility field effect transistor also has at least one of the following advantages: (1) the channel layer of the two-dimensional electron gas can be completely blocked without using a doping activation process, and the threshold voltage of the device is favorably improved; (2) the requirement on the precision of the etched groove is low, so that the process difficulty can be reduced; (3) two-dimensional electron gas in the conducting channel can be exhausted without utilizing an ion implantation process, the shutoff is realized, and the damage to the barrier layer caused by ion implantation can be avoided; (4) the normally-off characteristic of the device can be realized on a single chip without adopting a cascade mode, the cost can be reduced, and the introduction of additional parasitic parameters and the like can be avoided.
According to the embodiment of the invention, the forbidden bandwidth of the barrier layer is larger than that of the channel layer, and the forbidden bandwidth of the semiconductor layer is smaller than that of the channel layer. Therefore, a heterojunction structure can be formed between the barrier layer and the channel layer, a first two-dimensional electron gas can be generated at the heterojunction interface, the first two-dimensional electron gas can be formed on one side close to the channel layer, the heterojunction structure can be formed between the semiconductor layer and the channel layer, a second two-dimensional electron gas can be generated at the heterojunction interface, the second two-dimensional electron gas can be formed on one side close to the semiconductor layer, the normally-off characteristic of the vertical high-electron-mobility field effect transistor device can be well realized, the reliability and the stability of the vertical high-electron-mobility field effect transistor device are high, and the use performance is good.
According to an embodiment of the present invention, a material forming the barrier layer includes AlmGa(1-m)And the N crystal, wherein m is more than or equal to 0.15 and less than or equal to 0.80, and the thickness of the barrier layer is not less than 30 nm. Therefore, a heterojunction structure can be formed between the barrier layer formed by the materials and the channel layer, the first two-dimensional electron gas with higher concentration can be generated at the heterojunction interface, and the barrier layer has better performance when the thickness is in the range, so that the service performance of the vertical high-electron-mobility field effect transistor device can be further improved.
According to an embodiment of the present invention, a material forming the semiconductor layer includes InnGa(1-n)And N is more than 0 and less than or equal to 0.45, and the thickness of the semiconductor layer is not less than 30 nm. Therefore, a heterojunction structure can be formed between the semiconductor layer formed by the material and the channel layer, second two-dimensional electron gas with higher concentration can be generated at a heterojunction interface, and the service performance of the vertical high-electron-mobility field effect transistor device can be further improved. In addition, when the thickness of the semiconductor layer is within the above range, the semiconductor layer can have a good performance, and the use performance of the vertical high electron mobility field effect transistor device can be further improved.
According to the embodiment of the invention, the thickness of the current blocking layer is h, and h is more than or equal to 10nm and less than 1000 nm. Therefore, when the thickness of the current blocking layer is within the above range, the current leakage of the vertical high electron mobility field effect transistor can be suppressed well, and the usability of the vertical high electron mobility field effect transistor can be further improved.
According to an embodiment of the present invention, the vertical-type high electron mobility field effect transistor further includes: a nucleation layer disposed on one side of the substrate; a buffer layer disposed on a side of the nucleation layer remote from the substrate, the current blocking layer being formed in the buffer layer; the diffusion preventing layer is arranged on one side of the buffer layer far away from the nucleating layer; the channel layer is arranged on one side, far away from the buffer layer, of the diffusion-proof layer; the grid electrode is arranged on one side, away from the channel layer, of the semiconductor layer, the orthographic projection of the groove on the substrate is not larger than that of the grid electrode on the substrate, and the orthographic projection of the grid electrode on the substrate is not smaller than that of the conductive through hole on the substrate; the source electrode is arranged on one side, far away from the channel layer, of the barrier layer, and the source electrode is in contact with the barrier layer; a drain disposed on a side of the substrate away from the nucleation layer. Therefore, the nucleating layer can enable the substrate material to be matched with the buffer layer, the buffer layer can inhibit the current leakage of the vertical high electron mobility field effect transistor device, the diffusion-proof layer can better prevent ions in the current blocking layer from diffusing into the channel layer in the subsequent process so as to reduce the mobility of two-dimensional electron gas of the channel layer, the service performance of the vertical high electron mobility field effect transistor device can be improved, the grid electrode can form better Schottky contact with the semiconductor layer, the source electrode can directly contact with the barrier layer to form better ohmic contact, the drain electrode is manufactured below the substrate, the whole surface of the device can be in a low electric field state, the concentration of an electric field at the edge of the grid electrode can be effectively avoided, the voltage resistance of the device is not limited by the transverse size, and the device bears the voltage resistance mainly through the longitudinal distance between the grid electrode and the drain electrode, the transverse size of the device can be designed to be smaller, the area of a chip can be effectively saved, and the service performance of the vertical high-electron-mobility field effect transistor device can be further improved.
According to the embodiment of the invention, the material forming the substrate comprises one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium and silicon; the material forming the buffer layer comprises one or more of n-type gallium nitride crystals and unintentionally doped gallium nitride crystals; the material for forming the diffusion preventing layer comprises aluminum nitride; the material for forming the current blocking layer comprises p-type gallium nitride; the material forming the channel layer comprises unintentionally doped gallium nitride crystals; the material for forming the passivation layer comprises one or more of silicon dioxide and silicon nitride; the material for forming the source electrode and the drain electrode comprises one or more of titanium, aluminum, nickel, gold and tantalum; the material for forming the grid electrode comprises one or more of nickel, gold, palladium and platinum. Therefore, the service performance of the vertical high electron mobility field effect transistor device can be further improved.
In another aspect of the invention, the invention provides a method of manufacturing a vertical high electron mobility field effect transistor as described in any one of the preceding claims. According to an embodiment of the invention, the method comprises: providing a substrate; forming a current blocking layer on one side of the substrate, wherein the current blocking layer is provided with a conductive through hole; forming a channel layer on one side of the current blocking layer far away from the substrate; forming a barrier layer on one side of the channel layer far away from the current blocking layer, wherein a first two-dimensional electron gas is formed at an interface where the barrier layer and the channel layer are in contact, the first two-dimensional electron gas is formed on one side of the channel layer, a groove is formed in the barrier layer, and the distance between the bottom of the groove and the channel layer is not more than 5 nm; forming a passivation layer on one side of the barrier layer away from the channel layer, wherein the passivation layer covers the side wall of the barrier layer facing the inner part of the groove, and the passivation layer does not cover the bottom of the groove; and forming a semiconductor layer in the groove, wherein a second two-dimensional electron gas is formed at the interface of the semiconductor layer and the channel layer, and the second two-dimensional electron gas is formed on one side of the semiconductor layer. Therefore, in the method, the conducting channel formed by the first two-dimensional electron gas passing through the conducting through hole can be blocked by the passivation layer and the second two-dimensional electron gas, the vertical high electron mobility field effect transistor with normally-off characteristics can be simply and conveniently prepared, the vertical high electron mobility field effect transistor prepared by the method has the advantages of good use performance, high breakdown voltage, good voltage resistance, high reliability and stability, and the vertical high electron mobility field effect transistor prepared by the method also has at least one of the following advantages: (1) the channel layer of the two-dimensional electron gas can be completely blocked without using a doping activation process, and the threshold voltage of the device is favorably improved; (2) the requirement on the precision of the etched groove is low, so that the process difficulty can be reduced; (3) two-dimensional electron gas in the conducting channel can be exhausted without utilizing an ion implantation process, the shutoff is realized, and the damage to the barrier layer caused by ion implantation can be avoided; (4) the normally-off characteristic of the device can be realized on a single chip without adopting a cascade mode, the cost can be reduced, and the introduction of additional parasitic parameters and the like can be avoided.
According to an embodiment of the invention, forming the barrier layer further comprises: growing Al on the side of the channel layer far away from the current barrier layermGa(1-m)An N crystal material, wherein m is 0.15-0.80, so as to form a barrier layer preform; arranging a first mask on the partial surface of one side of the barrier layer prefabricated body far away from the channel layer; performing a first dry etching process on the barrier layer preform uncovered by the first mask so as to form the groove, wherein a difference between an etching depth of the first dry etching process and a thickness of the barrier layer preform is not more than 5 nm; and removing the first mask to form the barrier layer. Therefore, the barrier layer can be formed more simply and conveniently, and the vertical high-electron-mobility field effect transistor device with better performance can be prepared.
According to an embodiment of the present invention, forming the passivation layer further comprises: depositing a passivation layer material on a side of the barrier layer remote from the channel layer to form a passivation layer preform; arranging a second mask on the surface of the passivation layer prefabricated body, wherein the second mask covers the region except the bottom of the groove; performing a second dry etching treatment on the passivation layer prefabricated body which is not covered by the second mask so as to form the passivation layer, wherein the passivation layer covers the surface of the barrier layer on the side far away from the channel layer and covers the side wall of the barrier layer facing the inside of the groove; and removing the second mask. Therefore, the passivation layer can be generated more conveniently, and the service performance of the prepared vertical high-electron-mobility field effect transistor device can be further improved.
According to an embodiment of the present invention, before forming the current blocking layer, the method further includes: forming a buffer layer on one side of the substrate, and forming a material package of the buffer layerComprises the following steps: one or more of an n-type gallium nitride crystal, an unintentionally doped gallium nitride crystal; forming the current blocking layer further comprises: implanting Mg into partial surface of the buffer layer far away from the substrate by ion implantation process2+、Al3+And forming a current blocking layer on the side of the buffer layer far away from the substrate through an annealing process, wherein the current blocking layer is provided with a conductive through hole which is not implanted with ions, and the material for forming the current blocking layer comprises p-type gallium nitride. Therefore, the current blocking layer can be formed in the buffer layer more conveniently, and the service performance of the vertical high electron mobility field effect transistor device is further improved.
According to an embodiment of the present invention, before forming the current blocking layer, the method further includes: forming a buffer layer on one side of the substrate, the buffer layer being formed of a material including: one or more of an n-type gallium nitride crystal, an unintentionally doped gallium nitride crystal; forming the current blocking layer further comprises: and growing a p-type gallium nitride layer in situ on one side of the buffer layer, which is far away from the substrate, and forming the conductive through hole in the p-type gallium nitride layer through dry etching treatment to form the current blocking layer. Therefore, the current blocking layer can be formed on one side of the buffer layer more conveniently, and the service performance of the vertical high-electron-mobility field effect transistor device is further improved.
According to an embodiment of the present invention, before forming the current blocking layer, the method further includes: forming a buffer layer on one side of the substrate, the buffer layer being formed of a material including: one or more of an n-type gallium nitride crystal, an unintentionally doped gallium nitride crystal; performing dry etching treatment on a partial region of the buffer layer so as to form a first depressed part and a second depressed part after etching and the conductive through hole which is not etched, wherein the conductive through hole is positioned between the first depressed part and the second depressed part; epitaxially growing a p-type gallium nitride layer twice in the first and second recesses so as to form the current blocking layer having the conductive via. Therefore, the current blocking layer can be formed in the buffer layer more conveniently, and the service performance of the vertical high electron mobility field effect transistor device is further improved.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic view showing a structure of a vertical type hemt according to an embodiment of the present invention;
fig. 2 is a schematic view showing a structure of a vertical type hemt according to another embodiment of the present invention;
fig. 3 shows a flow chart of a method of fabricating a vertical hemt according to one embodiment of the present invention;
fig. 4 shows a flow chart of a method of fabricating a vertical hemt according to another embodiment of the present invention;
fig. 5 shows a flow chart of a method of fabricating a vertical high electron mobility field effect transistor according to yet another embodiment of the present invention;
fig. 6 shows a flow chart of a method of fabricating a vertical high electron mobility field effect transistor according to yet another embodiment of the present invention;
fig. 7 shows a flowchart of a method of fabricating a vertical hemt according to yet another embodiment of the present invention;
fig. 8 shows a flowchart of a method of fabricating a vertical hemt according to yet another embodiment of the present invention; and
fig. 9 shows a flowchart of a method of fabricating a vertical hemt according to yet another embodiment of the present invention.
Description of reference numerals:
100: a substrate; 110: a nucleation layer; 120: a buffer layer; 121: a first recess; 122: a second recess; 200: a current blocking layer; 201: a conductive via; 210: a diffusion preventing layer; 222: a p-type gallium nitride layer; 300: a channel layer; 310: a first two-dimensional electron gas; 320: a second two-dimensional electron gas; 400: a barrier layer; 401: a groove; 500: a passivation layer; 600: a semiconductor layer; 700: a gate electrode; 800: a source electrode; 900: a drain electrode; 1000: a vertical high electron mobility field effect transistor.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In one aspect of the present invention, a vertical high electron mobility field effect transistor is provided. According to an embodiment of the present invention, referring to fig. 1, the vertical type high electron mobility field effect transistor 1000 may include: a substrate 100, a current blocking layer 200, a channel layer 300, a barrier layer 400, a passivation layer 500, and a semiconductor layer 600. Wherein, the current blocking layer 200 is arranged at one side of the substrate 100, and the current blocking layer 200 is provided with a conductive through hole 201 therein; the channel layer 300 is disposed on a side of the current blocking layer 200 away from the substrate 100; the barrier layer 400 is disposed on a side of the channel layer 300 away from the current blocking layer 200, the first two-dimensional electron gas 310 is formed at an interface where the barrier layer 400 and the channel layer 300 are in contact, the first two-dimensional electron gas 310 is formed on the side of the channel layer 300, a groove (not marked in the drawing) is formed in the barrier layer 400, a distance between a bottom of the groove and the channel layer 300 is not more than 5nm, that is, a difference between a depth f of the groove and a thickness d of the barrier layer 300 is not more than 5nm (for example, referring to fig. 1, a distance between the bottom of the groove and the channel layer 300 is 0, that is, the depth f of the groove and the thickness; the passivation layer 500 is disposed on a side of the barrier layer 400 away from the channel layer 300, and the passivation layer 500 covers a sidewall of the barrier layer 400 facing the inside of the groove, the passivation layer 500 does not cover the bottom of the groove; the semiconductor layer 600 is disposed in the recess, and the second two-dimensional electron gas 320 is formed at the interface of the semiconductor layer 600 and the channel layer 300, the second two-dimensional electron gas 320 being formed at one side of the semiconductor layer 600. Therefore, the conductive channel formed by the first two-dimensional electron gas 310 passing through the conductive via 201 can be blocked by the passivation layer 500 and the second two-dimensional electron gas 320, so that the normally-off characteristic of the vertical high electron mobility field effect transistor 1000 device can be realized relatively easily, the voltage resistance of the vertical high electron mobility field effect transistor 1000 device is relatively good, the usability of the vertical high electron mobility field effect transistor 1000 device is relatively good, and the vertical high electron mobility field effect transistor 1000 device further has at least one of the following advantages: (1) the channel layer of the two-dimensional electron gas can be completely blocked without using a doping activation process, and the threshold voltage of the device is favorably improved; (2) the requirement on the precision of the etched groove is low, so that the process difficulty can be reduced; (3) two-dimensional electron gas in the conducting channel can be exhausted without utilizing an ion implantation process, the shutoff is realized, and the damage to the barrier layer caused by ion implantation can be avoided; (4) the normally-off characteristic of the device can be realized on a single chip without adopting a cascade mode, the cost can be reduced, and the introduction of additional parasitic parameters and the like can be avoided.
According to an embodiment of the present invention, the materials of the barrier layer 400, the channel layer 300, and the semiconductor layer 600 are not particularly limited as long as the forbidden bandwidth of the barrier layer 400 is greater than that of the channel layer 300 and the forbidden bandwidth of the semiconductor layer 6000 is less than that of the channel layer 300. Therefore, a heterojunction structure can be formed between the barrier layer 400 and the channel layer 300, a first two-dimensional electron gas 310 can be generated at a heterojunction interface, the first two-dimensional electron gas 310 can be formed at one side close to the channel layer 300, a heterojunction structure can be formed between the semiconductor layer 600 and the channel layer 300, a second two-dimensional electron gas 320 can be generated at the heterojunction interface, the second two-dimensional electron gas 320 can be formed at one side close to the semiconductor layer 600, the normally-off characteristic of the vertical high-electron-mobility field-effect transistor device 1000 can be better realized, the voltage resistance of the vertical high-electron-mobility field-effect transistor device 1000 is better, the reliability and the stability are higher, and the service performance is better.
According to an embodiment of the present invention, the material forming the substrate 100 is not particularly limited, and may be selected by those skilled in the art according to actual circumstances. For example, according to an embodiment of the present invention, the material forming the substrate 100 may include one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon. Therefore, the substrate 100 formed by the material can have better use performance.
The material forming the current blocking layer 200 is not particularly limited and may be selected as needed by those skilled in the art according to an embodiment of the present invention. For example, the material forming the current blocking layer 200 may include p-type gallium nitride. Therefore, when the current blocking layer 200 is formed of the material, the current leakage of the vertical high electron mobility field effect transistor 1000 can be well suppressed, and the usability of the vertical high electron mobility field effect transistor 1000 device can be improved. According to the embodiment of the invention, the thickness of the current blocking layer 200 may be h, specifically, h is 10nm ≦ h < 1000nm, for example, 20nm, 50nm, 100nm, 200nm, 300nm, 500nm, 600nm, 700nm, 800nm, 900nm, and the like. Thus, when the thickness of the current blocking layer 200 is within the above range, the current leakage of the vertical high electron mobility field effect transistor 1000 can be further suppressed, and the usability of the vertical high electron mobility field effect transistor 1000 device can be improved.
Specifically, the material forming the channel layer 300 is not particularly limited, and may be selected as needed by those skilled in the art. For example, the material forming the channel layer 300 may include unintentionally doped gallium nitride crystals. Therefore, when the channel layer 300 is formed of the material, the voltage endurance of the vertical high electron mobility field effect transistor 1000 device can be improved, and the vertical high electron mobility field effect transistor can operate at a higher temperature, and the channel layer 300 formed of the material and the barrier layer 400 formed subsequently can form a heterojunction structure better, and a two-dimensional electron gas with higher electron concentration and electron mobility can be generated at the heterojunction interface, and the on-resistance is lower, so that the usability of the vertical high electron mobility field effect transistor 1000 device can be further improved.
According to an embodiment of the present invention, referring to fig. 2, the vertical type high electron mobility field effect transistor 1000 may further include: the semiconductor device includes a nucleation layer 110, a buffer layer 120, and an anti-diffusion layer 210, wherein the nucleation layer 110 is disposed on one side of the substrate 100, the buffer layer 120 is disposed on one side of the nucleation layer 110 away from the substrate 100, the current blocking layer 200 is formed in the buffer layer 120, the anti-diffusion layer 210 is disposed on one side of the buffer layer 120 away from the nucleation layer 110, and the channel layer 300 is disposed on one side of the anti-diffusion layer 210 away from the buffer layer 120. Therefore, the nucleation layer 110 can match the substrate 100 material with the buffer layer 120, and the diffusion-preventing layer 210 can better prevent ions in the current-blocking layer from diffusing into the channel layer in the subsequent process, thereby reducing the mobility of the two-dimensional electron gas of the channel layer. According to an embodiment of the present invention, the material forming the buffer layer 120 may include one or more of n-type gallium nitride crystals, unintentionally doped gallium nitride crystals. Therefore, the buffer layer 120 formed by the material can inhibit the current leakage of the vertical high electron mobility field effect transistor 1000 and improve the service performance of the vertical high electron mobility field effect transistor 1000 device. Specifically, the material forming the diffusion preventing layer 210 may include aluminum nitride. Therefore, the diffusion-preventing layer 210 formed by the material can better prevent ions in the current-blocking layer from diffusing into the channel layer in the subsequent process, so that the mobility of two-dimensional electron gas of the channel layer is reduced.
According to an embodiment of the present invention, the barrier layer 400 may have a forbidden bandwidth greater than that of the channel layer 300. Therefore, a heterojunction structure can be formed between the barrier layer 400 and the channel layer 300, the first two-dimensional electron gas 310 with higher concentration can be formed at the heterojunction interface, and the first two-dimensional electron gas 310 can be formed at the side close to the channel layer 300 with smaller forbidden band width, so that the use performance of the vertical high electron mobility field effect transistor 1000 device can be further improved.
According to an embodiment of the present invention, the material forming the barrier layer 400 is not particularly limited and may be selected as needed by those skilled in the art. Specifically, the material forming the barrier layer 400 may include AlmGa(1-m)N crystal, wherein m is 0.15-0.80, and specifically m can be 0.2, 0.3, 0.4, or0.5, 0.6, 0.7, etc. Therefore, a heterojunction structure can be formed between the barrier layer 400 and the channel layer 300, the first two-dimensional electron gas 310 with high concentration can be formed at the heterojunction interface, and the first two-dimensional electron gas 310 can be formed at the side close to the channel layer 300 with small forbidden band width, so that the service performance of the vertical high electron mobility field effect transistor 1000 device can be further improved. Specifically, the thickness of the barrier layer 400 may be not less than 30nm, for example, 35nm, 40nm, 45nm, or the like. Therefore, when the thickness of the barrier layer 400 is within the above range, the barrier layer can have better performance, and the performance of the vertical high electron mobility field effect transistor 1000 device can be further improved.
The material forming the passivation layer 500 is not particularly limited and may be selected as needed by those skilled in the art according to an embodiment of the present invention. Specifically, the material forming the passivation layer 500 may include one or more of silicon dioxide and silicon nitride. Therefore, the passivation layer 500 formed by the material can improve the surface state of the device, can isolate the barrier layer 400 from the semiconductor layer 600, prevent the barrier layer 400 and the semiconductor layer 600 from influencing each other, form two-dimensional electron gas, generate leakage current and other undesirable problems, and can isolate the first two-dimensional electron gas 310 flowing through the conductive through hole 201 together with the second two-dimensional electron gas 320 by the passivation layer 500.
According to an embodiment of the present invention, the band gap of the semiconductor layer 600 may be smaller than the band gap of the channel layer 300. Therefore, a heterojunction structure can be formed between the semiconductor layer 600 and the channel layer 300, the second two-dimensional electron gas 320 with higher concentration can be formed at the heterojunction interface, and the second two-dimensional electron gas 320 is formed at a side close to the semiconductor layer 600 with smaller forbidden bandwidth, and the second two-dimensional electron gas 320 can enable a side of the channel layer 300 corresponding to the semiconductor layer 600 (i.e. a region below the groove) to generate holes for induced polarization, so that the first two-dimensional electron gas 310 in the region below the groove can be depleted, the first two-dimensional electron gas 310 can be further blocked from flowing through the conductive channel formed by the conductive through hole 201, the normally-off characteristic of the vertical high electron mobility field effect transistor 1000 device can be simply realized, and the use performance of the vertical high electron mobility field effect transistor 1000 device can be further improved.
According to an embodiment of the present invention, a material forming the semiconductor layer 600 is not particularly limited and may be selected as needed by those skilled in the art. Specifically, the material forming the semiconductor layer 600 may include InnGa(1-n)N is more than 0 and less than or equal to 0.45, and specifically, N can be 0.1, 0.2, 0.3, 0.4 and the like. Therefore, the semiconductor layer 600 formed by the material can further improve the concentration of the second two-dimensional electron gas 320 at the heterojunction interface, improve the electron mobility, and further improve the service performance of the vertical high electron mobility field effect transistor 1000 device. Specifically, the thickness of the semiconductor layer 600 may be not less than 30nm, for example, 35nm, 40nm, 45nm, or the like. Thus, when the thickness of the semiconductor layer 600 is in the above range, the use performance of the vertical type high electron mobility field effect transistor 1000 device can be further improved.
According to an embodiment of the present invention, referring to fig. 2, the vertical type hemt 1000 may further include: a gate 700, a source 800 and a drain 900, wherein the gate 700 is disposed on a side of the semiconductor layer 600 away from the channel layer 300, an orthographic projection of the recess on the substrate 100 is not larger than an orthographic projection of the gate 700 on the substrate 100, an orthographic projection of the gate 700 on the substrate 100 is not smaller than an orthographic projection of a conductive via (not shown in the figures, refer to the conductive via 201 in fig. 1) on the substrate 100, the source 800 is disposed on a side of the barrier layer 400 away from the channel layer 300, the source 800 is in contact with the barrier layer 400, and the drain 900 is disposed on a side of the substrate 100 away from the nucleation layer 110. Therefore, the gate 700 can form better schottky contact with the semiconductor layer 600, the source 800 can directly contact with the barrier layer 400 to form better ohmic contact, the drain 900 is manufactured below the substrate 100, the whole surface of the device can be in a low electric field state, the concentration of an electric field at the edge of the gate 700 can be effectively avoided, the voltage resistance of the device is not limited by the transverse size, the device mainly bears voltage resistance through the longitudinal distance between the gate 700 and the drain 900, the transverse size of the device can be designed to be smaller, the area of the device can be effectively saved, and the use performance of the vertical high electron mobility field effect transistor 1000 device can be further improved. Specifically, the material forming the gate electrode 700 may include one or more of nickel, gold, palladium, and platinum. Therefore, the gate 700 formed by the material can form a better schottky contact with the semiconductor layer 600, and the service performance of the vertical high electron mobility field effect transistor 1000 device can be further improved. Specifically, the material forming the source electrode 800 and the drain electrode 900 may include one or more of titanium, aluminum, nickel, gold, and tantalum. Therefore, the source electrode 800 formed by the material can be directly contacted with the barrier layer 400 to form better ohmic contact, the drain electrode 900 formed by the material has better performance, and the service performance of the vertical high electron mobility field effect transistor 1000 device can be further improved.
In summary, according to the vertical hemt 1000 of the embodiment of the present invention, the conductive channel formed by the first two-dimensional electron gas 310 through the conductive via 201 can be blocked by the passivation layer 500 and the second two-dimensional electron gas 320, so that the normally-off characteristic of the vertical hemt 1000 can be easily realized, the vertical hemt 1000 has good usability, high breakdown voltage, good voltage endurance, high reliability and stability, and when the vertical hemt 1000 operates, when an external voltage is applied to the gate 700, the second two-dimensional electron gas 320 can be exhausted, the induced polarization holes generated at the side of the channel layer 300 corresponding to the lower side of the gate 700 disappear, and the first two-dimensional electron gas 310 can be turned on again through the conductive channel formed by the conductive via 201, the vertical high electron mobility field effect transistor 1000 device has good use performance.
In another aspect of the present invention, the present invention provides a method of manufacturing the vertical-type high electron mobility field effect transistor described above. Referring to fig. 3 and 4, according to an embodiment of the present invention, the method includes:
s100: providing a substrate
In this step, a substrate is provided. According to an embodiment of the present invention, referring to (a) of fig. 4, a material forming the substrate 100 is not particularly limited, for example, the material forming the substrate 100 may include one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon. Therefore, the substrate 100 formed by the material has better service performance, and the service performance of the vertical high electron mobility field effect transistor can be improved.
According to an embodiment of the present invention, in order to further improve the performance of the fabricated hemt, after providing the substrate 100, the method may further include: a nucleation layer (not shown) is disposed on one side of the substrate 100, a buffer layer (not shown) is disposed on one side of the nucleation layer away from the substrate 100, and an anti-diffusion layer (not shown) is formed on one side of the buffer layer away from the nucleation layer. Therefore, the service performance of the vertical high electron mobility field effect transistor device can be further improved.
S200: forming a current blocking layer on one side of the substrate, the current blocking layer having a conductive via therein
In this step, a current blocking layer having a conductive via therein is formed on one side of a substrate. According to an embodiment of the present invention, referring to (b) of fig. 4, a current blocking layer 200 is formed at one side of a substrate 100, the current blocking layer 200 having a conductive via 201 therein. Specifically, the material forming the current blocking layer 200 is not particularly limited, and for example, the material forming the current blocking layer 200 may include p-type gallium nitride. Therefore, when the current blocking layer 200 is formed of the material, the current leakage of the vertical high electron mobility field effect transistor can be suppressed well, and the usability of the vertical high electron mobility field effect transistor can be further improved. According to the embodiment of the invention, the thickness of the current blocking layer 200 may be h, specifically, h is 10nm ≦ h < 1000nm, for example, 20nm, 50nm, 100nm, 200nm, 300nm, 500nm, 600nm, 700nm, 800nm, 900nm, and the like. Thus, when the thickness of the current blocking layer 200 is within the above range, the current leakage of the vertical high electron mobility field effect transistor can be further suppressed, and the usability of the vertical high electron mobility field effect transistor can be improved. Specifically, the current blocking layer 200 may be formed in the buffer layer. This makes it possible to form the current blocking layer 200 relatively easily.
According to an embodiment of the present invention, referring to fig. 7, before forming the current blocking layer 200, the method may further include: the buffer layer 120 is formed on one side of the substrate 100, and the material forming the buffer layer 120 may include: one or more of an n-type gallium nitride crystal, an unintentionally doped gallium nitride crystal. Therefore, the buffer layer 120 formed of the material can suppress current leakage of the vertical high electron mobility field effect transistor, and improve the use performance of the vertical high electron mobility field effect transistor device. Specifically, the forming of the current blocking layer 200 may further include: implanting Mg into a part of the surface of the buffer layer 120 on the side away from the substrate 100 by an ion implantation process2+、Al3+And forming a current blocking layer 200 on a side of the buffer layer away from the substrate 100 by an annealing process, the current blocking layer 200 having a conductive via 201 in which ions are not implanted, the material forming the current blocking layer 200 may include p-type gallium nitride. Thus, the current blocking layer 200 can be formed in the buffer layer 120 more easily, and the use performance of the vertical hemt device can be further improved.
Specifically, referring to fig. 8, after forming the buffer layer 120 on one side of the substrate 100, forming the current blocking layer 200 may further include: and growing a p-type gallium nitride layer 222 in situ on one side of the buffer layer 120 far away from the substrate 100, and forming a conductive through hole 201 in the p-type gallium nitride layer 222 through dry etching treatment to form the current blocking layer 200. Thus, the current blocking layer 200 can be formed on the buffer layer 120 side more easily, and the use performance of the vertical hemt device can be further improved.
Specifically, referring to fig. 9, after forming the buffer layer 120 on one side of the substrate 100, forming the current blocking layer 200 may further include: performing dry etching treatment on a partial region of the buffer layer 120 to form a first recess 121 and a second recess 122 after etching and an unetched conductive via 201, wherein the conductive via 201 is located between the first recess 121 and the second recess 122; a p-type gallium nitride layer is secondarily epitaxially grown in the first and second recesses 121 and 122 to form the current blocking layer 200 having the conductive via 201. Thus, the current blocking layer 200 can be formed in the buffer layer 120 more easily, and the use performance of the vertical hemt device can be further improved.
S300: forming a channel layer on the side of the current barrier layer far away from the substrate
In this step, a channel layer is formed on a side of the current blocking layer away from the substrate. According to an embodiment of the present invention, referring to (c) of fig. 4, the channel layer 300 is formed on a side of the current blocking layer 200 away from the substrate 100. Specifically, the material forming the channel layer 300 is not particularly limited, and for example, the material forming the channel layer 300 may include unintentionally doped gallium nitride crystals. Therefore, when the channel layer 300 is formed by the material, the voltage resistance of the vertical high electron mobility field effect transistor device can be improved, the vertical high electron mobility field effect transistor device can work at a higher temperature, a heterojunction structure can be well formed between the channel layer 300 formed by the material and a barrier layer formed subsequently, two-dimensional electron gas with higher electron concentration and electron mobility can be generated at a heterojunction interface, the on-resistance is lower, and the use performance of the vertical high electron mobility field effect transistor device can be further improved.
S400: forming a barrier layer on the channel layer far away from the current barrier layer, and forming a groove in the barrier layer
In the step, a barrier layer is formed on the side of the channel layer away from the current blocking layer, and a groove is formed in the barrier layer. According to an embodiment of the present invention, referring to (d) of fig. 4, a barrier layer 400 is formed on a side of the channel layer 300 away from the current blocking layer 200, and a recess 401 is formed in the barrier layer 400. Specifically, the barrier layer 400 is formed on a side of the channel layer 300 away from the current blocking layer 200, the first two-dimensional electron gas 310 is formed at an interface where the barrier layer 400 and the channel layer 300 are in contact, the first two-dimensional electron gas 310 is formed on the side of the channel layer 300, a groove 401 is formed in the barrier layer 400, a distance between a bottom of the groove 401 and the channel layer 300 is not more than 5nm, that is, a difference between a depth f of the groove 401 and a thickness d of the barrier layer 300 is not more than 5 nm. Therefore, the process for forming the groove 401 is also simple, and the use performance of the vertical high electron mobility field effect transistor can be further improved. Specifically, the distance between the bottom of the groove 401 and the channel layer 300 is not greater than 5nm, for example, may be 3nm, may be 1nm, and may be 0, that is, the depth f of the groove 401 is equal to the thickness of the barrier layer 400, so that when a semiconductor layer is subsequently formed in the groove 401, a second two-dimensional electron gas may be better formed between the semiconductor layer and the channel layer 300, and the etching process of the groove 401 is simpler, the requirement for etching accuracy is lower, and the operation is facilitated.
Specifically, the energy gap of the barrier layer 400 may be larger than that of the channel layer 300, and thus, the first two-dimensional electron gas 310 may be preferably formed near the channel layer 300 having a smaller energy gap. Specifically, the material forming the barrier layer 400 may include AlmGa(1-m)And (3) N crystals, wherein m is more than or equal to 0.15 and less than or equal to 0.80. Thus, the barrier layer 400 formed of the material can further improve the use performance of the vertical high electron mobility field effect transistor. Specifically, the thickness d of the barrier layer 400 may be not less than 30nm, for example, 35nm, 40nm, 45nm, or the like. Thus, when the thickness d of the barrier layer 400 is in the above range, the use performance of the vertical hemt device may be further improved. Specifically, referring to fig. 5, the forming the barrier layer may further include:
s401: forming barrier layer preforms
In this step, Al may be grown on the side of the channel layer away from the current blocking layermGa(1-m)N crystal material, wherein 0.15 m 0.80, to form a barrier layer preform.
S402: setting a first mask
In this step, a first mask may be provided on a partial surface of the barrier layer preform on a side away from the channel layer. Specifically, the material forming the first mask may include silicon dioxide or silicon nitride.
S403: carrying out first dry etching treatment on the barrier layer prefabricated body which is not covered by the first mask to form a groove
In this step, a barrier layer preform not covered by the first mask may be subjected to a first dry etching process, for example, the barrier layer preform not covered by the first mask may be etched by inductively coupled plasma etching (ICP), Reactive Ion Etching (RIE), electron cyclotron resonance plasma Etching (ECR), Ion Beam Etching (IBE), or the like, so as to form a groove, wherein a difference between an etching depth of the first dry etching process and a thickness of the barrier layer preform is not more than 5 nm. Therefore, the requirement on etching precision during groove forming is low, the process difficulty can be reduced, and the vertical high-electron-mobility field effect transistor device with good performance can be well prepared.
S404: removing the first mask to form a barrier layer
In this step, the first mask is removed, and a barrier layer having a recess is formed. Therefore, the barrier layer can be formed more simply and conveniently, and the vertical high-electron-mobility field effect transistor device with better performance can be prepared.
According to an embodiment of the present invention, after forming the barrier layer, the method may further include: and preparing a source electrode on the surface of the barrier layer on the side far away from the channel layer. Specifically, a metal material may be deposited on a region corresponding to the source electrode by using at least one of an electron beam evaporation technique or a magnetron sputtering technique, so as to form the source electrode, and then the source electrode is annealed so as to form the source electrode ohmic contact. Specifically, the material forming the source electrode may include one or more of titanium, aluminum, nickel, gold, and tantalum. Therefore, the service performance of the prepared vertical high electron mobility field effect transistor device can be further improved.
According to an embodiment of the present invention, after forming the barrier layer, the method may further include: and preparing a drain electrode on the surface of the substrate on the side far away from the nucleation layer. Specifically, a metal material may be deposited on a region corresponding to the drain electrode by using at least one of an electron beam evaporation technique or a magnetron sputtering technique, so as to form the drain electrode, and then the drain electrode is annealed, so as to form a drain electrode ohmic contact. Specifically, the material forming the drain electrode may include one or more of titanium, aluminum, nickel, gold, and tantalum. Therefore, the service performance of the prepared vertical high electron mobility field effect transistor device can be further improved.
S500: forming a passivation layer on the side of the barrier layer away from the channel layer
In this step, a passivation layer is formed on the side of the barrier layer away from the channel layer. According to an embodiment of the present invention, referring to (e) of fig. 4, a passivation layer 500 is formed on a side of the barrier layer 400 away from the channel layer 300, the passivation layer 500 covers a sidewall of the barrier layer 400 facing the inside of the groove 401, and the passivation layer 500 does not cover the bottom of the groove 401. Therefore, the passivation layer 500 can better improve the surface state of the device, isolate the barrier layer 400 from the semiconductor layer formed in the groove 401, prevent the barrier layer 400 from influencing the semiconductor layer formed in the groove 401, form two-dimensional electron gas, generate leakage current and other undesirable problems, and isolate the first two-dimensional electron gas 310 from the passivation layer 500 and the second two-dimensional electron gas 320. Specifically, the material forming the passivation layer 500 may include one or more of silicon dioxide and silicon nitride. Therefore, the passivation layer 500 formed by the material can further improve the surface state of the device, isolate the barrier layer 400 from a semiconductor layer formed in the groove 401 subsequently, and improve the service performance of the prepared vertical high electron mobility field effect transistor device. Specifically, referring to fig. 6, the forming of the passivation layer may further include:
s501: forming passivation layer preforms
In this step, a passivation layer material may be deposited on the side of the barrier layer remote from the channel layer in order to form a passivation layer preform. Specifically, a passivation layer may be grown on a side of the barrier layer away from the channel layer (i.e., in a region between the source electrodes) using a Metal Organic Chemical Vapor Deposition (MOCVD) or a Plasma Enhanced Chemical Vapor Deposition (PECVD). Therefore, the passivation layer can be generated more conveniently, and the service performance of the prepared vertical high-electron-mobility field effect transistor device can be further improved.
S502: providing a second mask covering the region except the bottom of the groove
In this step, a second mask may be provided on the surface of the passivation layer preform, the second mask covering the region except the bottom of the recess. Specifically, the material forming the second mask may include silicon dioxide or silicon nitride.
S503: performing second dry etching treatment on the passivation layer prefabricated body which is not covered by the second mask to form a passivation layer
In this step, a passivation layer is formed by performing a second dry etching process on the passivation layer preform not covered by the second mask. Specifically, the passivation layer preform not covered by the second mask may be subjected to a second dry etching process, for example, the passivation layer preform not covered by the second mask may be etched by using inductively coupled plasma etching (ICP), Reactive Ion Etching (RIE), electron cyclotron resonance plasma Etching (ECR), Ion Beam Etching (IBE), or the like, so as to form a passivation layer covering a surface of the barrier layer on a side away from the channel layer and covering a sidewall of the barrier layer facing the inside of the groove. Therefore, the passivation layer can be formed more conveniently, and the service performance of the prepared vertical high-electron-mobility field effect transistor device can be further improved.
S504: removing the second mask
In this step, the second mask is removed. Therefore, the passivation layer can be formed more conveniently, the passivation layer can better cover the surface of the barrier layer far away from one side of the channel layer and cover the side wall of the barrier layer facing the inside of the groove, the surface state of the device is better improved, the barrier layer and a semiconductor layer formed in the groove in the follow-up process can be isolated, the barrier layer and the semiconductor layer formed in the groove in the follow-up process are prevented from being influenced mutually, two-dimensional electron gas is formed, the poor problems of leakage current and the like are solved, the passivation layer can separate the first two-dimensional electron gas from the second two-dimensional electron gas, and the service performance of the prepared vertical high-electron-mobility field effect transistor device can be further improved.
S600: forming a semiconductor layer in the recess
In this step, a semiconductor layer is formed in the groove. According to an embodiment of the present invention, referring to (f) of fig. 4, a semiconductor layer 600 is formed in the recess 401, a second two-dimensional electron gas 320 is formed at an interface of the semiconductor layer 600 and the channel layer 300, and the second two-dimensional electron gas 320 is formed at a side of the semiconductor layer 600. Therefore, the second two-dimensional electron gas 320 can generate polarization-inducing holes on one side of the channel layer 300 corresponding to the semiconductor layer 600 (i.e., the region below the recess 401), so that the first two-dimensional electron gas 310 in the region below the recess 401 can be depleted, the first two-dimensional electron gas 310 can be further blocked from flowing through a conductive channel formed by a conductive via, a normally-off vertical high electron mobility field effect transistor device can be simply and conveniently prepared, and the use performance of the vertical high electron mobility field effect transistor device can be further improved. Specifically, a semiconductor material may be deposited in the groove 401 using a Metal Organic Chemical Vapor Deposition (MOCVD) method to form the semiconductor layer 600. This enables the semiconductor layer 600 to be formed relatively easily. Specifically, the material forming the semiconductor layer 600 may include InnGa(1-n)N crystal, wherein N is more than 0 and less than or equal to 0.45. Thus, the semiconductor layer 600 formed of the material may have a smaller forbidden band width than the channel layer 300, the second two-dimensional electron gas 320 having a higher concentration and a higher electron mobility may be formed at the heterojunction interface between the semiconductor layer 600 and the channel layer 300, and the second two-dimensional electron gas 320 is formed near the semiconductor layer 600 having a smaller forbidden band width, the second two-dimensional electron gas 320 may generate polarization-inducing holes at a side of the channel layer 300 corresponding to the semiconductor layer 600 (i.e., a region below the groove), therefore, the first two-dimensional electron gas 310 in the region below the groove can be exhausted, the first two-dimensional electron gas 310 can be further blocked from flowing through the conductive channel formed by the conductive through hole, the vertical high electron mobility field effect transistor device with normally-off characteristic can be simply prepared, and the prepared vertical high electron mobility field effect transistor device can be further improved.The performance is used. Specifically, the thickness of the semiconductor layer 600 may be not less than 30nm, for example, 35nm, 40nm, 45nm, or the like. Thus, when the thickness of the semiconductor layer 600 is in the above range, the use performance of the vertical type high electron mobility field effect transistor device can be further improved.
According to an embodiment of the present invention, after forming the semiconductor layer 600 in the groove 401, the method may further include: by using a photolithography process, a gate window is etched on a side of the semiconductor layer 600 away from the channel layer 300, and a gate is formed in the gate window. Specifically, the gate electrode may be formed by depositing a metal material in the gate window using an electron beam evaporation technique or a magnetron sputtering technique. Thereby, the gate electrode may form a schottky contact with the semiconductor layer 600. Specifically, the material forming the gate electrode may include one or more of nickel, gold, palladium, and platinum. Therefore, the grid electrode formed by the material can form better Schottky contact with the semiconductor layer 600, and the service performance of the prepared vertical high electron mobility field effect transistor device can be further improved.
In summary, the method includes forming a first two-dimensional electron gas at an interface where a barrier layer and a channel layer are in contact with each other, the first two-dimensional electron gas being formed at one side of the channel layer, forming a groove in the barrier layer such that a difference between a depth of the groove and a thickness of the barrier layer is not greater than 5nm, forming a passivation layer at a side of the barrier layer away from the channel layer such that the passivation layer covers a sidewall of the barrier layer facing an inside of the groove and the passivation layer does not cover a bottom of the groove, forming a semiconductor layer in the groove, forming a second two-dimensional electron gas at an interface between the semiconductor layer and the channel layer, the second two-dimensional electron gas being formed at one side of the semiconductor layer, wherein a conduction channel formed by the first two-dimensional electron gas passing through a conduction through hole can be blocked by the passivation layer and the second two-dimensional electron gas, the vertical high-electron-mobility field effect transistor device prepared by the method has the advantages of good use performance, high breakdown voltage, good voltage resistance, and high reliability and stability.
In the description of the present specification, the terms "upper", "lower", "bottom", "one side", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the present invention but do not require that the present invention must be constructed and operated in a specific orientation, and thus, are not to be construed as limiting the present invention.
In the description herein, references to the description of "one embodiment," "another embodiment," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (13)
1. A vertical high electron mobility field effect transistor, comprising:
a substrate;
a current blocking layer disposed on one side of the substrate, the current blocking layer having a conductive via therein;
the channel layer is arranged on one side, far away from the substrate, of the current blocking layer;
a barrier layer disposed on a side of the channel layer away from the current blocking layer, a first two-dimensional electron gas being formed at an interface where the barrier layer and the channel layer are in contact, the first two-dimensional electron gas being formed on the side of the channel layer, the barrier layer having a groove therein, a distance between a bottom of the groove and the channel layer being not more than 5 nm;
the passivation layer is arranged on one side, far away from the channel layer, of the barrier layer, covers the side wall, facing the inside of the groove, of the barrier layer, and does not cover the bottom of the groove;
a semiconductor layer disposed in the groove, a second two-dimensional electron gas formed at an interface of the semiconductor layer and the channel layer, the second two-dimensional electron gas being formed at one side of the semiconductor layer.
2. The vertical high electron mobility field effect transistor according to claim 1, wherein the barrier layer has a forbidden bandwidth greater than that of the channel layer, and the semiconductor layer has a forbidden bandwidth less than that of the channel layer.
3. The vertical hemt of claim 1, wherein said barrier layer is formed from a material comprising AlmGa(1-m)And the N crystal, wherein m is more than or equal to 0.15 and less than or equal to 0.80, and the thickness of the barrier layer is not less than 30 nm.
4. The vertical high electron mobility field effect transistor according to claim 1, wherein a material forming the semiconductor layer comprises InnGa(1-n)And N is more than 0 and less than or equal to 0.45, and the thickness of the semiconductor layer is not less than 30 nm.
5. The vertical high electron mobility field effect transistor according to claim 1, wherein the thickness of the current blocking layer is h, and h is 10nm ≦ h < 1000 nm.
6. The vertical high electron mobility field effect transistor of claim 1, further comprising:
a nucleation layer disposed on one side of the substrate;
a buffer layer disposed on a side of the nucleation layer remote from the substrate, the current blocking layer being formed in the buffer layer;
the diffusion preventing layer is arranged on one side of the buffer layer far away from the nucleating layer;
the channel layer is arranged on one side, far away from the buffer layer, of the diffusion-proof layer;
the grid electrode is arranged on one side, away from the channel layer, of the semiconductor layer, the orthographic projection of the groove on the substrate is not larger than that of the grid electrode on the substrate, and the orthographic projection of the grid electrode on the substrate is not smaller than that of the conductive through hole on the substrate;
the source electrode is arranged on one side, far away from the channel layer, of the barrier layer, and the source electrode is in contact with the barrier layer;
a drain disposed on a side of the substrate away from the nucleation layer.
7. The vertical high electron mobility field effect transistor according to claim 6,
the material for forming the substrate comprises one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium and silicon;
the material forming the buffer layer comprises one or more of n-type gallium nitride crystals and unintentionally doped gallium nitride crystals;
the material for forming the diffusion preventing layer comprises aluminum nitride;
the material for forming the current blocking layer comprises p-type gallium nitride;
the material forming the channel layer comprises unintentionally doped gallium nitride crystals;
the material for forming the passivation layer comprises one or more of silicon dioxide and silicon nitride;
the material for forming the source electrode and the drain electrode comprises one or more of titanium, aluminum, nickel, gold and tantalum;
the material for forming the grid electrode comprises one or more of nickel, gold, palladium and platinum.
8. A method of manufacturing the vertical high electron mobility field effect transistor of any of claims 1 to 7, comprising:
providing a substrate;
forming a current blocking layer on one side of the substrate, wherein the current blocking layer is provided with a conductive through hole;
forming a channel layer on one side of the current blocking layer far away from the substrate;
forming a barrier layer on one side of the channel layer far away from the current blocking layer, wherein a first two-dimensional electron gas is formed at an interface where the barrier layer and the channel layer are in contact, the first two-dimensional electron gas is formed on one side of the channel layer, a groove is formed in the barrier layer, and the distance between the bottom of the groove and the channel layer is not more than 5 nm;
forming a passivation layer on one side of the barrier layer away from the channel layer, wherein the passivation layer covers the side wall of the barrier layer facing the inner part of the groove, and the passivation layer does not cover the bottom of the groove;
and forming a semiconductor layer in the groove, wherein a second two-dimensional electron gas is formed at the interface of the semiconductor layer and the channel layer, and the second two-dimensional electron gas is formed on one side of the semiconductor layer.
9. The method of claim 8, wherein forming the barrier layer further comprises:
growing Al on the side of the channel layer far away from the current barrier layermGa(1-m)An N crystal material, wherein m is 0.15-0.80, so as to form a barrier layer preform;
arranging a first mask on the partial surface of one side of the barrier layer prefabricated body far away from the channel layer;
performing a first dry etching process on the barrier layer preform uncovered by the first mask so as to form the groove, wherein a difference between an etching depth of the first dry etching process and a thickness of the barrier layer preform is not more than 5 nm;
and removing the first mask to form the barrier layer.
10. The method of claim 8, wherein forming the passivation layer further comprises:
depositing a passivation layer material on a side of the barrier layer remote from the channel layer to form a passivation layer preform;
arranging a second mask on the surface of the passivation layer prefabricated body, wherein the second mask covers the region except the bottom of the groove;
performing a second dry etching treatment on the passivation layer prefabricated body which is not covered by the second mask so as to form the passivation layer, wherein the passivation layer covers the surface of the barrier layer on the side far away from the channel layer and covers the side wall of the barrier layer facing the inside of the groove;
and removing the second mask.
11. The method of claim 8, wherein prior to forming the current blocking layer, the method further comprises:
forming a buffer layer on one side of the substrate, the buffer layer being formed of a material including: one or more of an n-type gallium nitride crystal, an unintentionally doped gallium nitride crystal;
forming the current blocking layer further comprises:
implanting Mg into partial surface of the buffer layer far away from the substrate by ion implantation process2+、Al3+And forming a current blocking layer on the side of the buffer layer far away from the substrate through an annealing process, wherein the current blocking layer is provided with a conductive through hole which is not implanted with ions, and the material for forming the current blocking layer comprises p-type gallium nitride.
12. The method of claim 8, wherein prior to forming the current blocking layer, the method further comprises:
forming a buffer layer on one side of the substrate, the buffer layer being formed of a material including: one or more of an n-type gallium nitride crystal, an unintentionally doped gallium nitride crystal;
forming the current blocking layer further comprises:
and growing a p-type gallium nitride layer in situ on one side of the buffer layer, which is far away from the substrate, and forming the conductive through hole in the p-type gallium nitride layer through dry etching treatment to form the current blocking layer.
13. The method of claim 8, wherein prior to forming the current blocking layer, the method further comprises:
forming a buffer layer on one side of the substrate, the buffer layer being formed of a material including: one or more of an n-type gallium nitride crystal, an unintentionally doped gallium nitride crystal;
performing dry etching treatment on a partial region of the buffer layer so as to form a first depressed part and a second depressed part after etching and the conductive through hole which is not etched, wherein the conductive through hole is positioned between the first depressed part and the second depressed part;
epitaxially growing a p-type gallium nitride layer twice in the first and second recesses so as to form the current blocking layer having the conductive via.
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