CN108597451B - 像素驱动电路 - Google Patents
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Abstract
一种像素驱动电路,其具有第一晶体管,透过第一端或栅极端接收数据信号。第二晶体管的第一端连接于第一晶体管的第一端,栅极端连接第二晶体管的第二端。第三晶体管的第二端连接第二晶体管的第二端,栅极端接收第一扫描信号。第四晶体管的第一端连接第一晶体管的栅极端,栅极端接收第一扫描信号。第五晶体管的第二端连接第一晶体管的第一端,栅极端接收第二扫描信号。第六晶体管的第一端连接第一晶体管的第二端,栅极端接收第二扫描信号。发光二极管的阳极端连接第六晶体管的第二端。电容连接第一晶体管的第一端与栅极端之间。借助本发明能够减少电路布局面积,且减少功率消耗。
Description
技术领域
本发明涉及一种像素驱动电路;具体而言,本发明涉及一种具有发光二极管显示装置的像素驱动电路。
背景技术
一般而言,发光二极管显示装置中具有数据电路、扫描电路、像素驱动电路。像素驱动电路根据数据电路提供的数据信号及扫描电路提供的扫描信号驱动发光二极管发光。一般而言,发光二极管的驱动电流与数据信号及像素驱动电路中晶体管的临界电压有关;然而前述临界电压往往因制程因素存在偏异而影响发光二极管实际亮度。
为解决上述问题,现有的有机发光二极管显示装置或有提出像素驱动电路的改善设计以消除临界电压的影响。然而,现有的改善设计通常需要多个控制信号,因此所需电路布局面积较大且面板边框的电路结构较为复杂。此外,现有的改善设计在电路操作时可能存在直流静态电流路径,这将造成额外的功率消耗。因此,现有有机发光二极管显示装置的电路结构仍有待改进。
发明内容
本发明提供一种像素驱动电路,其包含第一晶体管,透过第一端或栅极端接收数据信号。第二晶体管的第一端连接于第一晶体管的第一端,栅极端连接第二晶体管的第二端。第三晶体管的第二端连接第二晶体管的第二端,栅极端接收第一扫描信号。第四晶体管的第一端连接第一晶体管的栅极端,栅极端接收第一扫描信号。第五晶体管的第二端连接第一晶体管的第一端,栅极端接收第二扫描信号。第六晶体管的第一端连接第一晶体管的第二端,栅极端接收第二扫描信号。发光二极管的阳极端连接第六晶体管的第二端。电容连接第一晶体管的第一端与栅极端之间。
本发明的一目的在于提供一种像素驱动电路,可提供稳定的驱动电流。
本发明的一目的在于提供一种像素驱动电路,可窄化显示面板周边区,并降低功率消耗。
附图说明
图1为本发明像素驱动电路的一实施例示意图。
图2为像素驱动电路的信号示意图。
图3A及图3B为对应图2所示出像素驱动电路于不同操作方式示意图。
图4及图5为像素驱动电路具有单一扫描信号的不同实施例示意图。
图6为像素驱动电路的另一实施例示意图。
图7及图8为像素驱动电路具有单一扫描信号的不同实施例示意图。
附图标记说明:
10,10A,10B,10C,10D,10E:像素驱动电路 OVDD:供应电压
102:发光二极管 OVSS:供应电压
C:电容 S:扫描信号
DATA:数据信号 T1~T7:晶体管
EM:扫描信号 VREF:参考信号
具体实施方式
以下将以附图及详细叙述清楚说明本揭示内容的精神,任何所属技术领域中普通技术人员在了解本申请所揭示内容的实施例后,当可由本申请揭示内容所教示的技术,加以改变及修饰,其并不脱离本申请揭示内容的精神与范围。
关于本文中所使用的“第一”、“第二”、……等,并非特别指称次序或顺位的意思,也并非用以限定本发明,而仅为了区别以相同技术用语描述的元件或操作。
关于本文中所使用的“电性耦接”,可指二或多个元件相互直接作实体或电性接触,或是相互间接作实体或电性接触,而“电性耦接”还可指二或多个元件相互操作或动作。
关于本文中所使用的“包含”、“包含”、“具有”、“含有”等等,均为开放性的用语,即意指包含但不限于。
关于本文中所使用的“及/或”,包含所述事物的任一或全部组合。
关于本文中所使用的用词(terms),除有特别注明外,通常具有每个用词使用在此领域中、在此揭露的内容中与特殊内容中的平常意义。某些用以描述本揭露的用词将于下面或在本说明书的别处讨论,以提供本领域技术人员在有关本揭露的描述上额外的引导。
下文依本发明的像素驱动电路,特举实施例配合所附图式作详细说明,但所提供的实施例并非用以限制本发明所涵盖的范围。
本发明提供一种像素驱动电路,其可用于例如有机发光二极管显示器。请参考图1,图1为本发明像素驱动电路的一实施例示意图。如图1所示,像素驱动电路10可具有晶体管T1~T5及晶体管T7、电容C,以及发光二极管102。上述晶体管T1~T5及T7,例如为薄膜晶体管,各晶体管包含包含第一端、第二端、栅极端。晶体管T4透过其第一端接收数据信号。晶体管T2的第一端电性连接于晶体管T4的第一端,而栅极端则连接晶体管T2的第二端。晶体管T3的第一端接收第一电压信号,第二端连接第二晶体管的第二端。第三晶体管的栅极端接收扫描信号S,并根据第一扫描信号导通第三晶体管。在此实施例,第一电压信号为数据信号DATA,且第二电压信号为参考信号VREF,数据信号DATA的电压电平大于参考信号VREF的电压电平。晶体管T5的第一端电性连接晶体管T4的栅极端,第二端接收第二电压信号(VREF)。晶体管T5的栅极端接收扫描信号S,并根据扫描信号S导通晶体管T5。晶体管T1的第一端接收供应电压OVDD,第二端电性连接晶体管T4的第一端。晶体管T1的栅极端接收另一扫描信号EM。晶体管T7的第一端电性连接晶体管T4的第二端,而晶体管T7的栅极端接收扫描信号EM。发光二极管102包含阳极端及阴极端。阳极端电性连接晶体管T7的第二端,阴极端接收另一供应电压OVSS。电容C电性连接于晶体管T4的第一端与栅极端之间。
像素驱动电路10的操作请一并参考图2、图3A、图3B。图2为像素驱动电路10的信号示意图。图3A及图3B为对应图2所示出像素驱动电路10于不同操作方式示意图。如图2所示,在期间D1,扫描信号S自高电压电平改变为低电压电平,扫描信号EM自低电压电平改变为高电压电平。如图3A所示,此时晶体管T1与晶体管T7为关断状态,而晶体管T3与晶体管T5为导通状态。晶体管T4的栅极端(A点)放电至VREF。晶体管T4的第一端(B点)于前一阶段为具有供应电压OVDD的高电位,在期间D1则放电至数据信号DATA与晶体管T2临界电压的绝对值Vth_T2的和(亦即DATA+|Vth_T2|)。
接着如图2所示,在期间D2,扫描信号S自低电压电平改变为高电压电平,扫描信号EM自高电压电平改变为低电压电平。如图3B所示,此时晶体管T3与晶体管T5为关断状态,而晶体管T1与晶体管T7为导通状态。晶体管T4的栅极端(A点)变成浮接状态,晶体管T4的第一端(B点)充电到供应电压OVDD的电压值,借此B点电压变动量将直接反映在A点上。发光二极管102根据流经晶体管T1、T4、T7的驱动电流I发光。
举例而言,B点电压变动量例如为(OVDD-DATA-|Vth_T2|),因此A点在期间D2具有(VREF+OVDD-DATA-|Vth_T2|)。此时晶体管T1的第一端(B点)电位为OVDD,栅极端(A点)电位为VREF+OVDD-DATA-|Vth_T2|。电容C于期间D2维持B点与A点的电压差。故驱动电流符合:I=(1/2)k(DATA-VREF)2。应理解,驱动电流一般与供应电压以及驱动晶体管的临界电压值有关,而经由前述实施例的设计,在驱动电流中消除了供应电压及驱动晶体管临界电压值的影响。如此一来,可确保驱动电流不受制程偏异及供应电压变化的影响,借此可提供稳定的驱动电流,提高显示品质。
在图1、图3A、图3B示出的实施例中,晶体管T2与晶体管T4为同类型晶体管,较佳具有相同的临界电压值(亦即Vth_T2=Vth_T4),借此同一像素内的驱动晶体管具有均匀的临界电压值,以于期间D1、D2提供操作稳定性。进一步而言,当晶体管T1~T5、T7为同类型晶体管(例如P型晶体管)时,扫描信号S与扫描信号EM的波型大体上反相,两者形成互补的信号。相较于现有技术扫描信号的数量减少,借此可简化电路设计以减少电路布局面积。
此外,于一实施例,像素驱动电路还包含晶体管T6。晶体管T6可以例如为薄膜晶体管,包含第一端、第二端、栅极端。如图3A所示,晶体管T6的第一端电性连接该晶体管T5的第二端,用以接收第二电压信号(VREF),第二端电性连接发光二极管102的阳极端。晶体管T6的栅极端用以接收扫描信号S。如图2及图3A,在期间D1,像素驱动电路10根据扫描信号S导通晶体管T6并重置发光二极管102的阳极端。如图3B所示,在期间D2,晶体管T6则为关断状态。借此,在期间D1将发光二极管102的阳极端拉到一个低电位(VREF),确保发光二极管102在期间D1不发光。于一实施例,参考信号VREF小于供应电压OVSS与发光二极管102导通电压之和,参考信号VREF的电平例如可将设为等于供应电压OVSS,但不限于此。
请参考图4及图5,图4及图5为本发明的另一实施例像素驱动电路10A的电路示意图。其中晶体管元电的连接关系大体上相似。值得一提的是,与前述实施例的差异在于,图4所示出的像素驱动电路10A与图5所示出的像素驱动电路10B具有单一扫描信号。请先看到图4,如图4所示,晶体管T1、T3、T5、T7的栅极端均接收扫描信号S,于另一实施例中,晶体管T6的栅极端也接收扫描信号S。详言之,晶体管T1与晶体管T7为同类型晶体管(例如N型晶体管)。晶体管T3与晶体管T5为同类型晶体管,与晶体管T1具有不同类型(例如P型晶体管)时,扫描信号整合为相同的扫描信号源。借此进一步简化电路设计,减少电路布局面积。于另一实施例,可采用晶体管T1、T7的栅极端所接收的扫描信号与晶体管T3、T5的栅极端所接收的扫描信号彼此独立,但两扫描信号输出波型大体上同相。
如图5所示,于又一实施例中,晶体管T1、T3、T5、T7的栅极端均接收扫描信号EM,另外,晶体管T6的栅极端也接收扫描信号EM。详言之,晶体管T1与晶体管T7为P型晶体管,而晶体管T3与晶体管T5为N型晶体管,扫描信号整合为相同的扫描信号源。借此进一步简化电路设计,减少电路布局面积。于另一实施例,可采用晶体管T1、T7的栅极端所接收的扫描信号与晶体管T3、T5的栅极端所接收的扫描信号彼此独立,但两扫描信号输出波型大体上同相。经由上述电路设计可减少电路布局面积,且在操作过程不会产生直流静态电流路径,可减少功率消耗。
图6为像素驱动电路10C的另一实施例示意图。如图6所示,像素驱动电路10C包含晶体管T1~T5及晶体管T7、电容C,以及发光二极管102。晶体管T4透过其栅极端接收数据信号DATA。晶体管T2的第一端电性连接于晶体管T4的第一端,而栅极端则连接晶体管T2的第二端。晶体管T3的第一端接收第一电压信号,第二端连接晶体管T2的第二端。晶体管T3的栅极端接收扫描信号S,并根据扫描信号S导通晶体管T3。在此实施例,第一电压信号为参考信号VREF,且第二电压信号为数据信号DATA,数据信号DATA的电压电平小于参考信号VREF的电压电平。晶体管T5的第一端电性连接晶体管T4的栅极端,第二端接收第二电压信号(DATA)。晶体管T5的栅极端接收扫描信号S,并根据扫描信号S导通晶体管T5。晶体管T1的第一端接收供应电压OVDD,第二端电性连接晶体管T4的第一端。晶体管T1的栅极端接收另一扫描信号EM。晶体管T7的第一端电性连接晶体管T4的第二端,而晶体管T7的栅极端接收扫描信号EM。发光二极管102包含阳极端及阴极端。阳极端电性连接晶体管T7的第二端,阴极端接收另一供应电压OVSS。电容电性连接于晶体管T4的第一端与栅极端之间。
如上述,数据信号DATA的电压电平小于参考信号VREF的电压电平,举例而言,此实施例中数据信号DATA的电压电平可设定为负值。类似地,采用如图2所示的信号操作,在期间D1,扫描信号S自高电压电平改变为低电压电平,扫描信号EM自低电压电平改变为高电压电平。在期间D1,晶体管T1与晶体管T7为关断状态,而晶体管T3与晶体管T5为导通状态。晶体管T4的栅极端(A点)放电至数据信号DATA。晶体管T4的第一端(B点)于前一阶段为具有供应电压OVDD的高电位,在期间D1则放电至参考信号与晶体管T2临界电压的绝对值Vth_T2的和(亦即VREF+|Vth_T2|)。
接着在期间D2,扫描信号S自低电压电平改变为高电压电平,扫描信号EM自高电压电平改变为低电压电平。在期间D2,晶体管T3与晶体管T5为关断状态,而晶体管T1与晶体管T7为导通状态。晶体管T4的栅极端(A点)变成浮接状态,晶体管T4的第一端(B点)充电到供应电压OVDD的电压值,借此B点电压变动量将直接反映在A点上。发光二极管102根据流经晶体管T1、T4、T7的驱动电流发光。
举例而言,B点电压变动量例如为(OVDD-VREF-|Vth_T2|),因此A点在期间D2具有(DATA+OVDD-VREF-|Vth_T2|)。此时晶体管T1的第一端(B点)电位为OVDD,栅极端(A点)电位为DATA+OVDD-VREF-|Vth_T2|。电容C于期间D2维持B点与A点的电压差。故驱动电流符合:I=(1/2)k(VREF-DATA)2。应理解,驱动电流一般与供应电压以及驱动晶体管的临界电压值有关,而经由前述实施例的设计,在驱动电流中消除了供应电压及驱动晶体管临界电压值的影响。如此一来,可确保驱动电流不受制程偏异及供应电压变化的影响,借此可提供稳定的驱动电流,提高显示品质。
在图6示出的实施例中,晶体管T1与晶体管T2为同类型晶体管,较佳具有相同的临界电压值(亦即Vth_T2=Vth_T4),借此同一像素内的驱动晶体管具有均匀的临界电压值,以于期间D1、D2提供操作稳定性。进一步而言,当晶体管T1~T5、T7为同类型晶体管(例如P型晶体管)时,扫描信号S与扫描信号EM的波型大体上反相,两者形成互补的信号。相较于现有技术扫描信号的数量减少,借此可简化电路设计以减少电路布局面积。
此外,于一实施例,像素驱动电路还包含晶体管T6。晶体管T6包含第一端、第二端、栅极端。如图6所示,晶体管T6的第一端电性连接该晶体管T3的第一端,用以接收第一电压信号(VREF),第二端电性连接发光二极管102的阳极端。晶体管T6的栅极端用以接收扫描信号S。在期间D1,像素驱动电路10C根据扫描信号S导通晶体管T6并重置发光二极管102的阳极端。在期间D2,晶体管T6则为关断状态。借此,在期间D1将发光二极管102的阳极端拉到一个低电位(VREF),确保发光二极管102在期间D1不发光。于一实施例,参考信号VREF小于OVSS与发光二极管导通电压之和,例如可将设为OVSS,但不限于此。
图7及图8为像素驱动电路10D及像素驱动电路10E具有单一扫描信号的不同实施例示意图。与图6实施例的差异在于,图7所示出的像素驱动电路10D与图8所示出的像素驱动电路10E具有单一扫描信号。如图7所示,晶体管T1、T3、T5、T7的栅极端均接收扫描信号S,另外,晶体管T6的栅极端也接收扫描信号S。详言之,晶体管T1与晶体管T7为同类型晶体管(例如N型晶体管)。晶体管T3与晶体管T5为同类型晶体管且与晶体管T1具有不同类型(例如P型晶体管)时,扫描信号整合为相同的扫描信号源。借此进一步简化电路设计,减少电路布局面积。于另一实施例,可采用晶体管T1、T7的栅极端所接收的扫描信号与晶体管T3、T5的栅极端所接收的扫描信号彼此独立,但两扫描信号输出波型大体上同相。
如图8所示,晶体管T1、T3、T5、T7的栅极端均接收扫描信号EM,另外,晶体管T6的栅极端也接收扫描信号EM。详言之,晶体管T1与晶体管T7为P型晶体管,而晶体管T3与晶体管T5为N型晶体管,扫描信号整合为相同的扫描信号源。借此进一步简化电路设计,减少电路布局面积。于另一实施例,可采用晶体管T1、T7的栅极端所接收的扫描信号与晶体管T3、T5的栅极端所接收的扫描信号彼此独立,但两扫描信号输出波型大体上同相。经由上述电路设计可减少电路布局面积,且在操作过程不会产生直流静态电流路径,可减少功率消耗。
本发明已由上述相关实施例加以描述,然而上述实施例仅为实施本发明的范例。必需指出的是,已揭露的实施例并未限制本发明的范围。相反地,包含于申请专利范围的精神及范围的修改及均等设置均包含于本发明的范围内。
Claims (4)
1.一种像素驱动电路,包含:
一第一晶体管,包含:
一第一端;
一第二端;
一栅极端;
一第二晶体管,包含:
一第一端,电性连接于该第一晶体管的该第一端;
一第二端;
一栅极端,连接该第二晶体管的该第二端;
一第三晶体管,包含:
一第一端,接收一数据信号;
一第二端,连接该第二晶体管的该第二端;
一栅极端,接收一第一扫描信号,并根据该第一扫描信号导通该第三晶体管,以进行数据写入;
一第四晶体管,包含:
一第一端,电性连接该第一晶体管的该栅极端;
一第二端,接收一第二电压信号;
一栅极端,接收该第一扫描信号,并根据该第一扫描信号导通该第四晶体管,以重置该第一晶体管的栅极端;
一第五晶体管,包含:
一第一端,用以接收一第一供应电压;
一第二端,电性连接该第一晶体管的该第一端;
一栅极端,用以接收一第二扫描信号;
一第六晶体管,包含:
一第一端,电性连接该第一晶体管的该第二端;
一第二端;
一栅极端,用以接收该第二扫描信号;
一发光二极管,包含:
一阳极端电性连接该第六晶体管的该第二端;
一阴极端接收一第二供应电压;以及
一电容,电性连接于该第一晶体管的该第一端与该栅极端之间,
其中该第二电压信号为一参考信号,该数据信号的电压电平大于该参考信号的电压电平,
该像素驱动电路还包含一第七晶体管,该第七晶体管包含:
一第一端;
一第二端,电性连接该发光二极管的该阳极端;
一栅极端,用以接收该第一扫描信号,根据该第一扫描信号导通该第七晶体管并重置该发光二极管的该阳极端,
其中该第一扫描信号与该第二扫描信号于一补偿期间互为反相。
2.如权利要求1所述的像素驱动电路,其中,该第七晶体管的第一端电性连接该第四晶体管的该第二端,用以接收该第二电压信号。
3.如权利要求1所述的像素驱动电路,其中该第一晶体管与该第二晶体管为同类型晶体管。
4.如权利要求1所述的像素驱动电路,其中当该第五晶体管与该第六晶体管为关断状态时,该第三晶体管与该第四晶体管为导通状态。
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TWI652665B (zh) | 2019-03-01 |
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