CN108550529B - 一种高压vdmos器件的制造方法 - Google Patents
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Abstract
本发明涉及一种高压VDMOS器件的制造方法,其特征在于所述方法通过在正面工艺前进行背面注入,对背面进行掺杂,并生长Si3N4对圆片背面进行保护,然后进行圆片正面工艺,从而提高背面掺杂浓度,降低接触电阻,得到更低的器件二极管正向压降和导通电阻。
Description
技术领域
本发明涉及一种高压VDMOS器件的制造方法。属于集成电路或分立器件制造技术领域。
背景技术
在使用掺锑衬底的高压VDMOS器件制造工艺过程中,背面接触电阻一直是影响器件二极管正向压降和导通电阻的重要影响因素。由于掺锑衬底掺杂浓度不够高,一般衬底电阻率在0.008-0.02ohm.cm即掺杂浓度在6.33e18/cm3-1.22e18/cm3,如衬底直接和背面金属接触,不能形成很好的欧姆接触,常规工艺是在正面工艺完成后,进行减薄,然后进行背面注入,进行退火,再生长背面金属的方法来增加衬底背面浓度,降低器件背面接触电阻,以达到低的器件二极管正向压降和导通电阻。但这样的背面注入工艺是在正面工艺完成之后才作业,由于正面金属已经形成,因此背面注入后的退火无法使用超过合金温度的工艺温度条件,一般背面注入退火温度在400℃到450℃之间,这样的退火温度杂质激活率很低,对大剂量背面注入引入的缺陷修复也不充分,导致器件二极管正向压降偏高,二极管损耗偏大。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种高压VDMOS器件的制造方法,克服常规掺锑衬底高压VDMOS背面工艺的缺点,降低器件二极管正向压降和工作损耗。
本发明解决上述问题所采用的技术方案为:一种高压VDMOS器件的制造方法,所述方法通过在正面工艺前进行背面注入,对背面进行掺杂,并生长Si3N4对圆片背面进行保护,然后进行圆片正面工艺,从而提高背面掺杂浓度,降低接触电阻,得到更低的器件二极管正向压降和导通电阻。
优选地,所述方法主要包括以下步骤:
第一步、选择合适厚度的外延圆片;
第二步、对圆片背面进行元素注入,注入元素可以是硼,也可以是磷,量在30Kev到160Kev之间,剂量在1E14到1E16之间。
第三步、在圆片正面和背面生长一层SiO2层作为一个缓冲应力层;
第四步、在圆片正面和背面的SiO2层表面上生长Si3N4层对圆片背面进行保护;
第五步、去除圆片正面的Si3N4层,正面停留在SiO2层;
第六步、去除圆片正面的SiO2层,圆片背面生长的SiO2和Si3N4完全保留;
第七步、完成圆片的正面工艺;
第八步、去除圆片背面的Si3N4层和SiO2层;
第九步、在圆片背面生长背面金属。
优选地,对于常规厚度的外延圆片,减薄厚度厚于最终硅片厚度;或直接采购接近最终厚度的外延圆片。
优选地,背面注入元素为硼或磷,注入能量在30Kev到160Kev之间,剂量在1E14到1E16之间。
优选地,使用干法刻蚀工艺去除圆片正面的Si3N4层。
优选地,使用湿法腐蚀工艺去除圆片正面的SiO2层。
与现有技术相比,本发明的优点在于:
1、在正面工艺前进行背面元素注入,并利用正面工艺中的热过程进行背面元素的扩散,背面元素扩散深度深,注入引入的晶格缺陷修复效果更好,降低了器件背面的接触电阻,降低器件二极管正向压降和导通电阻。
2、圆片背面增加了LPSiN(Si3N4),降低了高温炉管工艺过程中圆片背面外扩散造成的圆片表面浓度增加的影响,提高了器件圆片良率。
附图说明
图1为本发明高压VDMOS的工艺流程。
图2为本发明常规掺锑衬底高压VDMOS的工艺流程。
图3-图12为本发明流程的具体过程说明。
具体实施方式
下面结合具体的实例来进一步说明实现本发明提出的一种无铝下CVD肖特基二极管芯片及制造工艺。并且需要说明的是,附图均采用非常简化的形式且均使用非精确的比例,仅用以方便、明晰地辅助说明本发明的结构及实现的方式。
参见图3,本发明涉及一种高压VDMOS器件的制造方法,主要是通过在正面工艺前进行背面注入,对背面进行掺杂,并生长LPSiN(Si3N4)对圆片背面进行保护,然后进行圆片正面工艺,从而提高背面掺杂浓度,降低接触电阻,得到更低的器件二极管正向压降和导通电阻。具体包含以下几个步骤:
如图4所示,第1步,对于常规厚度的外延圆片,使用背面减薄工艺进行硅片减薄,减薄厚度稍厚于最终硅片厚度;也可以直接采购接近最终厚度的外延圆片,这样就可以减少减薄的工艺时间或者直接省略减薄步骤,更能够降低成本。
如图5所示,第2步,使用离子注入机,对圆片背面进行注入,注入元素可以是硼,也可以是磷,增加衬底溶度,减小接触电阻,注入能量在30Kev到160Kev之间,剂量在1E14到1E16之间。
如图6所示,第3步,使用LPTEOS工艺,在圆片正面和背面生长一层SiO2层,厚度在到之间,SiO2层作为一个缓冲应力层,由于后续生长的Si3N4膜应力较大,会对圆片本身造成影响,损坏圆片表面,因此先用一层SiO2进行缓冲保护。
如图7所示,第4步,使用LPSiN工艺,在圆片正面和背面的SiO2层表面上生长Si3N4层,厚度在到之间,Si3N4可以降低后续高温炉管工艺过程中圆片背面外扩散造成的圆片表面浓度增加的影响,提高了器件圆片良率。
如图8所示,第5步,使用干法刻蚀工艺去除圆片正面的Si3N4层,正面停留在SiO2层。
如图9所示,第6步,使用湿法腐蚀工艺去除圆片正面的SiO2层,完成此工艺后,圆片背面生长的SiO2和Si3N4完全保留,而圆片正面的生长的SiO2和Si3N4完全去除;
如图10所示,第7步,完成圆片的正面工艺,按圆片原来的正常工艺流程完成整个正面工艺,一直做到正面金属或钝化层(如有);
如图11所示,第8步,使用干法刻蚀工艺去除圆片背面的LPSiN(Si3N4)和LPTEOS(SiO2);
如图12所示,第9步,在圆片背面生长背面金属。
除上述实施例外,本发明还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本发明权利要求的保护范围之内。
Claims (6)
1.一种高压VDMOS器件的制造方法,其特征在于所述方法通过在正面工艺前进行背面注入,对背面进行掺杂,并生长Si3N4对圆片背面进行保护,然后进行圆片正面工艺,从而提高背面掺杂浓度,降低接触电阻,得到更低的器件二极管正向压降和导通电阻;所述方法主要包括以下步骤:
第一步、选择合适厚度的外延圆片;
第二步、对圆片背面进行元素注入,注入元素可以是硼,也可以是磷,量在30Kev到160Kev之间,剂量在1E14到1E16之间;
第三步、在圆片正面和背面生长一层SiO2层作为一个缓冲应力层;
第四步、在圆片正面和背面的SiO2层表面上生长Si3N4层对圆片背面进行保护;
第五步、去除圆片正面的Si3N4层,正面停留在SiO2层;
第六步、去除圆片正面的SiO2层,圆片背面生长的SiO2和Si3N4完全保留;
第七步、完成圆片的正面工艺,并利用正面工艺中的热过程进行背面元素的扩散;
第八步、去除圆片背面的Si3N4层和SiO2层;
第九步、在圆片背面生长背面金属。
2.根据权利要求1所述的一种高压VDMOS器件的制造方法,其特征在于对于常规厚度的外延圆片,减薄厚度厚于最终硅片厚度;或直接采购接近最终厚度的外延圆片。
3.根据权利要求1所述的一种高压VDMOS器件的制造方法,其特征在于使用LPTEOS工艺形成SiO2层,厚度在400Å到1000Å之间。
4.根据权利要求1所述的一种高压VDMOS器件的制造方法,其特征在于使用LPSiN工艺形成Si3N4层,厚度在1000Å到2000Å之间。
5.根据权利要求1所述的一种高压VDMOS器件的制造方法,其特征在于使用干法刻蚀工艺去除圆片正面的Si3N4层。
6.根据权利要求1所述的一种高压VDMOS器件的制造方法,其特征在于使用湿法腐蚀工艺去除圆片正面的SiO2层。
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