CN108540124A - A kind of level shifting circuit - Google Patents
A kind of level shifting circuit Download PDFInfo
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- CN108540124A CN108540124A CN201810338710.3A CN201810338710A CN108540124A CN 108540124 A CN108540124 A CN 108540124A CN 201810338710 A CN201810338710 A CN 201810338710A CN 108540124 A CN108540124 A CN 108540124A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018557—Coupling arrangements; Impedance matching circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
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- General Engineering & Computer Science (AREA)
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Abstract
A kind of level shifting circuit belongs to electronic circuit technology field.Including level conversion unit, the first timing control unit and the second timing control unit, on the one hand input signal connects the input terminal of the first timing control unit, the input terminal of the second timing control unit is on the one hand connected after reverse phase；Two timing control units are used for controlling the sequential of input signal, and output end is separately connected two input terminals of level conversion unit；Level conversion unit is used for obtaining being converted to low-voltage signal the first output signal and the second output signal of high-voltage signal.Level shifting circuit provided by the invention improves the driving capability of circuit, has the advantages that high conversion rate and simple in structure, while ensure that level conversion output is stablized, and the high voltage level conversion of high speed operation is realized in the case of no Degradation Reliability.
Description
Technical field
The invention belongs to electronic circuit technology field, it is related to a kind of level shifting circuit more particularly to one kind is suitable for height
The high voltage level conversion circuit of speed operation.
Background technology
Level shifting circuit includes high voltage level conversion circuit and low voltage level conversion circuit, wherein high voltage level conversion electricity
Low-voltage control signal is converted to high voltage control signal by road, realizes control of the low voltage logic to high-voltage power output stage.In general, root
According to the output polar difference of high voltage control signal, level shifting circuit can be divided into negative pressure level shifting circuit and positive pressure level conversion
Circuit.Typical level shifting circuit receives input signal by a pair of transistor, however, when incoming signal level declines to a great extent
When, the driving capability of driving tube will be deteriorated, and the delay of circuit can increase.In addition, extreme voltage decline can be further
Cause the mechanical periodicity of undesirable output signal, in some instances it may even be possible to because input transistors can not be by extremely low applied signal voltage
Conducting, and cause conversion circuit that can not work.And traditional level shifting circuit is due to the use of excessive high-breakdown-voltage pipe,
Cause conversion speed slow.
Invention content
Place against the above deficiency, the present invention provide a kind of level shifting circuit, can solve traditional level shifting circuit
Middle driving capability deficiency and the slower disadvantage of conversion speed, high speed operation is realized in the case of no Degradation Reliability.
The technical scheme is that：
A kind of level shifting circuit, including level conversion unit 110, the first timing control unit 100 and the second sequential control
Unit 120 processed,
The level conversion unit 110 includes phase inverter INV1, third NMOS tube MN3, the 4th NMOS tube MN4, the 5th
NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, third PMOS tube MP3, the 4th PMOS tube
MP4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the first capacitance C1 and second
Capacitance C2,
When the source electrode of third PMOS tube MP3 connects described first as the first input end of the level conversion unit 110
The output end of sequence control unit 100, grid connect the grid of the 4th PMOS tube MP4 and are grounded VSS, drain electrode connection the 4th
The grid of NMOS tube MN4 and the 6th NMOS tube MN6 and by being grounded VSS after the first capacitance C1；
When the source electrode of 4th PMOS tube MP4 connects described second as the second input terminal of the level conversion unit 110
The output end of sequence control unit 120, the grid of drain electrode connection third NMOS tube MN3 and the 5th NMOS tube MN5 simultaneously pass through second
It is grounded VSS after capacitance C2；
The source electrode of third NMOS tube MN3 connects the drain electrode of the 5th NMOS tube MN5, the 6th PMOS tube MP6 of drain electrode connection, the
The grid of eight PMOS tube MP8 and the 8th NMOS tube MN8 and as first node；
The source electrode of 4th NMOS tube NM4 connects the drain electrode of the 6th NMOS tube MN6, the 5th PMOS tube MP5 of drain electrode connection, the
The grid of seven PMOS tube MP7 and the 7th NMOS tube MN7 and as second node；
The drain electrode of 6th PMOS tube MP6 connects the second node, and the drain electrode of the 5th PMOS tube MP5 connects the first segment
Point；
The drain electrode of the 7th PMOS tube MP7 of drain electrode connection of 7th NMOS tube MN7 and as the of the level shifting circuit
One output end, the drain electrode of the 8th PMOS tube MP8 of drain electrode connection of the 8th NMOS tube MN8 and as the of the level shifting circuit
Two output ends；
The source electrode ground connection of 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7 and the 8th NMOS tube MN8；The
The source electrode connection high power supply voltage of five PMOS tube MP5, the 6th PMOS tube MP6, the 7th PMOS tube MP7 and the 8th PMOS tube MP8
VDDH；
The input terminal of the level shifting circuit connects the input terminal of first timing control unit 100 and the reverse phase
The input terminal of device INV1, the output end of the phase inverter INV1 connect the input terminal of second timing control unit 120.
Specifically, first timing control unit 100 includes the first NMOS tube MN1 and the first PMOS tube MP1, first
The gate interconnection of NMOS tube MN1 and the first PMOS tube MP1 and as the input terminal of first timing control unit 100, leakage
Pole also interconnects and as the output end of the first timing control monomer 100, and the source electrode of the first PMOS tube MP1 connects low power supply electricity
VDD, the source electrode of the first NMOS tube MN1 is pressed to be grounded VSS；
Second timing control unit 120 includes the second NMOS tube MN2 and the second PMOS tube MP2, the second NMOS tube MN2
With the gate interconnection of the second PMOS tube MP2 and as the input terminal of second timing control unit 120, drain electrode also interconnects simultaneously
As the output end of second timing control unit 120, the source electrode connection low supply voltage VDD of the second PMOS tube MP2, second
The source electrode of NMOS tube MN2 is grounded VSS.
Specifically, the power rail of the phase inverter INV1 is low supply voltage VDD to ground level VSS.
Specifically, being additionally provided with the 9th PMOS tube between the drain electrode and the first node of the 5th PMOS tube MP5
The source electrode of MP9, the 9th PMOS tube MP9 connect the drain electrode of the 5th PMOS tube MP5, and drain electrode connects the first node, grid
Connect the drain electrode of the 4th PMOS tube MP4；
It is additionally provided with the tenth PMOS tube MP10 between the drain electrode and the second node of the 6th PMOS tube MP6, the tenth
The source electrode of PMOS tube MP10 connects the drain electrode of the 6th PMOS tube MP6, and drain electrode connects the second node, and grid connects third
The drain electrode of PMOS tube MP3.
Specifically, the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th NMOS tube MN4,
Five NMOS tube MN5, the 6th NMOS tube MN6, the first PMOS tube MP1, the second PMOS tube MP2, third PMOS tube MP3 and the 4th PMOS
Pipe MP4 is low breakdown voltage pipe, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 5th PMOS tube MP5, the 6th PMOS tube
MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9 and the tenth PMOS tube MP10 are high-breakdown-voltage pipe.
Beneficial effects of the present invention are：The driving capability of circuit is improved, with high conversion rate and simple in structure excellent
Point, while ensure that level conversion output is stablized, the high voltage level of high speed operation is realized in the case of no Degradation Reliability
Conversion.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram for level shifting circuit that the embodiment of the present invention one proposes.
Fig. 2 is the figure of a kind of level shifting circuit time sequential routine that the embodiment of the present invention one proposes.
Fig. 3 is a kind of structural schematic diagram for level shifting circuit that the embodiment of the present invention two proposes.
Specific implementation mode
With reference to the accompanying drawings and detailed description, detailed description of the present invention technical solution.
Level shifting circuit proposed by the present invention, for low-voltage control signal to be converted to high voltage control signal, including electricity
Flat converting unit 110 and lotus root are connected to the first timing control unit 100 and the second timing control unit of level conversion unit
120, the present invention includes high-breakdown-voltage PMOS transistor, low breakdown voltage PMOS transistor, high-breakdown-voltage using device
NMOS transistor, low breakdown voltage NMOS transistor.
Embodiment one
As shown in figure 3, level conversion unit 110 include phase inverter INV1, third NMOS tube MN3, the 4th NMOS tube MN4,
5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, third PMOS tube MP3, the 4th
PMOS tube MP4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the first capacitance C1
With the source electrode of the second capacitance C2, third PMOS tube MP3 the first sequential control is connected as the first input end of level conversion unit 110
The output end of unit 100 processed, grid connect the grid of the 4th PMOS tube MP4 and are grounded VSS, drain electrode the 4th NMOS tube of connection
The grid of MN4 and the 6th NMOS tube MN6 and by being grounded VSS after the first capacitance C1；The source electrode of 4th PMOS tube MP4 is as level
Second input terminal of converting unit 110 connects the output end of the second timing control unit 120, drain electrode connection third NMOS tube
The grid of MN3 and the 5th NMOS tube MN5 and by being grounded VSS after the second capacitance C2；The source electrode connection the 5th of third NMOS tube MN3
The grid of the drain electrode of NMOS tube MN5, the 6th PMOS tube MP6 of drain electrode connection, the 8th PMOS tube MP8 and the 8th NMOS tube MN8 are simultaneously
As first node；The source electrode of 4th NMOS tube NM4 connects the drain electrode of the 6th NMOS tube MN6, drain electrode the 5th PMOS tube of connection
MP5, the grid of the 7th PMOS tube MP7 and the 7th NMOS tube MN7 and as second node；The drain electrode of 6th PMOS tube MP6 connects
The drain electrode of second node, the 5th PMOS tube MP5 connects first node；The drain electrode of 7th NMOS tube MN7 connects the 7th PMOS tube MP7
Drain electrode and as the first output end of level shifting circuit export the first output signal po, the 8th NMOS tube MN8 drain electrode connect
It connects the drain electrode of the 8th PMOS tube MP8 and exports the second output signal no as the second output terminal of level shifting circuit；5th
The source electrode ground connection of NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7 and the 8th NMOS tube MN8；5th PMOS tube MP5,
The source electrode of 6th PMOS tube MP6, the 7th PMOS tube MP7 and the 8th PMOS tube MP8 connect high power supply voltage VDDH.Level conversion electricity
The input terminal on road connects the input terminal of the input terminal and phase inverter INV1 of the first timing control unit 100, and phase inverter INV1's is defeated
Outlet connects the input terminal of the second timing control unit 120.
The first input end of level conversion unit 110 and the second input terminal are used for receiving 100 He of the first timing control unit
The output signal of second timing control unit 120.The input terminal of the first timing control unit of input signal pi connections 100, and lead to
Become rp input signal ni the second timing control units of connection after phase inverter INV1 reverse phases in over level converting unit 110
120 input terminal.First timing control unit 100 and the second timing control unit 120 are used for controlling input signal pi and reverse phase
The sequential of input signal ni, as shown in figure 3, the first timing control unit 100 includes the first NMOS tube MN1 and the in the present embodiment
The gate interconnection of one PMOS tube MP1, the first NMOS tube MN1 and the first PMOS tube MP1 and as the first timing control unit 100
Input terminal, drain electrode also interconnect and as the output ends of the first timing control monomer 100, and the source electrode of the first PMOS tube MP1 connects
The source electrode of low supply voltage VDD, the first NMOS tube MN1 are grounded VSS；Second timing control unit 120 includes the second NMOS tube MN2
With the gate interconnection of the second PMOS tube MP2, the second NMOS tube MN2 and the second PMOS tube MP2 and as the second timing control unit
120 input terminal, drain electrode also interconnect and as the output end of the second timing control unit 120, the source electrodes of the second PMOS tube MP2
The source electrode for connecting low supply voltage VDD, the second NMOS tube MN2 is grounded VSS.
Wherein the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS
Pipe MN5, the 6th NMOS tube MN6, the first PMOS tube MP1, the second PMOS tube MP2, third PMOS tube MP3 and the 4th PMOS tube MP4
For low breakdown voltage pipe, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the 7th
PMOS tube MP7 and the 8th PMOS tube MP8 is high-breakdown-voltage pipe.
Low supply voltage VDD is that the low level of whole system work operates voltage, and high power supply voltage VDDH is whole system
The high level of work operates voltage, and ground potential VSS is the ground potential of whole system.Pass through low breakdown voltage PMOS in the present embodiment
The third PMOS tube MP3 and the 4th PMOS tube MP4 of transistor come reinforce level conversion unit 110 input pole driving capability.
The clock signal figure being illustrated in figure 2 in the present embodiment.Situation (1)：When input signal pi and rp input signal
Ni level is respectively VSS and VDD and VDDH level when being VDD, the first output signal po that level conversion unit 110 exports and the
Two output signal no are respectively VDD and VSS.Situation (2)：When input signal pi and rp input signal ni level are respectively VDD
When with VSS and VDDH level being VDD, the first output signal po that level conversion unit 110 exports and the second output signal no points
It Wei not VSS and VDD.Situation (3) is respectively VDD and VSS and VDDH level as input signal pi and rp input signal ni level
For high tension voltage when, level conversion unit 110 export the first output signal po and the second output signal no be VSS and VDDH.
In actual use, the voltage value of high power supply voltage VDDH will be generally above the voltage value of low supply voltage VDD, lead to
It crosses and the low supply voltage VDD of input is converted into high power supply voltage VDDH achievees the purpose that conversion from from low pressure to high pressure；And
VDDH is to shield output when external voltage VDDH is fluctuated equal to the case where VDD, and the output of level shifting circuit is electric at this time
Pressure is not as effective output.
The operation principle of the present embodiment is：When input signal pi and anti-phase input type ni level are respectively VDD and VSS,
Third PMOS tube MP3 ends at this time, the 4th PMOS tube MP4 conducting, after the second capacitance C2 voltage stabilizings, the second capacitance C2 and the
Tie point, that is, node h2 of four PMOS tube MP4 drain electrodes becomes high level i.e. low supply voltage VDD, later third NMOS tube MN3 and
5th NMOS tube MN5 conductings so that the gate voltage of the 6th PMOS tube MP6 is ground potential VSS, and the 6th PMOS tube MP6 is connected, first
Capacitance C1 and the level of tie point, that is, node h1 of third PMOS tube MP3 drain electrodes ensure that the 4th NMOS by Coupled Feedback acceleration
The cut-off of pipe MN4 and the 6th NMOS tube MN6 make the 8th PMOS tube MP8 conductings, and final first output signal po is low level VSS,
Second output signal no is high power supply voltage VDDH.Node h1, h2 are by controlling the 7th PMOS tube MP7, the 8th PMOS tube MP8
Grid protects output nmos transistor, prevents damage of the high pressure to low breakdown metal-oxide-semiconductor.First timing control unit
100 and second timing control unit 120 be used for providing additional reinforcement path, level conversion unit 110 by ensureing node h1,
The voltage stabilization of h2 improves reliability, the 6th PMOS tube MP6, the 8th PMOS tube MP8 and the 5th PMOS tube MP5, the 7th PMOS
Pipe MP7 composition positive feedbacks are of coupled connections, and improve driving capability, ensure that level conversion output is stablized.
Embodiment two
Such as Fig. 1, the 9th PMOS tube is additionally provided between the drain electrode and first node of the 5th PMOS tube MP5 in the present embodiment
The source electrode of MP9, the 9th PMOS tube MP9 connect the drain electrode of the 5th PMOS tube MP5, drain electrode connection first node, grid connection
The drain electrode of 4th PMOS tube MP4；It is additionally provided with the tenth PMOS tube between the drain electrode and second node of the 6th PMOS tube MP6
The source electrode of MP10, the tenth PMOS tube MP10 connect the drain electrode of the 6th PMOS tube MP6, drain electrode connection second node, and grid connects
Connect the drain electrode of third PMOS tube MP3.
Wherein the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS
Pipe MN5, the 6th NMOS tube MN6, the first PMOS tube MP1, the second PMOS tube MP2, third PMOS tube MP3 and the 4th PMOS tube MP4
For low breakdown voltage pipe, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the 7th
PMOS tube MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9 and the tenth PMOS tube MP10 are high-breakdown-voltage pipe.
Embodiment two is constituted just compared to for embodiment one by increasing the 9th PMOS tube MP9 and the tenth PMOS tube MP10
Feedback arrangement makes conversion speed faster, but embodiment one compared to for embodiment two have simpler circuit structure.
The NMOS tube and PMOS tube that the present invention uses can be LDMOS, VDMOS and IGBT in one kind, the first capacitance C1,
Second capacitance C2 can be MOS linking capacitances, and MOS is NMOS or PMOS transistor.
To sum up, input signal pi reverse phases are obtained reverse phase by level shifting circuit provided by the invention by a phase inverter
Input signal ni, then input signal pi and anti-is controlled by the first timing control unit 100 and the second timing control unit 120 respectively
The sequential of phase input signal ni, then the first timing control unit 100 and 120 lotus root of the second timing control unit are connected to level conversion
Two input terminals of unit 110 complete the conversion from low level to high level, with traditional level using level conversion unit 110
Conversion circuit is compared, and the driving capability and reliability of circuit are improved, and has the advantages that high conversion rate, timing control unit tool
There is simpler structure, while ensure that level conversion output is stablized, realizes that high speed is grasped in the case of no Degradation Reliability
The high voltage level of work is converted.
It is understood that the present invention is not limited to the accurate configuration being illustrated above and components.Claims are not being departed from
Protection domain on the basis of, can be to method and structure above the step of sequence, details and operation make various modifications and optimization.
Claims (5)
1. a kind of level shifting circuit, which is characterized in that including level conversion unit (110), the first timing control unit (100)
With the second timing control unit (120),
The level conversion unit (110) includes phase inverter (INV1), third NMOS tube (MN3), the 4th NMOS tube (MN4),
Five NMOS tubes (MN5), the 6th NMOS tube (MN6), the 7th NMOS tube (MN7), the 8th NMOS tube (MN8), third PMOS tube
(MP3), the 4th PMOS tube (MP4), the 5th PMOS tube (MP5), the 6th PMOS tube (MP6), the 7th PMOS tube (MP7), the 8th
PMOS tube (MP8), the first capacitance (C1) and the second capacitance (C2),
When the source electrode of third PMOS tube (MP3) connects described first as the first input end of the level conversion unit (110)
The output end of sequence control unit (100), grid connect the grid of the 4th PMOS tube (MP4) and ground connection (VSS), drain electrode connection
The grid of 4th NMOS tube (MN4) and the 6th NMOS tube (MN6) is simultaneously grounded (VSS) afterwards by the first capacitance (C1)；
When the source electrode of 4th PMOS tube (MP4) connects described second as the second input terminal of the level conversion unit (110)
The grid of the output end of sequence control unit (120), drain electrode connection third NMOS tube (MN3) and the 5th NMOS tube (MN5) simultaneously leads to
It crosses the second capacitance (C2) and is grounded (VSS) afterwards；
The source electrode of third NMOS tube (MN3) connects the drain electrode of the 5th NMOS tube (MN5), the 6th PMOS tube (MP6) of connection that drains,
The grid of 8th PMOS tube (MP8) and the 8th NMOS tube (MN8) and as first node；
The source electrode of 4th NMOS tube (NM4) connects the drain electrode of the 6th NMOS tube (MN6), the 5th PMOS tube (MP5) of connection that drains,
The grid of 7th PMOS tube (MP7) and the 7th NMOS tube (MN7) and as second node；
The drain electrode of 6th PMOS tube (MP6) connects the second node, and the drain electrode of the 5th PMOS tube (MP5) connects the first segment
Point；
The drain electrode of 7th NMOS tube (MN7) connects the drain electrode of the 7th PMOS tube (MP7) and as the of the level shifting circuit
The drain electrode of one output end, the 8th NMOS tube (MN8) connects the drain electrode of the 8th PMOS tube (MP8) and as the level shifting circuit
Second output terminal；
5th NMOS tube (MN5), the 6th NMOS tube (MN6), the 7th NMOS tube (MN7) and the 8th NMOS tube (MN8) source electrode connect
Ground；5th PMOS tube (MP5), the 6th PMOS tube (MP6), the 7th PMOS tube (MP7) are connected with the source electrode of the 8th PMOS tube (MP8)
High power supply voltage (VDDH)；
The input terminal of the level shifting circuit connects the input terminal of first timing control unit (100) and the phase inverter
(INV1) input terminal, the output end of the phase inverter (INV1) connect the input terminal of second timing control unit (120).
2. level shifting circuit according to claim 1, which is characterized in that
First timing control unit (100) includes the first NMOS tube (MN1) and the first PMOS tube (MP1), the first NMOS tube
(MN1) and the gate interconnection of the first PMOS tube (MP1) and as the input terminal of first timing control unit (100), leakage
Pole also interconnects and as the output end of the first timing control monomer (100), and the source electrode of the first PMOS tube (MP1) connects low electricity
Source voltage (VDD), the source electrode ground connection (VSS) of the first NMOS tube (MN1)；
Second timing control unit (120) includes the second NMOS tube (MN2) and the second PMOS tube (MP2), the second NMOS tube
(MN2) and the gate interconnection of the second PMOS tube (MP2) and as the input terminal of second timing control unit (120), leakage
Pole also interconnects and as the output end of second timing control unit (120), and the source electrode of the second PMOS tube (MP2) connects low electricity
Source voltage (VDD), the source electrode ground connection (VSS) of the second NMOS tube (MN2).
3. level shifting circuit according to claim 1, which is characterized in that the power rail of the phase inverter (INV1) is low
Supply voltage (VDD) arrives ground level (VSS).
4. level shifting circuit according to claim 2 or 3, which is characterized in that the drain electrode of the 5th PMOS tube (MP5)
The 9th PMOS tube (MP9) is additionally provided between the first node, the source electrode of the 9th PMOS tube (MP9) connects the 5th PMOS tube
(MP5) drain electrode, drain electrode connect the first node, and grid connects the drain electrode of the 4th PMOS tube (MP4)；
It is additionally provided with the tenth PMOS tube (MP10) between the drain electrode and the second node of 6th PMOS tube (MP6), the tenth
The source electrode of PMOS tube (MP10) connects the drain electrode of the 6th PMOS tube (MP6), and drain electrode connects the second node, grid connection
The drain electrode of third PMOS tube (MP3).
5. level shifting circuit according to claim 4, which is characterized in that first NMOS tube (MN1), the 2nd NMOS
Manage (MN2), third NMOS tube (MN3), the 4th NMOS tube (MN4), the 5th NMOS tube (MN5), the 6th NMOS tube (MN6), first
PMOS tube (MP1), the second PMOS tube (MP2), third PMOS tube (MP3) and the 4th PMOS tube (MP4) are low breakdown voltage pipe, institute
State the 7th NMOS tube (MN7), the 8th NMOS tube (MN8), the 5th PMOS tube (MP5), the 6th PMOS tube (MP6), the 7th PMOS tube
(MP7), the 8th PMOS tube (MP8), the 9th PMOS tube (MP9) and the tenth PMOS tube (MP10) are high-breakdown-voltage pipe.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810338710.3A CN108540124A (en) | 2018-04-16 | 2018-04-16 | A kind of level shifting circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810338710.3A CN108540124A (en) | 2018-04-16 | 2018-04-16 | A kind of level shifting circuit |
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| CN108540124A true CN108540124A (en) | 2018-09-14 |
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| CN201810338710.3A Pending CN108540124A (en) | 2018-04-16 | 2018-04-16 | A kind of level shifting circuit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110545096A (en) * | 2019-09-02 | 2019-12-06 | 成都锐成芯微科技股份有限公司 | Quick start circuit |
| CN110585605A (en) * | 2019-10-10 | 2019-12-20 | 中国人民解放军第四军医大学 | Laser therapeutic instrument |
| CN113131921A (en) * | 2019-12-31 | 2021-07-16 | 圣邦微电子（北京）股份有限公司 | Ultra-low power consumption high-speed dynamic level converter |
| CN114095012A (en) * | 2021-09-28 | 2022-02-25 | 荣湃半导体（上海）有限公司 | Level conversion circuit |
| WO2022048128A1 (en) * | 2020-09-02 | 2022-03-10 | 敦泰电子（深圳）有限公司 | Level shifter circuit |
| CN117318697A (en) * | 2023-09-15 | 2023-12-29 | 辰芯半导体（深圳）有限公司 | Level shift circuit and power supply device |
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| CN110545096A (en) * | 2019-09-02 | 2019-12-06 | 成都锐成芯微科技股份有限公司 | Quick start circuit |
| CN110545096B (en) * | 2019-09-02 | 2023-09-15 | 成都锐成芯微科技股份有限公司 | Quick starting circuit |
| CN110585605A (en) * | 2019-10-10 | 2019-12-20 | 中国人民解放军第四军医大学 | Laser therapeutic instrument |
| CN113131921A (en) * | 2019-12-31 | 2021-07-16 | 圣邦微电子（北京）股份有限公司 | Ultra-low power consumption high-speed dynamic level converter |
| WO2022048128A1 (en) * | 2020-09-02 | 2022-03-10 | 敦泰电子（深圳）有限公司 | Level shifter circuit |
| CN114095012A (en) * | 2021-09-28 | 2022-02-25 | 荣湃半导体（上海）有限公司 | Level conversion circuit |
| CN114095012B (en) * | 2021-09-28 | 2022-11-08 | 荣湃半导体（上海）有限公司 | Level conversion circuit |
| CN117318697A (en) * | 2023-09-15 | 2023-12-29 | 辰芯半导体（深圳）有限公司 | Level shift circuit and power supply device |
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Application publication date: 20180914 |