CN106899288A - Level shifting circuit - Google Patents
Level shifting circuit Download PDFInfo
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- CN106899288A CN106899288A CN201710092872.9A CN201710092872A CN106899288A CN 106899288 A CN106899288 A CN 106899288A CN 201710092872 A CN201710092872 A CN 201710092872A CN 106899288 A CN106899288 A CN 106899288A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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Abstract
The present invention relates to a kind of level shifting circuit, the source electrode of the first PMOS is connected with external power source, and drain electrode is connected with the source electrode of the 3rd PMOS, and grid is connected with the drain electrode of the 4th PMOS；The source electrode of the second PMOS is connected with external power source, and grid is connected with the drain electrode of the 3rd PMOS, and drain electrode is connected with the source electrode of the 4th PMOS；The drain electrode of the 3rd PMOS is connected with the source electrode of the first NMOS tube, the drain electrode of the 4th PMOS is connected with the source electrode of the second NMOS tube, the grid of the 3rd PMOS, the grid of the first NMOS tube, the grid of the grid of the second NMOS tube and the 4th PMOS is connected with phase inverter, the input signal of the grid of the grid of the second NMOS tube and the 4th PMOS is identical with the input end signal of phase inverter, the input signal of the grid of the 3rd PMOS and the grid of the first NMOS tube is opposite, the control end of latch module receives external threshold signal, first end is grounded, second end respectively with the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the 3rd PMOS and the drain electrode connection of the 4th PMOS.
Description
Technical field
The present invention relates to electronic circuit technology field, more particularly to a kind of level shifting circuit.
Background technology
In numerous semiconductor integrated circuit, circuit signal is not very stable, is disturbed or upper level electricity when receiving
During the error signal of road, next stage circuit misoperation is easily caused, such case is particularly evident in level shifting circuit.Level turns
Change circuit and low level signal is exactly transformed into high level signal, or high level signal is transformed into low level signal, when low
During the power supply power-fail of level signal, signal is unable to normal delivery, causes the reception signal of high-tension electricity source domain mistake occur, and may
Produce the problem of big electric leakage.
There is above mentioned problem in traditional level shifting circuit, when low level signal power supply power-fail, export uncertain electricity
Level values, the i.e. input state of subordinate's circuit are neither high level is nor low level, but the median for falling between, lead
Cause lower logical circuit easily to produce high current, and damage related device.
The content of the invention
Based on this, it is necessary to cause output unstable when there is instant cut-off or power down for traditional level shifting circuit
Problem, there is provided one kind can ensure that output signal is continual and steady, make the level shifting circuit of the Input-to-state stability of subordinate's circuit.
A kind of level shifting circuit, including phase inverter, level translator and the latch module being sequentially connected；
Level translator includes the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the first NMOS tube
And second NMOS tube；The source electrode of the first PMOS is connected with external power source, drain electrode and the 3rd PMOS of the first PMOS
Source electrode is connected, and the grid of the first PMOS is connected with the drain electrode of the 4th PMOS；The source electrode of the second PMOS connects with external power source
Connect, the grid of the second PMOS is connected with the drain electrode of the 3rd PMOS, the source electrode drained with the 4th PMOS of the second PMOS
Connection；The drain electrode of the 3rd PMOS is connected with the source electrode of the first NMOS tube, the grid of the 3rd PMOS, the grid of the first NMOS tube
The grid of pole, the grid of the second NMOS tube and the 4th PMOS is connected with phase inverter, the input letter of the grid of the second NMOS tube
Number and the 4th PMOS grid input signal it is identical with the input end signal of phase inverter, the grid of the 3rd PMOS it is defeated
The input signal for entering the grid of signal and the first NMOS tube is identical with inverter output signal；The drain electrode of the 4th PMOS with
The source electrode connection of the second NMOS tube, the input of phase inverter as level shifting circuit input, the source electrode of the first NMOS tube
As the output end of level shifting circuit；
The control end of latch module receives external threshold signal, the first end ground connection of latch module, the second of latch module
End drain electrode, the drain electrode of the second NMOS tube, the drain electrode of the 3rd PMOS and the leakage of the 4th PMOS respectively with the first NMOS tube
Pole connects.
Above-mentioned level shifting circuit, including phase inverter, level translator and the latch module being sequentially connected, level translator
Including the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the first NMOS tube and the second NMOS tube, latch
The control end of module receives external threshold signal, the first end ground connection of latch module, and the second end of latch module is respectively with first
The drain electrode of NMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the 3rd PMOS and the drain electrode of the 4th PMOS connection, by outer
Portion's threshold signal opens latch module, it is ensured that when instant cut-off or power down occurs in level shifting circuit, level shifting circuit
The voltage of output end is still stablized.
Brief description of the drawings
Fig. 1 is a kind of circuit theory diagrams of the level switch module of level shifting circuit；
Fig. 2 is the circuit structure diagram of level shifting circuit in one embodiment；
Fig. 3 is the circuit theory diagrams of level shifting circuit in one embodiment；
Fig. 4 is the current potential schematic diagram of each node in level shifting circuit in Fig. 3 in one embodiment.
Specific embodiment
A kind of level switch module of level shifting circuit is as shown in figure 1, the level shifting circuit includes 4 PMOSs
(MP1, MP2, MP3 and MP4), 2 NMOS tubes (MN1 and MN2), 2 phase inverters (VD1 and VD2), 1 input voltage port
Vin and 1 output voltage port Vout.
When the input voltage of input voltage port Vin is logic low 0, such as it is grounded, inverted device VD1 outputs are patrolled
Collect the grid of the NMOS tube of high level 1 to the first MN1 so that the first NMOS tube MN1 is turned on, output is caused under the drop-down effects of MN1
The output voltage of voltage port Vout is 0V.
When the input voltage of input voltage port Vin is logic high 1, such as voltage V11, after inverted device VD1
Export logic low to the grid of the first NMOS tube MN1 and the grid of the 3rd PMOS MP3 so that the first NMOS tube MN1 cuts
Only, the grid of the 3rd PMOS MP3 is logic low so that the 3rd PMOS MP3 is turned on, and is exported after inverted device VD2 and patrolled
Collect high level to the grid of the second NMOS tube MN2 and the grid of the 4th PMOS MP4, the second NMOS tube MN2 conductings, the 4th PMOS
Pipe MP4 ends, and the grid of the first PMOS MP1 is connected with the source electrode of the second NMOS tube MN2, i.e., the grid of MP1 is logic low electricity
It is flat so that the first PMOS MP1 is turned on, under the first PMOS MP1 and the effect of the 3rd PMOS MP3 pull-up, level conversion
The output voltage of circuit output voltage port Vout is voltage V22, is realized by the conversion of voltage V11 to voltage V22.
In the unexpected power down of first voltage, first voltage is 0 to the level shifting circuit, and phase inverter is stopped so that MN1
And the grid voltage on MN2 is 0, so as to the grid voltage for causing MP1 and MP2 plays pendulum, in such case
Under, the output voltage of the level shifting circuit output voltage port may be logic low 0, logic high 1 or intermediate state,
So as to have influence on the stable state of late-class circuit.
In one embodiment, as shown in Fig. 2 a kind of level shifting circuit, including the phase inverter that is sequentially connected, level turn
Parallel operation and latch module；
Level translator includes the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the first NMOS tube
And second NMOS tube；The source electrode of the first PMOS is connected with external power source, drain electrode and the 3rd PMOS of the first PMOS
Source electrode is connected, and the grid of the first PMOS is connected with the drain electrode of the 4th PMOS；The source electrode of the second PMOS connects with external power source
Connect, the grid of the second PMOS is connected with the drain electrode of the 3rd PMOS, the source electrode drained with the 4th PMOS of the second PMOS
Connection；The drain electrode of the 3rd PMOS is connected with the source electrode of the first NMOS tube, the grid of the 3rd PMOS, first NMOS tube
The grid of grid, the grid of the second NMOS tube and the 4th PMOS is connected with phase inverter, the input of the grid of the second NMOS tube
The input signal of the grid of signal and the 4th PMOS is identical with the input end signal of phase inverter, the grid of the 3rd PMOS
The input signal of the grid of input signal and the first NMOS tube is identical with inverter output signal；The drain electrode of the 4th PMOS
Source electrode with the second NMOS tube is connected, the input of phase inverter as level shifting circuit input, the source of the first NMOS tube
Pole as level shifting circuit output end；
The control end of latch module receives external threshold signal, the first end ground connection of latch module, the second of latch module
End drain electrode, the drain electrode of the second NMOS tube, the drain electrode of the 3rd PMOS and the leakage of the 4th PMOS respectively with the first NMOS tube
Pole connects.
Above-mentioned level shifting circuit, including phase inverter, level translator and the latch module being sequentially connected, level translator
Including the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the first NMOS tube and the second NMOS tube, latch
The control end of module receives external threshold signal, the first end ground connection of latch module, and the second end of latch module is respectively with first
The drain electrode of NMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the 3rd PMOS and the drain electrode of the 4th PMOS connection, by outer
Portion's threshold signal opens latch module, it is ensured that when instant cut-off or power down occurs in level shifting circuit, level shifting circuit is defeated
The output voltage for going out end is still stablized.
In one embodiment, the latch module of level shifting circuit includes the 3rd NMOS tube, the 4th NMOS tube and the
Five NMOS tubes；
The source electrode of the 3rd NMOS tube is connected with the drain electrode of the 3rd PMOS, the grid of the 3rd NMOS tube and the 4th PMOS
Drain electrode connection, the grounded drain of the 3rd NMOS tube；The source electrode of the 4th NMOS tube is connected with the drain electrode of the 4th PMOS, the 4th NMOS
The grid of pipe is connected with the drain electrode of the 3rd PMOS, the grounded drain of the 4th NMOS tube；The source electrode of the 5th NMOS tube is respectively with
The drain electrode of one NMOS tube and the drain electrode of the second NMOS tube are connected, the grounded drain of the 5th NMOS tube, the grid of the 5th NMOS tube
Receive external threshold signal.
The level shifting circuit includes the phase inverter, level translator and the latch module that are sequentially connected, level translator bag
The first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the first NMOS tube and the second NMOS tube are included, mould is latched
Block includes the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube, the drain electrode of the source electrode and the 3rd PMOS of the 3rd NMOS tube
Connection, the grid of the 3rd NMOS tube is connected with the drain electrode of the 4th PMOS, the grounded drain of the 3rd NMOS tube；4th NMOS tube
Source electrode is connected with the drain electrode of the 4th PMOS, and the grid of the 4th NMOS tube is connected with the drain electrode of the 3rd PMOS, the 4th NMOS tube
Grounded drain；The source electrode of the 5th NMOS tube is connected with the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube respectively, the
The drain electrode of five NMOS tubes is connected to ground, and the grid of the 5th NMOS tube receives external threshold signal, is opened by threshold signal and latched
Module, it is ensured that when instant cut-off or power down occurs in level shifting circuit, the output voltage of level shifting circuit output end is still
Stabilization.
In one embodiment, the first PMOS of level shifting circuit, the second PMOS, the 3rd PMOS and the 4th
PMOS is the PMOS of same model, the first NMOS tube and the NMOS tube that the second NMOS tube is same model, level conversion electricity
3rd NMOS tube of road latch module, the 4th NMOS tube and the NMOS tube that the 5th NMOS tube is same model, so facilitate level
The production of change-over circuit.
In one embodiment, as shown in Fig. 2 the phase inverter of level shifting circuit includes the first CMOS inverter, second
The grid of the grid of NMOS tube and the 4th PMOS is connected with the input of the first CMOS inverter, the grid of the 3rd PMOS
And first the grid of NMOS tube be connected with the first CMOS inverter output end.In another embodiment, as shown in figure 3, electric
The phase inverter of flat change-over circuit also includes the second CMOS inverter being connected with the first CMOS inverter, the first CMOS inverter
Input as phase inverter input, the output end of the second CMOS inverter as phase inverter output end, the 3rd PMOS
Grid and the grid of the first NMOS tube be connected with the output end of the first CMOS inverter, the grid of the second NMOS tube and
The grid of four PMOSs is connected with the output end of the second CMOS inverter.Specifically, each CMOS inverter includes the 5th PMOS
Pipe and the 6th NMOS tube, the 5th PMOS source electrode is connected with external power source, the grid of the 5th PMOS and the grid of the 6th NMOS tube
Pole connects, and used as the input of phase inverter, the drain electrode of the 5th PMOS is connected with the drain electrode of the 6th NMOS tube, and as anti-phase
The output end of device, the source ground of the 6th NMOS tube.CMOS inverter is connected by a PMOS and a NMOS tube, PMOS
Used as load pipe, used as input pipe, this configuration can be greatly reduced power consumption to NMOS tube, because in two kinds of logic states, two
One in individual transistor is always off, and processing speed can also be improved well, because anti-with nmos type and pmos type
Phase device is compared, and the resistance of CMOS inverter is relatively low.
In one embodiment, the external power source output first voltage of level shifting circuit, the input of phase inverter is received
External voltage, the input range of external voltage is 0 to second voltage, and first voltage is more than second voltage, is capable of achieving level conversion
The input voltage of circuit input end is second voltage, and the output voltage of level shifting circuit output end is first voltage.Level turns
Changing circuit includes buffer cell, and the input of level shifting circuit is connected by buffer cell with level shifting circuit, and buffering is single
Unit includes two buffer inverters being sequentially connected, and buffer cell enhances the driving force to level translator, and to defeated
The input signal for entering end carries out shaping, can effectively improve the stability of input signal, it is to avoid unstable input signal is to level
The influence of change-over circuit.
Operation principle to the level shifting circuit by taking the level shifting circuit that the band shown in Fig. 3 is latched as an example is illustrated such as
Under, the circuit structure of the level shifting circuit includes：(1) first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3,
4th PMOS MP4；(2) first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th
NMOS tube MN5；(3) first phase inverter VD1, the second phase inverter VD2；(4) input voltage port Vin, output voltage port Vout,
Threshold value port Vlatch.
Wherein, the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, a NMOS
Pipe MN1, the second NMOS tube MN2, the first phase inverter VD1, the second phase inverter VD2, input voltage port Vin, output voltage port
Vout, the circuit structure connection with the level switch module of level shifting circuit in Fig. 1 is consistent.
The source electrode of the 3rd NMOS tube MN3 is connected with the drain electrode of the 3rd PMOS MP3, the grid of the 3rd NMOS tube MN3 and
The drain electrode connection of four PMOS MP4, the grounded drain of the 3rd NMOS tube MN3；The source electrode and the 4th PMOS of the 4th NMOS tube MN4
The drain electrode connection of MP4, the grid of the 4th NMOS tube MN4 is connected with the drain electrode of the 3rd PMOS MP3, the leakage of the 4th NMOS tube MN4
Pole is grounded；The source electrode of the 5th NMOS tube MN5 is connected with the drain electrode of the first NMOS tube MN1, the grounded drain of the 5th NMOS tube MN5,
The grid of the 5th NMOS tube MN5 is connected with threshold value port Vlatch.
The latching process of the level shifting circuit is as follows：
When the input signal of threshold value port Vlatch is logic high 1, MN5 conductings, it is low level 0 that node e is pulled low,
Level shifting circuit is unlatching state.Now when the input voltage of input voltage port Vin is logic low 0, pass through
Node a after first phase inverter VD1 is logic high 1, the grid of the first NMOS tube MN1 and the grid of the 3rd PMOS MP3
It is logic high, the first NMOS tube MN1 conductings, the 3rd PMOS MP3 ends, and it is logic low 0 that node c is pulled low, the
The grid of four NMOS tube MN4 is logic low so that the 4th NMOS tube MN4 ends；Node after the second phase inverter VD2
B is logic low 0, and the second NMOS tube MN2 is not turned on, and the 4th PMOS MP4 conductings, node d is logic high 1；Due to
Node d is logic high 1, and the grid of the 3rd NMOS tube MN3 is logic high so that the 3rd NMOS tube MN3 is turned on, and is connect
Ground, node c is logic low 0, and now the output voltage of output voltage port Vout is logic low 0.
The input signal of threshold value port Vlatch is changed to logic low 0, the 5th NMOS tube MN5 cut-offs, node e is height
Level 1, level shifting circuit enters latch mode；When input voltage port occurs signal fault, it is originally logic low to cause
The node b of level 0, is changed into logic high 1, because node e is logic high 1, node d is still logically high electricity
It is logic low 0 that flat 1, node c are pulled low, and the output voltage of output voltage port Vout is still logic low 0.
When the input signal of input voltage port Vin is logic low 0, level shifting circuit is before latch and latches
Before the current potential situation of each circuit node afterwards is as shown in figure 4, latch：Fig. 3 interior joints a is logic high 1, and node b is logic
Low level 0, node c is logic level 0, and node d is logic high 1, and node e is logic low 0；After latch, saved in Fig. 3
Point a is logic high 1, and node b is logic high 1, and node c is logic level 0, and node d is logic high 1, node e
It is logic high 1.
Similarly, when the input signal of input voltage port Vin is logic high 1, it is equally applicable to above-mentioned analysis.
When the input signal of threshold value port Vlatch is logic high 1, MN5 conductings, it is low level 0 that node e is pulled low,
Level shifting circuit is unlatching state.Now when the input voltage of input voltage port Vin is logic high 1, pass through
Node a after first phase inverter VD1 is logic low 0, the grid of the first NMOS tube MN1 and the grid of the 3rd PMOS MP3
It is logic low, the first NMOS tube MN1 cut-offs, the 3rd PMOS MP3 conductings；It is by the node b after the second phase inverter VD2
Logic high 1, the second NMOS tube MN2 conductings, the 4th PMOS MP4 cut-offs, node d is logic low 0；Due to node d
It is logic low 0, the grid of the 3rd NMOS tube MN3 is logic low so that the 3rd NMOS tube MN3 ends, a PMOS
Pipe MP1 is turned on, and node c is logic high 1, and now the output voltage of output voltage port Vout is logic high 1.
The input signal of threshold value port Vlatch is changed to logic low 0, the 5th NMOS tube MN5 cut-offs, node e is height
Level 1, level shifting circuit enters latch mode；When input voltage port occurs signal fault, it is originally logic low to cause
The node a of level 0, is changed into logic high 1, the 3rd PMOS MP3 cut-offs, the first NMOS tube MN1 conductings, because node e
It is logic high 1, so node c is logic high 1, the output voltage of output voltage port Vout is still logic high
1。
Based on foregoing circuit structure, when the input voltage of input voltage port Vin is continuously a certain level, by threshold value
The input signal of port Vlatch controls the unlatching of latch module, after latch function module is started, can effectively ensure output
Voltage is continual and steady, the input signal of next stage circuit is kept continual and steady, it is to avoid the influence of external interference, such as Vin become
Dynamic violent, phase inverter is damaged, signal is interrupted temporarily etc..
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope of this specification record is all considered to be.
Embodiment described above only expresses several embodiments of the invention, and its description is more specific and detailed, but simultaneously
Can not therefore be construed as limiting the scope of the patent.It should be pointed out that coming for one of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. a kind of level shifting circuit, it is characterised in that including the phase inverter, level translator and the latch module that are sequentially connected；
The level translator includes the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the first NMOS tube
And second NMOS tube；The source electrode of first PMOS is connected with external power source, the drain electrode of first PMOS with it is described
The source electrode connection of the 3rd PMOS, the grid of first PMOS is connected with the drain electrode of the 4th PMOS；Described second
The source electrode of PMOS is connected with the external power source, and the grid of second PMOS connects with the drain electrode of the 3rd PMOS
Connect, the drain electrode of second PMOS is connected with the source electrode of the 4th PMOS；The drain electrode of the 3rd PMOS with it is described
The source electrode connection of the first NMOS tube, the grid of the 3rd PMOS, the grid of first NMOS tube, second NMOS tube
Grid and the grid of the 4th PMOS be connected with the phase inverter, the input signal of the grid of second NMOS tube
And the input signal of the grid of the 4th PMOS is identical with the input end signal of the phase inverter, the 3rd PMOS
Grid input signal and first NMOS tube grid input signal it is identical with the inverter output signal；
The drain electrode of the 4th PMOS is connected with the source electrode of second NMOS tube, and the input of the phase inverter is used as the level
The input of change-over circuit, the source electrode of first NMOS tube as the level shifting circuit output end；
The control end of the latch module receives external threshold signal, the first end ground connection of the latch module, the latch mould
The drain electrode respectively with first NMOS tube of second end of block, the drain electrode of the second NMOS tube, the drain electrode of the 3rd PMOS with
And the drain electrode connection of the 4th PMOS.
2. level shifting circuit according to claim 1, it is characterised in that the latch module include the 3rd NMOS tube,
4th NMOS tube and the 5th NMOS tube；
The source electrode of the 3rd NMOS tube is connected with the drain electrode of the 3rd PMOS, the grid of the 3rd NMOS tube with it is described
The drain electrode connection of the 4th PMOS, the grounded drain of the 3rd NMOS tube；The source electrode and the described 4th of the 4th NMOS tube
The drain electrode connection of PMOS, the grid of the 4th NMOS tube is connected with the drain electrode of the 3rd PMOS, the 4th NMOS
The grounded drain of pipe；The drain electrode respectively with first NMOS tube of the source electrode of the 5th NMOS tube and second NMOS tube
Drain electrode connection, the grounded drain of the 5th NMOS tube, the grid of the 5th NMOS tube receives external threshold signal.
3. level shifting circuit according to claim 2, it is characterised in that the 3rd NMOS tube, the 4th NMOS
Pipe and the 5th NMOS tube are the NMOS tube of same model.
4. level shifting circuit according to claim 1, it is characterised in that the phase inverter includes that a CMOS is anti-phase
The grid of device, the grid of second NMOS tube and the 4th PMOS connects with the input of first CMOS inverter
Connect, the grid of the 3rd PMOS and the grid of first NMOS tube connect with the first CMOS inverter output end
Connect.
5. level shifting circuit according to claim 1, it is characterised in that the phase inverter includes be sequentially connected first
CMOS inverter and the second CMOS inverter, the input of first CMOS inverter as the phase inverter input,
The output end of second CMOS inverter as the phase inverter output end, the grid of the 3rd PMOS and described
The grid of the first NMOS tube is connected with the output end of first CMOS inverter, the grid of second NMOS tube and described
The grid of the 4th PMOS is connected with the output end of second CMOS inverter.
6. the level shifting circuit according to claim 4 or 5, it is characterised in that each CMOS inverter includes the
Five PMOSs and the 6th NMOS tube, the 5th PMOS source electrode are connected with the external power source, the grid of the 5th PMOS
Pole is connected with the grid of the 6th NMOS tube, and used as the input of the phase inverter, the drain electrode of the 5th PMOS with
The drain electrode connection of the 6th NMOS tube, and as the output end of the phase inverter, the source ground of the 6th NMOS tube.
7. level shifting circuit according to claim 1, it is characterised in that also including external power source, the external power source
Output first voltage, the input of the phase inverter receives external voltage, and the scope of the external voltage is 0 to second voltage,
The first voltage is more than the second voltage.
8. level shifting circuit according to claim 1, it is characterised in that also including buffer cell, the level conversion
The input of circuit is connected by the buffer cell with the level shifting circuit.
9. level shifting circuit according to claim 8, it is characterised in that the buffer cell is sequentially connected including two
Buffer inverter.
10. level shifting circuit according to claim 1, it is characterised in that first PMOS, the 2nd PMOS
Pipe, the 3rd PMOS and the PMOS that the 4th PMOS is same model, first NMOS tube and described second
NMOS tube is the NMOS tube of same model.
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| CN201710092872.9A CN106899288B (en) | 2017-02-21 | 2017-02-21 | Level conversion circuit |
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| CN201710092872.9A CN106899288B (en) | 2017-02-21 | 2017-02-21 | Level conversion circuit |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107659302A (en) * | 2017-08-28 | 2018-02-02 | 天津大学 | Level shifting circuit with pre-amplification |
| CN108540124A (en) * | 2018-04-16 | 2018-09-14 | 电子科技大学 | A kind of level shifting circuit |
| CN109756222A (en) * | 2017-11-03 | 2019-05-14 | 展讯通信（上海）有限公司 | A kind of level shifting circuit and chip system |
| CN112332833A (en) * | 2020-11-16 | 2021-02-05 | 海光信息技术股份有限公司 | Level conversion circuit and CPU chip with same |
| CN113131917A (en) * | 2019-12-31 | 2021-07-16 | 圣邦微电子（北京）股份有限公司 | High-voltage-resistant high-speed level shifter |
| CN113938126A (en) * | 2021-10-25 | 2022-01-14 | 中国电子科技集团公司第五十八研究所 | Voltage latching type level conversion circuit |
| CN115037292A (en) * | 2022-08-09 | 2022-09-09 | 成都市安比科技有限公司 | High-dropout level transfer circuit with enabling detection and power-down protection |
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| CN101686047A (en) * | 2008-09-24 | 2010-03-31 | 奕力科技股份有限公司 | Level switching circuit |
| CN103856206A (en) * | 2012-12-06 | 2014-06-11 | 上海华虹集成电路有限责任公司 | Low-to-high logic level conversion circuit |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107659302A (en) * | 2017-08-28 | 2018-02-02 | 天津大学 | Level shifting circuit with pre-amplification |
| CN109756222A (en) * | 2017-11-03 | 2019-05-14 | 展讯通信（上海）有限公司 | A kind of level shifting circuit and chip system |
| CN108540124A (en) * | 2018-04-16 | 2018-09-14 | 电子科技大学 | A kind of level shifting circuit |
| CN113131917A (en) * | 2019-12-31 | 2021-07-16 | 圣邦微电子（北京）股份有限公司 | High-voltage-resistant high-speed level shifter |
| CN113131917B (en) * | 2019-12-31 | 2022-10-21 | 圣邦微电子（北京）股份有限公司 | High-voltage-resistant high-speed level shifter |
| CN112332833A (en) * | 2020-11-16 | 2021-02-05 | 海光信息技术股份有限公司 | Level conversion circuit and CPU chip with same |
| CN112332833B (en) * | 2020-11-16 | 2022-08-26 | 海光信息技术股份有限公司 | Level conversion circuit and CPU chip with same |
| CN113938126A (en) * | 2021-10-25 | 2022-01-14 | 中国电子科技集团公司第五十八研究所 | Voltage latching type level conversion circuit |
| CN113938126B (en) * | 2021-10-25 | 2023-08-01 | 中国电子科技集团公司第五十八研究所 | Voltage latching type level conversion circuit |
| CN115037292A (en) * | 2022-08-09 | 2022-09-09 | 成都市安比科技有限公司 | High-dropout level transfer circuit with enabling detection and power-down protection |
| CN115037292B (en) * | 2022-08-09 | 2022-10-28 | 成都市安比科技有限公司 | High-dropout level transfer circuit with enabling detection and power-down protection |
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