CN108428662A - 在芯片制造期间处置薄晶片 - Google Patents
在芯片制造期间处置薄晶片 Download PDFInfo
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- CN108428662A CN108428662A CN201810151267.9A CN201810151267A CN108428662A CN 108428662 A CN108428662 A CN 108428662A CN 201810151267 A CN201810151267 A CN 201810151267A CN 108428662 A CN108428662 A CN 108428662A
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Abstract
本发明涉及在芯片制造期间处置薄晶片。提供了一种制造方法,其包括:在晶片(100)的正面(102)中形成凹进部(112),将第一临时支持体(104)连接到凹进的晶片(100)的正面,此后从背面(106)将晶片(100)减薄,将第二临时支持体(110)连接到背面(106),以及此后移除第一临时支持体(104)。
Description
技术领域
本发明涉及制造方法、中间产品、半导体器件和电子器件。
背景技术
用于电子芯片的诸如模具结构之类的常规封装已经发展到封装不再显著地阻碍电子芯片性能的水平。此外,在晶片级上处理电子芯片是用于有效率地生产它们的已知过程。蚀刻电子芯片是用于从其移除材料的常规技术。在封装制造期间将电子芯片进行包封可以保护它们免受环境影响。
在另一种技术中,使用了非包封式半导体器件,其中再分配层与焊接结构一起形成在其中具有集成电路的半导体主体上。
然而,仍然存在潜在的空间来降低制造成本以及简化电子芯片的处理,同时维持处理的高精确度。此外,处置越来越薄的晶片和电子芯片变得越来越有挑战。
发明内容
可能需要一种制造具有小厚度的电子芯片的可靠方法。
根据示例性实施例,提供了一种制造方法,其包括:在晶片的正面中形成凹进部,将第一临时支持体连接到凹进的晶片的正面,在此之后从背面对该晶片进行减薄,将第二临时支持体连接到该背面,以及在此之后移除该第一临时支持体。
根据另一示例性实施例,提供一种制造方法,其包括:在晶片的正面中形成凹进部,在晶片的正面上附接导电互连结构,将第一临时支持体连接到凹进的晶片的正面并且将导电互连结构嵌入该第一临时支持体中,以及在此之后将该晶片单颗化成多个电子芯片。
根据又一示例性实施例,提供了一种制造方法,其包括:在晶片的正面中形成凹进部,将临时支持体连接到凹进的晶片的正面,以及在此之后从背面将该晶片一直减薄至小于300 μm的厚度。
根据另外又一示例性实施例,提供一种中间产品,其包括:多个电子芯片,在该电子芯片中的每个上的至少一个焊接结构,以及在该电子芯片和导电互连结构上的公共临时支持体。
根据另外又一示例性实施例,提供了一种非包封式半导体器件,其包括:具有不大于200 μm的厚度的半导体主体,在该半导体主体的正面上的至少一个焊接结构,以及该半导体主体与该至少一个焊接结构之间的再分配层。
根据另外又一示例性实施例,提供了一种电子器件,其包括:器件载体(例如印刷电路板,PCB)和具有上文所提到的特征并且被安装在该器件载体上的非包封式半导体器件。
根据本发明的示例性实施例,提供了一种制造半导体器件的方法,其中首先从正面使晶片凹进,以及然后在将该晶片连接到第一临时支持体之后将该晶片从背面减薄。在这样的减薄之后,该方法还可以实现将晶片的电子芯片进行单颗化,可以将第二临时支持体附接到背面(已经发生减薄之处),以及可以然后移除该第一临时支持体。替换地,还可以在背面减薄之后通过正面切割来实现单颗化。通过这样的架构,可以实现的是,灵敏的经减薄的电子芯片和/或晶片总是保持被附接到至少一个临时支持体,这显著地简化了处置并且保护薄电子芯片或薄晶片免于损坏。因此,所描述的架构允许制造具有与常规可以实现的厚度相比显著更薄的厚度的(特别是非包封式或裸露式)半导体器件。因此,该制造架构在不增加灵敏的薄电子芯片的损坏风险的情况下提升了电子芯片的小型化。
进一步示例性实施例的描述
在本申请的情境中,术语“临时支持体”可以尤其表示一种主体(诸如柔性箔),其在制造半导体器件期间临时地支持晶片和/或各个电子芯片,但是不形成容易制造的半导体器件的部分。因此,该一个或多个临时支持体(其在某些实施例中还可以被表示为临时载体)在临时粘附于晶片或电子芯片上之后可以从晶片或电子芯片移除。该(一个或多个)临时支持体可以支持或支撑晶片或芯片,并且可以因此简化它们的处置,特别地在晶片或芯片已经非常薄的时候。可变形的临时载体还可以覆盖晶片或芯片的表面,并且可以因此保护表面在例如研磨之类的处理期间免受化学或机械影响。
在本申请的情境中,术语“非包封式半导体器件”可以尤其表示一种半导体芯片,其中提供了具有电耦合结构(诸如再分配层)但是并不由模塑化合物、层压件或另一种密封剂所包封的半导体芯片(即,裸管芯,其中可以形成至少一个单片集成电路)。然而,可以利用一层清漆等等(其可以例如在单颗化之后通过喷涂来施加)来覆盖该非包封式半导体器件。还可能的是,利用(例如黑色的)背面保护箔(BSP箔)来覆盖该非包封式半导体器件。
在下文中,将解释该方法、中间产品、半导体器件以及电子器件的进一步示例性实施例。
在实施例中,该方法可以被配置成根据被应用到芯片级封装的晶片级球栅阵列架构来进行操作。
在实施例中,该方法包括从正面和背面中的至少一个移除凹进的晶片的材料,以由此将晶片单颗化成多个电子芯片。在一个实施例中,通过仅从晶片的背面通过研磨来移除材料来实现单颗化(例如参见图1到图7)。在另一实施例中,通过首先从晶片的背面通过研磨来移除材料,接着通过刀片切割正面上先前形成的凹进部来实行单颗化(例如参见图8到图13)。两个过程都允许在没有处置问题的情况下制造具有极薄厚度的半导体器件。
在实施例中,该方法包括:通过由以下各项组成的组中的至少一项来移除材料:从背面研磨,以及利用刀片从正面切割。利用研磨过程,可以实现对晶片的均匀减薄。通过利用刀片进行切割(其还可以被表示为刀片切割),凹槽形的预切凹进部可以被转换成通孔,从而完成单颗化过程。这些凹进部可以是通道或长圆孔。
在实施例中,一个或多个凹进部是通过等离子处理或激光开槽所形成的。凹进可以包括形成将经处理晶片的区域进行分隔的沟槽,这些区域之后构成各个半导体器件或电子芯片。可以通过等离子处理来有利地实现形成这种可以之后在减薄时限定分隔位置的沟槽或凹槽。等离子蚀刻的特定进一步优点是,这允许自由地选择芯片形状(例如矩形、圆形、八边形等)。与机械凹进部形成技术相反的是,等离子处理对于已经很薄的晶片是非常柔和的,这提供了针对晶片或电子芯片的破损或劣化的可靠保护。然而,只要确保凹进部形成不损坏晶片材料,其他凹进部形成技术也是可能的(例如刀片切割)。当沿着晶片的表面引导激光时,也可以通过这样的激光处理或激光烧蚀来形成(一个或多个)凹进部。
在实施例中,通过研磨来实行减薄。可以以机械方式来实现研磨,并且研磨可以从背面移除晶片的材料,以使得当研磨过程到达(或接近)从正面形成的凹进部时,可以将对应形成的电子芯片单颗化(或者可以准备单颗化)。作为通过研磨进行减薄的替换方案,还可能的是通过等离子处理、化学蚀刻、激光处理等来将晶片减薄。
在实施例中,该方法进一步包括:在将第一临时支持体连接到凹进的晶片的正面以及连接到导电互连结构之前,将导电互连结构附接在晶片的正面上(或者附接到晶片上的再分配层上)。优选地,导电互连结构可以是焊接结构,尤其是焊球,其可以被焊接到晶片的正面上。然而,作为对焊球等的替换方案,还可能的是将导电互连结构配置为凸块(bump)。在这样的实施例中,可以生长(例如具有在10 μm与50 μm之间的范围中的厚度的)导电材料(尤其是铜),并且可以由非氧化层(例如具有若干微米的厚度,例如无电镀NiPPd层)来覆盖该导电材料。这还允许在PCB(印刷电路板)或另一器件载体上进行焊接。此外,可以通过焊接或另一电接触方法来将导电互连结构配置用于导电互连配置。这样的替换方案可以是使用下述各项:导电粘合剂、通过施加压力变为导电的粘合剂,等等。
可以通过半导体技术在正面上处理晶片及其电子芯片。换言之,一个或多个集成电路元件可以被单片集成在晶片及其电子芯片的正面上的活动区域中。相应地,可以在正面上形成再分配层(在半导体世界的小尺寸与PCB世界的更大尺寸之间转化)。可以通过被应用于晶片或电子芯片的正表面上的导电互连结构来实现将容易形成的半导体器件或电子芯片与诸如印刷电路板之类的电子环境电耦合。令人惊奇的是,在正面上提供焊球或任意其他导电互连结构以及导致形成表面轮廓或突出物并不阻止这样的结构正确地连接到第一临时支持体。相反,可能的是在出于平面化和保护目的进行研磨之前,将导电互连结构嵌入第一临时支持体中。
在实施例中,该方法进一步包括由以下各项组成的组中的至少一项:实行晶片的功能测试以及将数据写入晶片中。这可以通过在将第一临时支持体连接到凹进的晶片的正面以及连接到导电互连结构之前向导电互连结构施加电信号来实现。对于执行功能测试的附加或替换,还可能的是晶片探头等被用于将数据写入晶片或其电子芯片中。例如,这样的数据可以是用于以下各项的参数:修整或线性化相应电子芯片的功能、相应电子芯片的存储器中的操作***或其他软件的加载等等。在加密应用中,例如可能的是将芯片个体密钥写入到相应电子芯片中,该电子芯片由此可以变成唯一的。
已经由电子芯片或半导体器件提供了全部电子功能性,同时该电子芯片或半导体器件在单颗化之前仍在晶片级上是互连的。因此,可能的是通过向导电互连结构施加刺激信号并且在单颗化之前测量相同和/或其他导电互连结构上的响应信号来实行电子功能测试。
在实施例中,该方法进一步包括:通过第二临时支持体来对背面(特别是已经单颗化的晶片的背面,或者完成单颗化之前的晶片的背面)进行激光处理。例如,电子芯片或晶片可以被提供有标识符,该标识符可以通过激光处理被雕刻在电子芯片或晶片的功能上不活动的背面上。有利地,不必为了激光加标而移除第二临时支持体,因为已经证明的是在相应地调节第二临时支持体的材料(例如适合的聚合物)和激光波长(例如绿光)时,激光辐射可以基本上在第二临时支持体不吸收激光辐射的情况下通过第二临时支持体。
在实施例中,该方法进一步包括:从第二临时支持体各个地拾取电子芯片。当第一临时支持体已经被移除时,可能的是各个电子芯片或半导体器件由拾取和放置机构各个地拾取,并且被直接组装到器件载体(诸如PCB)上或者被安装在条带上(例如带盘式过程中)等等。例如,装备有薄尺寸的各个电子芯片的这种条带可以然后在卷轴上卷起。例如,可以通过吸引机构利用真空力将电子芯片从第二临时支持体拆分来拾取单个电子芯片。
特别地,所描述的拾取过程可以通过以下方式来实现:吸引套管吸取(特别是由真空支持)电子芯片或半导体器件中的相应一个的正面,同时释放体(诸如释放针)从电子芯片中相应一个的背面对其进行推动(特别是通过第二临时支持体)。
在实施例中,该方法进一步包括:在移除第一临时支持体之前,将第二临时支持体连接到背面。通过在移除第一临时支持体之前将第二临时支持体连接到半成产品,确保了灵敏的薄电子芯片或晶片决不与临时支持体中的至少一个分离。因此,可以通过提供两个临时支持体来安全地防止对敏感的经减薄电子芯片或晶片的损坏,两个临时支持体中的一个要被附接到正面,而另一个要被附接到背面。
在实施例中,该方法包括:通过将晶片从背面至少一直减薄至凹进部来将晶片单颗化成多个电子芯片。参照图1到图7来描述这样的实施例。研磨过程持续直到研磨到达晶片的相对主表面上的凹进部,从而完成单颗化。
在另一实施例中,该方法包括:通过从背面将晶片减薄,之后从正面移除凹进部处的材料,来将晶片单颗化成多个电子芯片。在这样的替换实施例中,参见例如图8到图13,在研磨之后单颗化还未完成。与此相对比的是,在研磨之后,为了完成单颗化而实行利用刀片进行切割,即,切割经减薄的晶片的预先形成的凹进部,直到各个电子芯片被分离。
在实施例中,第一临时支持体被配置为柔性(例如带粘性的)薄板,其具有面对至少一个焊接结构的塑性可变形的或变形的表面部分。例如,第一临时支持体可以是柔性箔,其可以(例如通过层压)被附接到晶片的上表面上。该箔可以具有载体膜,该载体膜上可以应用可变形材料。通过热处理,第一临时支持体可以开始融化,并且可以被塑性变形,以便形成与其上具有导电互连结构的晶片的表面相比基本上倒转的表面轮廓。通过采用这种措施,导电互连结构以下述方式被嵌入第一临时支持体中:在不损坏导电互连结构的情况下实行将第一临时支持体随后从然后被单颗化的电子芯片释放。第一临时支持体可以像帐篷一样覆盖导电互连结构。第一临时支持体还可以用作表面保护,并且可以具有对晶片或电子芯片的平面化效果。在另一实施例中,可以基于可流动介质(诸如聚合物液体或粘性材料)来制作第一临时支持体,该可流动介质可以以液体形式应用(例如分配)并且在此之后在晶片的上表面上固化(例如热固化)。
在实施例中,第二临时支持体被配置为柔性(例如带粘性的)薄板。因此,第二临时支持体可以是柔性箔,其可以(例如通过层压)被附接到晶片的下表面或已经分离的电子芯片的下表面上。在另一实施例中,第二临时支持体可以是可流动介质(诸如聚合物液体或粘性材料),该可流动介质可以在晶片或已经分离的电子芯片的下表面上应用(例如分配)和固化(例如热固化)。第二临时支持体还可以用作支撑、表面保护,并且可以具有平面化效果。
在实施例中,该方法进一步包括:在电子芯片保持附接到第二临时支持体的同时对背面进行激光加标。令人惊讶的是,通过第二临时支持体在经减薄的电子芯片的背面上进行激光加标是可能的,所以无需为了加标而移除电子芯片。替换地,在已经将各个半导体器件从第二临时支持体拆分之后,还可以通过激光处理来完成针对可追溯性的器件加标。
在实施例中,该方法进一步包括各个地(即,逐个)将电子芯片从第二临时支持体拆分。因此可以将电子芯片从第二临时主体一个接一个地移除以用于进一步处理,例如组装或转移到条带。
在实施例中,将晶片从至少600 μm的初始厚度减薄至不多于200 μm的最终厚度。在600 μm或更多的厚度下,仍可能在没有严重的损坏风险的情况下单独地处置晶片。例如,初始厚度甚至可以大于700 μm。通过减薄过程,厚度可以一直被减少至不多于200 μm,特别是甚至150 μm或更少。通过使用两个临时支持体来有力地支持该过程,确保了经减薄的电子芯片从不需要独立于支持体而被处置。因此,可以安全地防止极薄电子芯片的损坏。
在实施例中,该方法进一步包括:将电子芯片从第一临时支持体再次粘附到背面上的第二临时支持体。换言之,经减薄的电子芯片可以首先在它们的正面上与第一临时支持体附接,并且可以然后在它们的背面上与第二临时支持体连接,优选地移除第一临时支持体之前。由此,电子芯片的粘附的主表面(即,正面或背面)可以在减薄之后并且在拾取电子芯片之前被改变。
在实施例中,该方法进一步包括:在减薄之前将导电互连结构焊接在晶片的正面上。这使得下述情况是不必要的或者是可有可无的:使已经减薄的或者甚至分离的芯片成为焊接应用过程的主体。与此相对比的是,在减薄之前并且因此在仍完整的晶片上可能已经实现焊接应用。这在配准精确度方面放宽了要求。
在实施例中,导电互连结构被至少部分地嵌入临时支持体中。可以充分宽松地嵌入这些导电互连结构,以使得当将临时支持体从电子芯片拆分时,导电互连结构保持附接在电子芯片上。通过嵌入突出的导电互连结构(其可能涉及到箔型的第一临时支持体的变形),可以使得第一临时支持体与其上具有再分配层和导电互连结构的晶片的正面上的组成部分之间的接触是可靠的。超出电子芯片表面其余部分而突出的焊球可以因此被临时放置在第一临时支持体的内部中。这可以例如通过充分柔软的和/或可变形的第一临时支持体或者通过在导电互连结构的位置处具有永久凹进部的临时支持体来实现。通过这两种方法都可以确保的是,通过具有导电互连结构和与其附接的第一临时支持体的晶片来获得平面结构,该平面结构简化了研磨。
在实施例中,中间产品的电子芯片具有不多于200 μm的厚度。相应地,半导体器件的半导体主体可以具有不多于200 μm的厚度。因此,可以在研磨之后在没有处置问题的情况下使电子芯片是非常薄的。因此,它们的处置是不成问题的,因为它们在被拾取和运输到目的地之前,总是保持附接到临时支持体中的至少一个。
在实施例中,半导体器件被配置为芯片级封装(CSP封装)。为了有资格成为芯片级,该封装应当具有不大于管芯或电子芯片的面积的1.2倍的面积,并且其应当是单管芯、直接表面可安装的封装。可以被应用来使封装有资格成为CSP封装的另一个标准是:它的球间距(ball pitch)应当不大于1 mm。特别地,CSP封装可以具有下述尺寸:该尺寸大于其电子芯片的尺寸不多于20%。CSP封装通常是非包封式的,并且可以因此被提供有非常小的厚度。因此,CSP封装非常适合于诸如可穿戴设备、便携式设备、手表、智能眼镜等等的应用。
在优选的实施例中,电子芯片被配置为控制器芯片、处理器芯片、存储器芯片、传感器芯片或微机电***(MEMS)。在替换的实施例中,还可能的是,电子芯片被配置为功率半导体芯片。因此,电子芯片(诸如半导体芯片)可以被用于例如汽车领域中的功率应用,并且可以例如具有至少一个集成绝缘栅双极晶体管(IGBT)和/或至少一个另一类型的晶体管(诸如MOSFET、JFET等)和/或至少一个集成二极管。可以例如以硅技术或者基于宽带隙半导体(诸如碳化硅、氮化镓或硅上氮化镓)来制作这样的集成电路元件。半导体功率芯片可以包括一个或多个场效应晶体管、二极管、反相器电路、半桥、全桥、驱动器、逻辑电路、另外的器件等等。
在一个实施例中,器件载体可以被配置为印刷电路板(PCB)。然而,也可以使用其他种类的器件载体。例如,半导体器件还可以被安装在诸如芯片卡之类的其他器件载体之上和/或之中。这样的芯片卡可以例如包括芯片或半导体器件以及天线等等。
作为形成电子芯片的基础的基板或晶片,可以使用半导体基板,优选为硅基板。替换地,可以提供二氧化硅基板或另一绝缘体基板。还可能的是实现锗基板或Ⅲ-Ⅴ族半导体材料。例如,可以以GaN或SiC技术来实现示例性实施例。根据示例性实施例的半导体器件可以被配置为微机电***(MEMS)、传感器等等。
此外,示例性实施例可以利用标准半导体处理技术,诸如适当的蚀刻技术(包括各向同性和各向异性蚀刻技术、特别是等离子蚀刻、干法蚀刻、湿法蚀刻)、图案化技术(其可能涉及到光刻掩模)、沉积技术(诸如化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、原子层沉积(ALD)、溅射等等)。
本发明的上述和其他目标、特征和优点,将根据结合附图进行以下的描述和所附权利要求而变得显而易见,在附图中相同的部分或元素由相同的附图标记来表示。
附图说明
被包括来提供对示例性实施例的进一步了解以及组成本说明书的一部分的附图图示了示例性实施例。
在附图中:
图1到图7示出了根据示例性实施例的在实行制造半导体器件的方法期间获得的中间产品的截面图。
图8到图13示出了根据另一示例性实施例的在实行制造半导体器件的方法期间获得的中间产品的截面图。
图14示出了根据示例性实施例的由作为表面安装式半导体器件的芯片级封装和作为用于半导体器件的器件载体的印刷电路板(PCB)所组成的电子器件的截面图。
具体实施方式
附图中的图示是示意性的。
在更详细描述进一步的示例性实施例之前,将总结发明人的一些基本考虑,基于这些考虑已经开发了示例性实施例,这些示例性实施例提供了能够处置非常薄的晶片和电子芯片的制造概念。
根据本发明的示例性实施例,提供了一种用于由经修改的晶片级结合架构来制造半导体器件的过程流程。更具体而言,示例性实施例提供了一种半导体封装,该半导体封装具有作为封装主体的小厚度的其半导体材料(特别是硅材料)。特别地,这样的制造架构特别有利于芯片级封装概念。
在常规的方法中,芯片级封装的制造过程要求晶片的某种最小厚度,以使得在处理期间可以处置晶片。目前,晶片需要具有400 μm的最小厚度,以便可利用标准处置设备进行处理。能够处置非常薄晶片的特殊设备则可以是可有可无的。
与此相对比的是,本发明的示例性实施例与半导体材料的甚至显著地更小的厚度相兼容。当晶片已经被处理时,即,集成电路(IC)元件已经被单片集成于其中并且再分配层已经形成于其上时,可以发起等离子切割(即,通过等离子处理形成凹进部)。替换地,还可以实行刀片切割(即,通过使用刀片的机械切割过程来形成凹进部)。利用这样的过程,可以在晶片的正面表面中形成凹进部。
随后,可能的是将导电互连结构(特别是焊球)焊接到晶片的正面上,更确切地说是焊接到其再分配层上。在制造过程的这个阶段,可以使用导电互连结构来实行对仍在晶片级上彼此连接的电子芯片的功能性的电测试。
随后,可以通过从背面研磨晶片来将各个电子芯片、构件或半导体器件单颗化。在该过程期间,可能的是将先前应用的导电互连结构嵌入第一临时支持体内,该第一临时支持体还可以被表示为研磨箔。
可以然后将经单颗化的电子芯片从研磨箔再次粘附到另一箔(其可以是锯切箔并且其可以被表示为第二临时支持体)上,该经单颗化的电子芯片在先前形成的凹进部的位置处作为研磨的结果而被分离。这意味着第二临时支持体可以被粘附到经单颗化的电子芯片的背面,并且在此之后第一临时支持体可以被移除。通过采用这种措施,薄的经单颗化的电子芯片决不会与临时支持体箔中的至少一个分离地处置。这显著地简化了对灵敏的非常薄的电子芯片的处置,并且防止对它们进行损坏。因此,经研磨的背面现在被附接到可以是粘性箔的第二临时支持体。
随后,背面可以成为通过第二临时支持体的激光加标过程的主体。这意味着激光可以传播通过第二临时支持体,并且可以对电子芯片的背面进行雕刻或加标。
接下来,可以从第二临时支持体拾取粘附到第二临时支持体的各个电子芯片,并且各个电子芯片可以之后被进一步处理。例如,它们可以被附接于带状物或者带子或者条带上。
所描述的过程流程具有显著的优点。利用这样的过程,起初仍是晶片化合物的组成部分的电子芯片可以保持在相对大的起始厚度(例如775 μm)上,直到它们被研磨回到它们的最终更小的厚度(例如大约150 μm)上。这简化了处置并且保护电子芯片免于损坏。当研磨晶片时,同时将电子芯片单颗化。这可以被表示为“在研磨之前切割”。
所描述的制造架构具有的优点为:在没有制造过程期间将芯片毁坏的风险的情况下,可以获得具有例如100 μm的非常小的厚度的CSP封装。薄箔可以被用作相应的支持体。
图1到图7示出了根据示例性实施例的在实行制造半导体器件130的方法期间获得的中间产品的截面图。所制造的半导体器件130在图6和图7中示出。所描述的过程涉及在完成半导体处理之前并且在诸如PCB之类的器件载体192(参见图14)上组装非包封式半导体器件130之前的制造阶段。
图1示出了半导体晶片100,在此被体现为硅晶片,其具有正面102和背面106。晶片100可以是具有例如300 mm的直径的圆盘,并且可以具有例如775 μm的初始厚度D。然而应当说明的是,其他尺寸也是可能的。例如,晶片100的直径还可以是200 mm、400 mm或450mm。在正面102上,多个集成电路元件(诸如晶体管、二极管等)被单片集成在晶片100的表面部分中。正面102对应于晶片100的活动区域。在晶片100的正面102的表面上,形成芯片焊盘165。晶片100包括多个电子芯片108,该电子芯片108可以是控制器、处理器、存储器芯片、传感器或半导体功率芯片。根据图1,电子芯片108仍被整体地连接。与此其对比的是,在示出的实施例中,晶片100的背面106尚未由半导体技术处理。
在已经将晶片100的正面102上的活动区域中的集成电路元件单片集成之后,在正面102上形成再分配层134。再分配层134充当用于增加间距的分界面。再分配层134被配置为包括一个或多个介电层181(尤其是由聚酰亚胺制成)的层序列,其中嵌入了金属结构133(例如电镀铜或电镀铝)。金属结构133被暴露以用于可连接到导电互连结构114,即,用于限定导电互连结构114的位置(参见图3)。金属结构133还与晶片100的上部中的活动区域上的芯片焊盘165电耦合。再分配层134由此在半导体世界中的结构(即,晶片100的正面102上的单片集成电路元件)的小距离与可以将要从晶片100单颗化的电子芯片108安装于其上的器件载体192的更大尺寸之间进行转变。例如,这样的器件载体192可以是印刷电路板(PCB)或芯片卡。
参照图2,通过等离子处理或蚀刻液或通过激光烧蚀在晶片100的正面102上的表面部分中形成一个或多个凹进部112。当实施蚀刻液时,可以使用在各向同性蚀刻过程中得到的液体蚀刻介质来实现凹进部112的形成。然而,在适当选择硅材料的晶体取向时,该过程仍然能够一直蚀刻到预定义的深度。形成凹进部112的过程可以被称为切入。出于这个目的,可以在再分配层134上应用掩模(未示出),并且可以为掩模提供开口以用于限定截槽(kerv),即,凹进部112的位置和尺寸。此后,可能的是实行一个或多个各向同性和/或各向异性蚀刻过程,其可以涉及等离子体。这允许在位置、深度和形状方面(即,具有跨截面基本上矩形的槽状)非常精确地限定凹进部112。在所描述的实施例中,凹进部112的深度L可以比处于制造中的半导体器件的最终厚度稍大(比较图7)。例如,在所描述的实施例中深度L可以在100 μm与200 μm之间的范围内。而且,凹进部112的宽度w可以是非常小的。作为所描述的制造方法的结果,获得了小截槽。宽度w可以例如在30 μm与70 μm之间的范围内,例如54 μm。当使用等离子蚀刻时,可以形成具有非常小的宽度w的凹进部112(例如在几微米之间的范围内,特别是5 μm和70 μm)。由于损失了更少的半导体材料,该方法允许从晶片100获得大量电子芯片108。
因此,为了获得图2中示出的结构,实行等离子切割(或等离子切削)过程以用于在正面102上形成凹进部112。这可以通过等离子处理来实现,即以非常柔和但仍然可靠且可再生的方式来实现。通过这种凹进过程,要被单颗化的相邻电子芯片108(参见图5)之间的边界被精确地限定。该过程还可以被称为等离子预切。
参照图3,此处被体现为焊球的导电互连结构114可以被焊接在晶片100的正面102上,更特别地被焊接在其金属结构133上。此处为球形的导电互连结构114的直径B可以例如是190 μm。在金属结构133上焊接导电互连结构114可能涉及到例如260℃的温度。因此,在金属结构133上在过程的当前阶段已经焊接导电互连结构114保护了之后附接的箔型临时支持体104、110(参见图5和图6)免于热损坏。因此,增加了选择用于临时支持体104、110的材料的设计自由度,因为它们的材料不需要一定是一直到焊接温度都是温度稳定的。只要晶片100仍是完整的并且尚未单颗化成电子芯片108,将导电互连结构114附接到金属结构114就还是简单得多(例如,在配准精确度方面)。
为了获得图3中示出的结构,导电互连结构114通过焊接连接到再分配层134。焊球114实现了一方面的要从晶片100单颗化的电子芯片108与另一方面的器件载体192(例如PCB,未示出)之间的焊接连接。将导电互连结构114焊接到再分配层132上的过程也可以被称为球施加(ball apply)。
参照图4,该方法进一步包括:通过向导电互连结构114施加电信号来实行电子功能测试。如可以根据图4所理解的,并且如在那里由箭头185示意性指示的,可以实行对要从晶片100单颗化的电子芯片108的功能进行电子测试。利用该功能测试,可以测试晶片100是否在根据图1到图3的过程期间已经受到损坏。测试设备的针阵列(或针筒)中的针(未示出)可以出于测试目的来接触导电互连结构114。可以施加电激励并且可以测量电响应信号、可以执行漏泄测试等等。相同的测试设备可以被用于所描述的功能测试,其也已经被用于前端测试、从而进一步增加该过程的效率。除了这样的功能测试之外,还可能的是借助于测试设备将数据写入晶片100或各个电子芯片108中。
参照图5,柔性且可变形的第一临时支持体104被连接到凹进的晶片100的正面102,以及被连接到导电互连结构114。因此,在再分配层132上形成导电互连结构114,并且在附接第一临时支持体104之前实行电子测试(参见图4)。此后,晶片100可以成为用于将晶片100从背面106一直减薄到小于300 μm的厚度d的减薄过程的主体,以由此将晶片100单颗化成多个电子芯片108。在这种通过研磨进行的减薄过程期间,晶片100从至少600 μm的初始厚度D被减薄至例如150 μm的最终厚度d。通过研磨进行的减薄在其达到凹进部112的底部表面之前一直持续,从而将多个单个电子芯片108从先前整体的晶片100进行分离或单颗化。
第一临时支持体104通过以下述方式进行压层而附接到凹进的晶片100的正面102,该方式为:导电互连结构114和再分配层134由此被第一临时支持体104覆盖。再分配层134的平面表面被第一临时支持体104以不透液体的方式覆盖,并且导电互连结构114被第一临时支持体104像帐篷一样覆盖。这种覆盖防止导电互连结构114和再分配层134以及下方的半导体结构在研磨期间损坏。研磨过程可能生成磨粉浆,其可能污染或者甚至损坏导电互连结构114和晶片100的集成电路元件(即,其活动区域)。因此,损坏可能由于机械应力和/或浆液的化学影响而产生。有利地,临时支持体104被配置为具有面对导电互连结构114的塑性可变形的或变形的表面部分的柔性薄板。通过施加热和压力,可以触发临时支持体104的塑性变形,这将导电互连结构114嵌入形成于第一临时支持体104内的容纳容积中。通过这种过程,第一临时支持体104被层压到导电互连结构114和再分配层134上。
作为所描述的层压和研磨过程的结果,获得了如图5中示出的中间产品120。中间产品120包括均被再分配层134的一部分和至少一个导电互连结构114所覆盖的多个分离的电子芯片108。第一临时支持体104保持附接到所有现在已分离的电子芯片108和公共的导电互连结构114,并且由此简化了对大量薄的并且因此灵敏的电子芯片108的处置。特别地,导电互连结构114以像帐篷一样的方式嵌入临时支持体104中。在第一临时支持体104与导电互连结构114之间的这种仅轻微的相互作用防止了在之后对第一临时支持体104进行拆分离(参见图6)期间损坏导电互连结构114。
如所提到的,通过对晶片100从背面106进行释放研磨,晶片100被单颗化成多个单独的电子芯片108。然而,在发起这种研磨过程之前,用第一临时支持体104来覆盖图4中示出的结构的正面。作为这种覆盖的结果,导电互连结构114被嵌入第一临时支持体120中来获得可以被良好处置的平面结构。这使得研磨过程更精确。
参照图6,该方法以下述过程继续进行:将电子芯片108从正面102上的第一临时支持体104再次粘附到背面106上的第二临时支持体110。更具体而言,第二临时支持体110首先通过层压连接到经单颗化的晶片100(即,电子芯片108)的背面106。第二临时支持体110可以被配置为粘附到背面106的柔性薄板。此后,可以从电子芯片108移除或拆分第一临时支持体104,例如通过将其剥离。因此,在移除第一临时支持体104之前,第二临时支持体110被附接到背面106。这确保了灵敏的薄的且单独的电子芯片108由临时支持体104、110中的至少一个持续地支撑,从而确保了对它们的保护以及不间断地对它们进行处置的能力。
如由附图标记187示意性指示的,该方法进一步包括通过第二临时支持体110来激光处理经单颗化的晶片100的电子芯片108的背面106。换言之,通过传播通过第二临时支持体110的激光来在电子芯片108的背面106上形成标记。出于该目的,可以选择激光器的波长(例如,在绿色波长范围内进行发射的激光)以使得由该激光器发射的电磁辐射基本上不被第二临时支持体110的材料所吸收。通过采用这种措施,可以实现对背面106进行激光加标,同时电子芯片108保持附接到第二临时支持体110。激光加标可以在作为将晶片100单颗化成电子芯片108的结果而获得的各个半导体器件130的可追溯性方面是有利的。可以在框架上实现激光加标。
作为所描述的制造过程的结果,获得了图6中示出的具有背面标记的非包封式(即,没有模塑化合物或层压包封)半导体器件130。被配置为芯片级封装(CSP封装)的非包封式半导体器件130由以下部分组成:具有150 μm厚度的半导体主体132、半导体主体132的正面102上的导电互连结构114、以及半导体主体132与焊接结构114之间的再分配层134。
参照图7,所描述的制造方法进一步包括:将半导体器件130从第二临时支持体110各个地拆分。更具体而言,从第二临时支持体110各个地拾取半导体器件130(以及因此还有电子芯片108)。这可以通过以下方式来实现:吸引套管177在半导体器件130中的相应一个的正面上施加吸力175(由真空生成),同时释放主体179从电子芯片108中的相应一个的背面将其向上推动(参见推力176)。因此,在此处被体现为吸引套管177的拾取元件能够各个地拾取经单颗化的半导体器件130。在示出的实施例中,拾取元件因此是可以通过真空力拾取半导体器件130中的相应一个的吸盘。所拾取的半导体器件130或电子芯片108然后可以成为带盘式过程(未示出)的主体。
作为对所描述的方法的替换方案,还可能的是,在已经根据图7(而不是根据图6通过第二临时支持体110)拾取了各个半导体器件130之后,出于可追溯性的目的来实行激光加标。
图8到图13示出了根据另一示例性实施例的在实行制造半导体器件130的方法期间所获得的中间产品的截面图。
参照图8,以如上文参照图2所描述的对应的方式在覆盖有再分配层134的晶片100的表面中形成了凹进部112。然而,在图8中示出的实施例中,凹进部112的深度l现在是显著更小的,例如在5 μm至10 μm之间的范围内。可以通过等离子切割或激光开槽来实现凹进部112的形成。可以通过凹进过程来移除可能在晶片100中出现的低k介电层(图8中未示出),以进一步简化之后的刀片切割过程,该刀片切割过程将在下文参照图13进行描述。当在用刀片进行切割之前移除嵌入的低k层时,通过刀片或其他切割元件进行的这种之后的材料机械移除可以更精确地工作。
参照图9,导电互连结构114被焊接在焊盘133上,如上文参照图3所描述的。
参照图10,第一临时支持体104被层压在图9中示出的结构的顶部,如参照图5所图示和描述的。
参照图11,通过研磨将凹进的晶片100的材料从背面106移除,以由此将晶片100减薄至d=150 μm的厚度。根据所描述的实施例,然而,将晶片100单颗化成电子芯片108不再由研磨过程完成,不像根据图5的过程中那样。
可以在根据图12的阶段或者在根据随后图13所描述的阶段处实行对电子芯片108的激光加标。激光加标可以被配置为上文参照图1到图7所描述的那样。
参照图12,以与上文参照图6所描述的类似方式将第二临时支持体110层压在图11中示出的结构的下部主表面上。此后,可以从图11中示出的结构的上部主表面移除第一临时支持体104。
参照图13,然后从现在暴露的正面102移除凹进的晶片100的材料,以由此将晶片100单颗化成多个电子芯片108。可以通过用刀片(未示出)从正面102进行切割来实行这种移除材料的过程。如在图13中示意性指示的,这还可以移除第二临时支持体110的表面材料中的一小部分,以确保单颗化过程被可靠地完成。这可以在凹进部112的位置处在第二临时载体主体110中形成压痕195。作为对刀片切割的替换方案,还可以通过激光烧蚀过程来实现分离。在后者的替换方案中,与等离子蚀刻一样,激光允许基本上任何自由可选择的芯片形状(诸如圆形、三角形等等)。
参照图11和图13,所描述的方法因此通过首先将晶片100从背面106减薄,之后通过从正面102在凹进部112处对材料进行随后的选择性移除,来将晶片100单颗化成多个电子芯片108。
图14示出了根据示例性实施例的电子器件190的截面图。电子器件190由芯片级封装和印刷电路板(PCB)组成,该芯片级封装被体现为表面安装非包封式半导体器件130,以及该印刷电路板被体现为用于承载半导体器件130的器件载体192。通过导电互连结构114来实现半导体器件130与器件载体192之间的电耦合和机械耦合,该导电互连结构114将焊盘133与板状器件载体192的暴露顶部主表面上的器件载体焊盘155进行互连。
应当注意的是,术语“包括”不排除其他元件或功能,以及“一个”或“一”不排除多个。并且与不同实施例相关联地描述的元件可以被组合。还应当注意的是,附图标记不应当被理解为限制权利要求的范围。此外,本申请的范围不意图被限制到说明书中所描述的过程、机器、制造、以及物质组成、装置、方法和步骤的特定实施例。因此,所附权利要求意图将这样的过程、机器、制造、物质组成、装置、方法或步骤包括在权利要求的范围内。
Claims (22)
1.一种制造方法,其包括:
·在晶片(100)的正面(102)中形成凹进部(112);
·将第一临时支持体(104)连接到凹进的晶片(100)的所述正面(102);
·此后将所述晶片(100)从背面(106)减薄;
·将第二临时支持体(110)连接到所述背面(106);
·此后移除所述第一临时支持体(104)。
2.根据权利要求1所述的方法,其中所述方法包括:从所述正面(102)和所述背面(106)中的至少一个移除所述凹进的晶片(100)的材料,以由此将所述晶片(100)单颗化成多个电子芯片(108)。
3.根据权利要求1或2所述的方法,其中所述方法进一步包括:在将所述第一临时支持体(104)连接到所述凹进的晶片(100)的所述正面(102)以及连接到导电互连结构(114)之前,将所述导电互连结构(114)附接在所述晶片(100)的所述正面(102)上。
4.根据权利要求3的任一项所述的方法,其中所述方法进一步包括由以下各项组成的组中的至少一项:在将所述第一临时支持体(104)连接到所述凹进的晶片(100)的所述正面(102)以及连接到所述导电互连结构(114)之前,通过向所述导电互连结构(114)施加电信号来实行对所述晶片(100)的功能测试以及将数据写入所述晶片(100)中。
5.根据权利要求1至4中的任一项所述的方法,其中所述方法进一步包括:通过所述第二临时支持体(110)来激光处理所述背面(106)。
6.一种制造方法,其包括:
·在晶片(100)的正面(102)中形成凹进部(112);
·将导电互连结构(114)附接在所述晶片(100)的所述正面(102)上;
·将第一临时支持体(104)连接到凹进的晶片(100)的所述正面(102),并且将所述导电互连结构(114)嵌入所述第一临时支持体(104)中;
·此后将所述晶片(100)单颗化成多个电子芯片(108)。
7.根据权利要求6所述的方法,其中所述方法包括:通过将所述晶片(100)从背面(106)至少一直减薄至所述凹进部(112)来将所述晶片(100)单颗化成所述多个电子芯片(108)。
8.根据权利要求6所述的方法,其中所述方法包括:通过将所述晶片(100)从背面(106)减薄,之后从所述正面(102)移除在所述凹进部(112)处的材料,来将所述晶片(100)单颗化成所述多个电子芯片(108)。
9.根据权利要求6至8中的任一项所述的方法,其中所述方法进一步包括:在移除所述第一临时支持体(104)之前,将第二临时支持体(110)连接到背面(106)。
10.根据权利要求9所述的方法,其中所述第二临时支持体(110)被配置为柔性薄板。
11.根据权利要求9或10所述的方法,其中所述方法进一步包括:从所述第二临时支持体(110)各个地拆分所述电子芯片(108)。
12.一种制造方法,其包括:
·在晶片(100)的正面(102)中形成凹进部(112);
·将临时支持体(104)连接到凹进的晶片(100)的所述正面(102);
·此后将所述晶片(100)从背面(106)一直减薄至小于300 μm的厚度。
13.根据权利要求12所述的方法,其中所述方法包括:特别是通过由减薄过程和切割过程组成的组中的至少一个来将所述晶片(100)单颗化成多个电子芯片(108)。
14.根据权利要求12或13所述的方法,其中将所述晶片(100)从至少600 μm的初始厚度(D)减薄至不多于200 μm的最终厚度(d)。
15.根据权利要求13或14所述的方法,其中所述方法进一步包括:将所述电子芯片从所述临时支持体(104)再次粘附到所述背面(106)上的另一临时支持体(110)。
16.一种中间产品(120),其包括:
·多个电子芯片(108);
·在所述电子芯片(108)中的每个上的至少一个焊接结构(114);
·在所述电子芯片(108)和导电互连结构(114)上的公共临时支持体(104)。
17.根据权利要求16所述的中间产品(120),其中所述导电互连结构(114)被嵌入所述临时支持体(104)中,以使得当将所述临时支持体(104)从所述电子芯片(108)拆分时,所述导电互连结构(114)保持附接在所述电子芯片(108)上。
18.根据权利要求16或17所述的中间产品(120),其中所述电子芯片(108)具有不多于200 μm的厚度(d)。
19.根据权利要求16至18中的任一项所述的中间产品(120),其中所述临时支持体(104)被配置为具有面对所述至少一个焊接结构(114)和所述电子芯片(108)的塑性可变形的或变形的表面部分的柔性薄板。
20.一种非包封式半导体器件(130),其包括:
·半导体主体(132),其具有不多于200 μ m的厚度(d);
·至少一个焊接结构(114),其在所述半导体主体(132)的正面(102)上;
·再分配层(134),其在所述半导体主体(132)与所述至少一个焊接结构(114)之间。
21.根据权利要求20所述的半导体器件(130),其被配置成芯片级封装。
22.一种电子器件(190),其包括:
·器件载体(192);以及
·根据权利要求20或21的安装在所述器件载体(192)上的非包封式半导体器件(130)。
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DE102016103585B4 (de) * | 2016-02-29 | 2022-01-13 | Infineon Technologies Ag | Verfahren zum Herstellen eines Package mit lötbarem elektrischen Kontakt |
US11841803B2 (en) | 2019-06-28 | 2023-12-12 | Advanced Micro Devices, Inc. | GPU chiplets using high bandwidth crosslinks |
US11507527B2 (en) | 2019-09-27 | 2022-11-22 | Advanced Micro Devices, Inc. | Active bridge chiplet with integrated cache |
US20210098419A1 (en) * | 2019-09-27 | 2021-04-01 | Advanced Micro Devices, Inc. | Fabricating active-bridge-coupled gpu chiplets |
US11232622B2 (en) | 2019-11-27 | 2022-01-25 | Advanced Micro Devices, Inc. | Data flow in a distributed graphics processing unit architecture |
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