CN108390358A

CN108390358A - Electrical integrated form controller

Info

Publication number: CN108390358A
Application number: CN201810300387.0A
Authority: CN
Inventors: 朱志浩; 黄迪; 潘祥; 乔晓葳; 顾昕华; 樊响; 唐亮; 黎侠
Original assignee: Shenyang (shanghai) Intelligent System Research And Design Co Ltd
Current assignee: Shenyang (shanghai) Intelligent System Research And Design Co Ltd
Priority date: 2018-04-04
Filing date: 2018-04-04
Publication date: 2018-08-10
Anticipated expiration: 2038-04-04
Also published as: CN108390358B

Abstract

The present invention provides a kind of electrical integrated form controller, including：FPGA integrated circuit boards are integrated on the FPGA integrated circuit boards：Bus communication circuitry, for being communicated with external control devices；Multi-way switching values input circuit, the On-off signal state for reading each output switch parameter equipment；Multi-way switching values output circuit, for controlling each On-off signal equipment to each On-off signal equipment input switch amount；Multichannel optocoupler secondary side output loop circuit, for to each signal circuit equipment output loop signal to control the state of each signal circuit equipment；Driving circuit, for being connected with multiple driven equipments, for driving each driven equipment operation；Power supply circuit, include the independently-powered circuit powered for FPGA integrated circuit boards and be above-mentioned each circuit power supply multiple power supply sub-circuits.The present invention has high electrical integrated, high reliability, high maintenance, inexpensive advantage.

Description

Electrical integrated form controller

Technical field

The present invention relates to Industry Control and automatic field, more particularly to numerically-controlled machine tool and its technical field of automation, Specially a kind of electrical integrated form controller.

Background technology

CNC machine and the function of automatic machining tool realize that needing dependence to improve reliable electric automatization equipment gives Take on.It is widely used in industry at present：PLC controller+discrete electromechanical movement device (such as relay, contactor etc.)+discrete The mode of rigid line connection constitutes relevant electric automatization functional circuit, but in the application of scale, so passes System scheme, which has the following problems, to be difficult to solve：

1) conventional electrical scheme is connected using discrete movement device and rigid line, relies primarily on live manual routing and hand Work is installed, and can not ensure the integrity of live manual work by the means of automated production and detection, in reality, there is It the problems such as a considerable amount of rigid line wrongs, cruelty construction and finally finished product electric property can not be completely the same equal, is easy to lead Cause is got half the result with twice the effort.

2) using traditional electrical arrangement in large-scale production, a large amount of manpowers is needed to execute handwork；It debugs open-minded The working hour that process occupies is also long, can not often take on without the worker tightly trained.This is in labor cost height enterprise Instantly, more burdens can be brought to enterprise.

3) it is held after sale in market, means there is large-scale electrical equipment and phase using the machine tool of conventional electrical scheme Connection wiring needs site examining and repairing to safeguard, difficulty and manpower costs well imagine.

4) with higher level technology development needs such as the development of control technology and industry 4.0, Machine Tools Electric system needs More on-site parameters, signal are acquired, state ... is performed simultaneously more fine actions and control law, these work are adopted It is increasingly difficult to realize with traditional electrical arrangement, complicated in disorder field condition will more deteriorate originally.

Those skilled in the art are seeking a kind of scheme and are going to solve problem above.

Invention content

In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of electrical integrated form controller, For solving, maintenance low to the auto-control degree of CNC machine and automatic machining tool and control difficulty in the prior art Big problem.

In order to achieve the above objects and other related objects, the present invention provides a kind of electrical integrated form controller, including：FPGA Integrated circuit board is integrated on the FPGA integrated circuit boards：Bus communication circuitry, for being led to external control devices Letter；Driving circuit, for being connected with multiple driven equipments, for driving each driven equipment operation；Power supply circuit, packet It includes the independently-powered circuit powered for the FPGA integrated circuit boards and is multiple power supply sub-circuits of above-mentioned each circuit power supply.

In one embodiment of the invention, the bus communication circuitry includes：Set on the place of the FPGA integrated circuit boards Reason device in for communicated with the external control devices the soft cores of communication IP, be set to the FPGA integrated circuit boards on and with The soft nuclear phases of communication IP communication input interface even communicates output interface and is connected to the communication input interface, described Communicate the telecommunication circuit between output interface and the external control devices.

In one embodiment of the invention, the telecommunication circuit includes：Communication physical layer chip, with the integrated electricity of the FPGA The communication input interface on the plate of road is connected with the communication output interface；Network transformer, with the communication physical layer core Piece is connected, and is isolated and is converted for the signal of communication to the communication physical layer chip；Communication interface becomes with the network Depressor is connected with the external control devices, for being communicated with the external control devices.

In one embodiment of the invention, the electrical integrated form controller further includes being integrated in the FPGA integrated circuits On plate：Multi-way switching values input circuit reads each output switch parameter and sets for being connected with multiple switch amount output equipment Standby On-off signal state；Multi-way switching values output circuit described is opened to each for being connected with multiple switch amount input equipment Input equipment input switch amount is measured to control each On-off signal equipment in pass；Multichannel optocoupler secondary side output loop circuit, For being connected with multiple signal circuit equipment, returned to each signal circuit equipment output loop signal with controlling each signal The state of pipeline equipment.

In one embodiment of the invention, include per the switching value input circuit described all the way：Photoelectrical coupler, for being isolated With the conditioning On-off signal signal；Wherein, the photoelectrical coupler has receiving terminal and transmission terminal；The receiving terminal The corresponding On-off signal signal for being connected and reading each output switch parameter equipment with the output switch parameter equipment of son；It is described Transmission terminal is connected with the processor of the FPGA integrated circuit boards, described in after the photoelectric coupler isolation and conditioning On-off signal signal transmission to the FPGA integrated circuit boards processor.

In one embodiment of the invention, include per the switching value output circuit described all the way：Solid-state relay is used for basis The On-off signal signal generates the driving control signal for driving the On-off signal equipment；Wherein, the solid-state relay Utensil has receiving terminal and leading-out terminal；The receiving terminal is connected with the processor of the FPGA integrated circuit boards, receives institute State the digital output modul signal of processor output；The leading-out terminal is connected with the On-off signal equipment, and being used for will be described The driving control signal that solid-state relay generates is input to the On-off signal equipment to control the On-off signal Equipment.

In one embodiment of the invention, include per the secondary side output loop circuit described all the way：Buffer, and it is described The processor of FPGA integrated circuit boards is connected, and receives the loop control signal of the processor output；Photoelectrical coupler, have with What the connected primary side connecting pin of the buffer and tool were formed into a loop there are two leading-out terminal and with the signal circuit equipment Secondary side connecting pin.

In one embodiment of the invention, the driving circuit includes：Single phase ac electric drive circuit and three-phase alternating current Driving circuit.

In one embodiment of the invention, the single phase ac electric drive circuit includes：Switching circuit, single-phase electric drive electricity Road, overload detection circuit and logic control circuit；The switching circuit is connected with the processor of the FPGA integrated circuit boards, The enable signal exported according to the processor of the FPGA integrated circuit boards is turned on and off；The overload detection circuit point It is not connected with the driven equipment and the logic control circuit, detects whether the driven equipment occurs overload and will examine The detection the signal whether driven equipment measured overloads is exported to the logic control circuit；The logic control Circuit is connected with the overload detection circuit and the single-phase electric drive circuit respectively, is generated and is driven according to the enabled control signal in outside The enabled drive signal of the dynamic driven equipment operating simultaneously exports the enabled drive signal to the single-phase electric drive electricity Road, while stopping exporting to the single-phase electric drive circuit according to the overload detection signals received from the overload detection circuit The enabled drive signal；Single-phase electric drive circuit is connected with the switching circuit and the driven equipment respectively, from institute It states logic control circuit and receives the enabled drive signal and generate driving when the switching circuit is connected and described driven The singlephase drive signal of equipment operation stops driving the driven equipment fortune when not receiving the enabled drive signal Row.

In one embodiment of the invention, the overload detection circuit includes：Current sensor, with the driven equipment It is connected, detects the electric current in the driven equipment；Comparator, respectively with the current sensor and the logic control circuit It is connected, the electric current that the current sensor detects is compared with default overload protection electric current, if the current sensor is examined The electric current of survey is more than or equal to default overload protection electric current, then output overloading detects signal to the logic control circuit, if described The electric current of current sensor detection is less than default overload protection electric current, then exports non-overload detection signals to logic control electricity Road.

In one embodiment of the invention, the single-phase electric drive circuit include silicon-controlled photoelectrical coupler and with it is described can Control the triode ac switch of silicon photoelectrical coupler connection.

In one embodiment of the invention, the three-phase alternating current electric drive circuit includes：Switching circuit, three-phase electric drive electricity Road, overload detection circuit and logic control circuit；The switching circuit is connected with the processor of the FPGA integrated circuit boards, The enable signal exported according to the processor of the FPGA integrated circuit boards is turned on and off；The overload detection circuit point It is not connected with the driven equipment and the logic control circuit, detects whether the driven equipment occurs overload and will examine The detection the signal whether driven equipment measured overloads is exported to the logic control circuit；The logic control Circuit is connected with the overload detection circuit and the three-phase electric drive circuit respectively, is generated and is driven according to the enabled control signal in outside The enabled drive signal of the dynamic driven equipment operating simultaneously exports the enabled drive signal to three-phase electric drive electricity Road, while stopping exporting to the three-phase electric drive circuit according to the overload detection signals received from the overload detection circuit The enabled drive signal；The three-phase electric drive circuit is connected with the switching circuit and the driven equipment respectively, It receives the enabled drive signal from the logic control circuit and is generated when the switching circuit is connected and drive the quilt The three-phase driving signal of driving equipment operation stops driving the driven equipment when not receiving the enabled drive signal Operation.

In one embodiment of the invention, the overload detection circuit includes：First current sensor, the second current sense Device and third current sensor connect wires with the three-phase of driven equipment described in three-phase be connected respectively, and detection is described to be driven Electric current in equipment；First comparator, the second comparator and third comparator, respectively with first current sensor, institute It states the second current sensor and the third current sensor corresponds to and is connected, and be connected with the logic control circuit, will divide The electric current that each current sensor detects Dui Ying be compared with default overload protection electric current, if the current sensor detects Electric current be more than or equal to default overload protection electric current, then output overloading detects signal to the logic control circuit, if the electricity The electric current of flow sensor detection is less than default overload protection electric current, then exports non-overload detection signals to logic control electricity Road.

In one embodiment of the invention, the three-phase electric drive circuit includes three to be connected respectively with the switching circuit A controllable silicon drive circuit, each described controllable silicon drive circuit include silicon-controlled photoelectrical coupler and with the silicon-controlled light The triode ac switch of electric coupler connection.

In one embodiment of the invention, the electrical integrated form controller further includes：Ic for energy metering, and is described The three phase mains of FPGA integrated circuit boards power supply is connected, for the power consumption of the FPGA integrated circuit boards and each circuit into Row metering；The ic for energy metering includes：Current Mutual Inductance circuit, with the three phase mains powered for the FPGA integrated circuit boards Power input be connected, for induction power supply input terminal per phase current value；Voltage modulate circuit is integrated with for the FPGA The power input of the three phase mains of circuit board power supply is connected, and for acquiring the power input, to be input to the FPGA integrated Every phase voltage value of circuit board；Electric energy computation chip, respectively with the Current Mutual Inductance circuit, the voltage modulate circuit and institute The processor for stating FPGA integrated circuit boards is connected, and electricity is improved according to the current value of the Current Mutual Inductance circuit inductance and the voltage The voltage value that road obtains measures corresponding power consumption data, and the power consumption data of metering is sent to the FPGA The processor of integrated circuit board；The external control devices are by the bus communication circuitry from the FPGA integrated circuit boards Processor obtains the power consumption data.

In one embodiment of the invention, the ic for energy metering is three-phase four-wire system, the Current Mutual Inductance circuit packet Include the first current transformer, the second current transformer and third current transformer, respectively with for the FPGA integrated circuit boards It is connected with the three-phase connecting pin of the three phase mains of each circuit power supply；The voltage modulate circuit include first resistor pressure divider circuit, Second resistance pressure divider circuit and 3rd resistor pressure divider circuit, respectively with for the FPGA integrated circuit boards and each circuit power supply The three-phase connecting pin of three phase mains is connected.

In one embodiment of the invention, the electric energy computation chip has voltage acquisition channel and current acquisition channel.

In one embodiment of the invention, the electrical integrated form controller further includes：Three-phase alternating current pile defection electricity Road is connected with the three-phase alternating current input port of the FPGA integrated circuit boards, and the integrated electricity of the FPGA is input to for detecting Three-phase alternating current in the plate of road whether phase shortage；The three-phase alternating current lack detection circuit includes：Detection circuit, for detecting three The input of phase alternating current；Phase shortage decision circuitry, for judging whether the three-phase alternating current lacks according to the input of three-phase alternating current Phase.

In one embodiment of the invention, the detection circuit includes：First photoelectrical coupler, the second photoelectrical coupler with And third photoelectrical coupler, it is connected respectively with the three-phase connecting pin of three-phase alternating current and is connected in input AC electricity；It is described to lack Phase decision circuitry includes：First comparator, the second comparator, third comparator, the 4th comparator, field-effect transistor, capacitance, 4th photoelectrical coupler；The first comparator, second comparator, the third comparator input terminal respectively it is corresponding with First photoelectrical coupler, second photoelectrical coupler and the third photoelectrical coupler are connected, output end with it is described The grid of field-effect transistor is connected；The both ends of the capacitance are connected with the source electrode and drain electrode of the field-effect transistor respectively； The drain electrode of the field-effect transistor connects the electrode input end of the 4th comparator；The output end of 4th comparator with 4th photoelectrical coupler is connected.

In one embodiment of the invention, output end and the FPGA integrated circuit boards of the 4th photoelectrical coupler Processor is connected, by whether the detection signal of phase shortage is exported to the processor of the FPGA integrated circuit boards；The external control Equipment by the bus communication circuitry, from described in the acquisition of the processor of the FPGA integrated circuit boards, whether believe by the detection of phase shortage Number.

In one embodiment of the invention, the independently-powered circuit includes：With the processing of the FPGA integrated circuit boards Low pressure difference linear voltage regulator device connected adjusting and voltage-reduction switch power supply chip and be connected with the adjusting and voltage-reduction switch power supply chip.

In one embodiment of the invention, the pin of the adjusting and voltage-reduction switch power supply chip and the FPGA integrated circuit boards Processor power pins between be connected with decoupling capacitor.

In one embodiment of the invention, the electrical integrated form controller further includes being integrated in the FPGA integrated circuits On plate：Clock input circuit, the processor for the FPGA integrated circuit boards provide work clock；Program configuration circuit, will The configuration data of the FPGA integrated circuit boards is loaded into the FPGA from nonvolatile external memory Flash or EEPROM and integrates In circuit board；Debugging interface circuit, the processor for the FPGA integrated circuit boards provide debugging interface；RAM chip is extended out, is The FPGA integrated circuit boards provide external memory space.

As described above, the present invention relies on FPGA integrated circuit boards, by traditional scheme controller, discrete movement device, Connection three functional units of rigid line are integrated on FPGA integrated circuit boards, based on the high processing speed of FPGA integrated circuit boards and A large amount of internal I/O resource and by the way of network communication, can carry a large amount of sensor resource, can be to high-rise MES The state and fault message of System Reports various field：State including the machine itself and failure, and the present invention is also pre- simultaneously Communication/the control interface for having stayed industrial robot, can arrange in pairs or groups third-party industrial machine person cooperative work, realize higher degree Factory automation, in addition, the present invention can be with main control room or host computer forming control system and the sensing for completing industry spot Device is matched with operator signals, has high electrical integrated, high reliability, high maintenance, inexpensive advantage.

Description of the drawings

Fig. 1 is shown as the functional block diagram of the electrical integrated form controller of the present invention.

Fig. 2 and Fig. 3 is respectively indicated as a kind of concrete principle block diagram of the electrical integrated form controller of the present invention.

Fig. 4 is shown as the signal of communication physical layer chip in the bus communication circuitry of the electrical integrated form controller of the present invention Figure.

Fig. 5 is shown as the theory structure of network transformer in the bus communication circuitry of the electrical integrated form controller of the present invention Figure.

Fig. 6 is shown as in the electrical integrated form controller of the present invention principle assumption diagram of switching value input circuit all the way.

Fig. 7 is shown as in the electrical integrated form controller of the present invention principle assumption diagram of switching value output circuit all the way.

Fig. 8 is shown as in the electrical integrated form controller of the present invention theory structure of secondary side output loop circuit all the way Figure.

Fig. 9 is shown as the principle schematic of single phase ac electric drive circuit in the electrical integrated form controller of the present invention.

Figure 10 is shown as the particular circuit configurations of single phase ac electric drive circuit in the electrical integrated form controller of the present invention Figure.

Figure 11 is shown as the principle schematic of three-phase alternating current electric drive circuit in the electrical integrated form controller of the present invention.

Figure 12 is shown as the particular circuit configurations of three-phase alternating current electric drive circuit in the electrical integrated form controller of the present invention Figure.

Figure 13 is shown as the circuit structure diagram of ic for energy metering in the electrical integrated form controller of the present invention.

Figure 14 is shown as the circuit structure of three-phase alternating current lack detection circuit in the electrical integrated form controller of the present invention Figure.

Figure 15 is shown as the circuit structure diagram of independently-powered circuit in the electrical integrated form controller of the present invention.

Figure 16 is shown as the circuit structure diagram of 12V power supplies sub-circuit in the electrical integrated form controller of the present invention.

Figure 17 is shown as the circuit structure diagram of 5V power supplies sub-circuit in the electrical integrated form controller of the present invention.

Figure 18 is shown as the circuit structure diagram of clock input circuit in the electrical integrated form controller of the present invention.

Figure 19 is shown as the circuit structure diagram of the electrical integrated form controller Program configuration circuit of the present invention.

Figure 20 is shown as the circuit structure diagram of debugging interface circuit in the electrical integrated form controller of the present invention.

Figure 21 is shown as extending out the circuit structure diagram of RAM chip in the electrical integrated form controller of the present invention.

Component label instructions

100 FPGA integrated circuit boards

110 bus communication circuitries

111 communication physical layer chips

112 network transformers

120 multi-way switching values input circuits

121 photoelectrical couplers

130 multi-way switching values output circuits

131 solid-state relays

140 multichannel optocoupler secondary side output loop circuits

141 buffers

142 photoelectrical couplers

150 driving circuits

151 single phase ac electric drive circuits

1511 switching circuits

1512 single-phase electric drive circuits

1513 overload detection circuits

1514 logic control circuits

152 three-phase alternating current electric drive circuits

1521 switching circuits

1522 three-phase electric drive circuits

1523 overload detection circuits

1524 logic control circuits

160 power supply circuits

161 independently-powered circuits

162 12V power supply sub-circuits

163 5V power supply sub-circuits

170 ic for energy metering

180 three-phase alternating current lack detection circuits

190 clock input circuits

1100 program configuration circuits

1110 debugging interface circuits

1120 extend out RAM chip

Specific implementation mode

Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that in the absence of conflict, following embodiment and implementation Feature in example can be combined with each other.

It please refers to Fig.1 to Figure 21.It should be clear that structure, ratio, size etc. depicted in this specification institute accompanying drawings, are only used To coordinate the revealed content of specification, so that those skilled in the art understands and reads, being not limited to the present invention can The qualifications of implementation, therefore do not have technical essential meaning, the tune of the modification of any structure, the change of proportionate relationship or size It is whole, in the case where not influencing the effect of present invention can be generated and the purpose that can reach, should all still fall in disclosed skill Art content obtains in the range of capable of covering.Meanwhile in this specification it is cited as "upper", "lower", "left", "right", " centre " and The term of " one " etc. is merely convenient to being illustrated for narration, rather than to limit the scope of the invention, relativeness It is altered or modified, in the case where changing technology contents without essence, when being also considered as the enforceable scope of the present invention.

The purpose of the present embodiment is that a kind of electrical integrated form controller is provided, for solving in the prior art to CNC machines Bed it is low with the auto-control degree of automatic machining tool, maintenance and the big problem of control difficulty.Described in detail below hair The principle and embodiment of bright electrical integrated form controller, makes those skilled in the art not need creative work and is appreciated that The electrical integrated form controller of the present invention.

The present embodiment relies on FPGA device, using large-scale integrated circuit and PCBA Surface Mount technologies, by traditional scheme In controller, discrete movement device, connection three functional units of rigid line be integrated into as possible inside a power electronic equipment, this sets The standby Electronic Assemblies technique productions using automatic patch can be done directly the automation patch assembling of PCBA in manufacturing works And automatic test, pass through the inspection and examination of automatic detection program when whole set equipment dispatches from the factory, it is ensured that go out plant Consistency and integrity.At the scene that lathe etc. finally uses, the electrical integrated form controller of the present embodiment only needs simply to hang Installation is carried, the power cable and necessary power supply/network/bus communication cable of motor are connected, in addition i.e. without other scenes Installation and wiring work.After installation is complete, function is opened in the included debugging of equipment itself, and the function is protected with basic function Shield, can effectively prevent misconnection and feed back possible fault message, and field worker can carry out energization tune after reading handbook Runin is logical, without complicated technical training.

At the same time, have benefited from the high processing speed of FPGA device and a large amount of internal I/O resource and led to using network The electrical integrated form controller of the mode of letter, the present embodiment can carry a large amount of sensor resource, can be to high-rise MES systems State and fault message --- the state including the machine itself and the failure of system report various field；On the other hand, the present invention is same When also reserved communication/control interface of industrial robot, can arrange in pairs or groups this enterprise or third-party industrial robot collaboration work Make, realizes the factory automation of higher degree.

The present embodiment provides for industry with automation control especially numerically-controlled machine tool control a kind of high electrical integrated, high Reliability, high maintenance, it is inexpensive, can with main control room or host computer forming control system and complete industry spot Sensor and the matched electrical integrated form industrial control unit (ICU) of operator signals.Referring to Fig. 1, being shown as electrically collecting in the present invention The functional block diagram of accepted way of doing sth controller.As shown in Figure 1, the electrical integrated form controller includes：FPGA integrated circuit boards 100 are Interacted with the various kinds of equipment in numerically-controlled machine tool and its automatic control system, FPGA integrated circuit boards 100 up to It has been integrated in less：Bus communication circuitry 110, driving circuit 150 and power supply circuit 160.

It please refers to Fig.1 to Fig.3, the electrical integrated form controller of the present embodiment is described in detail according to Fig. 1 to Fig. 3.

In this present embodiment, using 100 framework of FPGA integrated circuit boards, function wiring is substantially zeroed, relative to tradition from Hundreds of physical circuit connection can be reduced by dissipating formula electrical arrangement, simplify cumbersome electrical assembly and layout.

The main function of FPGA (field programmable gate array) integrated circuit board：Integrated circuit board is soft by integrated IP Core constitutes communication and control function of the slave station system realization of EtherCAT industrial field bus with host computer main website, described FPGA integrated circuit boards 100 are by the data of the On-off signal signal of the slave station system acquisition industry spot of composition and pass through work Industry fieldbus is transferred to host computer main website, and host computer main website carries out the processing and simultaneously of control algolithm according to collected information Various control information control digital output signals, photoelectrical coupler secondary side can be sent to the FPGA integrated circuit boards 100 The state of output signal, triode ac switch exchange electricity output.

The most prominent feature of electrical integrated form controller is in numerically-controlled machine tool or automatic control system in the present embodiment Electrical resources highly integrated, the electrical composition of simplified control system, promote numerically-controlled machine tool and its automate industry product Industrial competition.EP4CE30F23C8 in the present embodiment in IV Series FPGAs of Cyclone of specifically used altera corp, Internal resource is quite abundant, and frequency is high, and delay is small, while having stability high, and good reliability is at low cost, field-programmable And the advantage that extended capability is strong, operation industrial field bus system is carried based on it and realize the acquisition of industrial field data with Control has the characteristics that high reliability, highly integrated and inexpensive.

In this present embodiment, the bus communication circuitry 110 with external control devices for being communicated.Wherein, described External control devices are preferably host computer, or the controller in main control room, main control platform.The bus communication electricity Road 110 is for realizing EtherCAT Industrial Ethernet bus communication functions, for being communicated and being controlled with host computer main website.

In this present embodiment, the bus communication circuitry 110 includes：Set on the processing of the FPGA integrated circuit boards 100 In device for communicated with the external control devices the soft cores of communication IP, be set to the FPGA integrated circuit boards 100 on and The soft nuclear phases of IP communication input interface even is communicated, output interface is communicated and is connected to the communication input interface, institute with described State the telecommunication circuit between communication output interface and the external control devices.

Wherein, as shown in Figure 4 and Figure 5, the telecommunication circuit includes：Communication physical layer chip 111, network transformer 112 And communication interface.

In this present embodiment, the communication physical layer chip 111 and the communication on the FPGA integrated circuit boards 100 Input interface is connected with the communication output interface；The network transformer 112 is connected with the communication physical layer chip 111, It is isolated and is converted for the signal of communication to the communication physical layer chip 111；Communication interface, with the network transformer 112 are connected with the external control devices, for being communicated with the external control devices.

Wherein, the catenation principle at port communications input interface (ends EtherCAT bus communication IN) and the telecommunication circuit It is as follows：

EtherCAT communication by host computer main website send EtherCAT data frames read and write slave station equipment internal storage region Lai It realizes.EtherCAT only supports the ethernet physical layer PHY devices of MII (Management Interface) interface on hardware, In order to reduce processing and Forwarding Latency, it is desirable that the sound of the detection loss of link of PHY (physical layer physical layers) device It is less than 15us between seasonable and is preferably provided with the auto-negotiation functionality of baud rate and full duplex, the mono- power supplies of 3.3V.Such as Fig. 3 institutes Show, the communication physical layer chip 111 selects DP83848PHY physical chips, meets the ports pair above-mentioned EtherCAT communication IN The requirement of PHY devices.MII interface signals PHY0_RX0, PHY0_RX1, PHY0_RX2, PHY0_RX3, RX_DV0, RX_ERR0, PHY0_TX0、PHY0_TX1、PHY0_TX2、PHY0_TX3、TX_ENA0、LINK_MII0、MI_DATA、MI_CLK、PHY_RST、 IP_MII_TX_CLK0_in, IP_MII_RX_CLK0_in are connected with FPGA interface, and DP83848 exports PHY0_TX+, PHY0_ TX- differential pairs send signal and PHY0_RX+, PHY0_RX- differential pair and receive signal, and with 112 phase of network transformer in Fig. 5 Connection, network transformer 112 plays the role of electrical isolation, by network transformer 112 be converted into TX0+, TX0-, RX0+, RX0- simultaneously passes through the ports RJ45 correspondence with foreign country.

The catenation principle of the port communications output interface (EtherCAT bus communication OUT terminals mouth) and the telecommunication circuit is such as Under：

EtherCAT communication by host computer main website send EtherCAT data frames read and write slave station equipment internal storage region Lai It realizes.EtherCAT only supports the ethernet physical layer PHY devices of MII (Management Interface) interface on hardware, In order to reduce processing and Forwarding Latency, it is desirable that be less than 15us and best to the response time of the detection loss of link of PHY devices Auto-negotiation functionality with baud rate and full duplex, the mono- power supplies of 3.3V.As shown in figure 4, the communication physical layer chip 111 select DP83848PHY physical chips, meet requirement of the above-mentioned EtherCAT communications OUT terminal mouth to PHY devices.MII connects Message PHY1_RX0, PHY1_RX1, PHY1_RX2, PHY1_RX3, RX_DV1, RX_ERR1, PHY1_TX0, PHY1_TX1, PHY1_TX2、PHY1_TX3、TX_ENA1、LINK_MII1、MI_DATA、MI_CLK、PHY_RST、IP_MII_TX_CLK1_in、 IP_MII_RX_CLK1_in is connected with FPGA interface, and DP83848 exports PHY1_TX+, PHY1_TX- differential pair and sends signal Signal is received with PHY1_RX+, PHY1_RX- differential pair, and is connected with the network transformer 112 in Fig. 5, network transformer 112 play the role of electrical isolation, are converted into TX1+, TX1-, RX1+, RX1- by network transformer 112 and by the ends RJ45 Port communications.

As shown in Figures 2 and 3, the electrical integrated form controller further includes being integrated on the FPGA integrated circuit boards 's：Multi-way switching values input circuit 120, multi-way switching values output circuit 130 and multichannel optocoupler secondary side output loop circuit 140。

In this present embodiment, the multi-way switching values input circuit 120 is read for being connected with multiple switch amount output equipment Take the On-off signal state of each output switch parameter equipment.Such as the multi-way switching values input circuit 120 provides 33 tunnels Industry spot On-off signal signal, the various On-off signal states for reading industry spot.

In this present embodiment, as shown in fig. 6, including per the switching value input circuit described all the way：Photoelectrical coupler 121 is used In being isolated and improve the On-off signal signal；Wherein, the photoelectrical coupler 121 has receiving terminal and transmission terminal； The receiving terminal correspond to be connected with the output switch parameter equipment and read each output switch parameter equipment switching value it is defeated Enter signal；The transmission terminal is connected with the processor of the FPGA integrated circuit boards 100, will be through the photoelectrical coupler 121 Isolation and conditioning after the On-off signal signal transmission to the FPGA integrated circuit boards 100 processor.

As shown in fig. 6, only representing connection and the realization principle of first via switching value input circuit in Fig. 6.Switching value is defeated Enter 33 road 0V or 24V voltage input signal DI1~DI33 concatenation 3.3K resistance that external terminal is attracted from industry spot to be followed by The anode of photoelectrical coupler 121ACPL-214, access COM0~COM2's is public after the cathode of photoelectrical coupler 121ACPL-214 Port can be compatible with the two kinds of sensor signals of NPN and PNP in this way.

The corresponding pin DIN0_0~DIN2_6 of On-off signal.If corresponding pin is high level, the FPGA is integrated It is 1 that the processor (i.e. fpga core main control unit) of circuit board 100, which reads corresponding positions,；If corresponding pin is low level, read It is 0 to take corresponding positions.By photoelectrical coupler 121 (model ACPL-214 shown in Fig. 5), by 33 way switch amount input signals with The ground GND of the processor (i.e. fpga core main control unit) of the FPGA integrated circuit boards 100, eliminates connection electrically System, realizes the isolation of On-off signal, enhances the hardware anti-interference performance of controller.

In this present embodiment, the multi-way switching values output circuit 130 is used to be connected with multiple switch amount input equipment, to Each On-off signal equipment input switch amount is to control each On-off signal equipment.Such as the multi-way switching values are defeated Go out circuit 130 and 16 tunnel industry spot switching value output signals are provided, for directly driving various solenoid valves in industry spot etc. Equipment.

In this present embodiment, as shown in fig. 7, including per the switching value output circuit described all the way：Solid-state relay 131 is used In the driving control signal for generating the driving On-off signal equipment according to the On-off signal signal；Wherein, described solid State relay 131 has receiving terminal and leading-out terminal；The processor of the receiving terminal and the FPGA integrated circuit boards 100 It is connected, receives the digital output modul signal of the processor output；The leading-out terminal is connected with the On-off signal equipment, The driving control signal for generating the solid-state relay 131 is input to the On-off signal equipment to control State On-off signal equipment.

As shown in fig. 7, only representing connection and the realization principle of first via switching value output circuit in Fig. 7.By described The 16 road drive signal MOS_DOUT0_0 of processor (i.e. fpga core main control unit) output of FPGA integrated circuit boards 100~ 2 feet of MOS_DOUT1_7 connection solid-state relays 131VN751PT, when the FPGA integrated circuit boards 100 processor (i.e. Fpga core main control unit) control MOS_DOUT0_0 be high level when, 3 feet and 5 feet of solid-state relay 131VN751PT are led Lead to and exports the 24VOUT driving external loadings for being connected to 3 feet.

In this present embodiment, the multichannel optocoupler secondary side output loop circuit 140 is used for and multiple signal circuit equipment It is connected, to each signal circuit equipment output loop signal to control the state of each signal circuit equipment.Such as such as Fig. 3 Shown, the multichannel optocoupler secondary side output loop circuit 140 provides No. 16 photoelectrical coupler secondary side output loops, for controlling The state in industry spot coherent signal processed circuit.

In this present embodiment, as shown in figure 8, including per the secondary side output loop circuit described all the way：Buffer 141, with The processor of the FPGA integrated circuit boards 100 is connected, and receives the loop control signal of the processor output；Photoelectrical coupler 142, there is the primary side connecting pin being connected with the buffer 141 and tool there are two leading-out terminal and set with the signal circuit The secondary side connecting pin of standby forming circuit.

As shown in figure 8, exporting 16 by the processor (i.e. fpga core main control unit) of the FPGA integrated circuit boards 100 Road drive signal DOUT0_0~DOUT1_7 and the Buffer output DO_0 for passing through photoelectrical coupler 142 (U2) secondary side output loop ~DO_15 signals only show first via secondary side output loop circuit in Fig. 8.When FPGA controls DOUT0_0 is high level When, it is high level that buffered device 141 (model SN74LVC244PW is shown in Fig. 8), which exports DO_0 also, and DO_0 passes through the 1K that connects Resistance makes photoelectrical coupler 142 (U2) primary side be connected, so that 4 feet and 3 feet of photoelectrical coupler 142 (U2) secondary side Conducting exports the conducting circuit of ext1_IN+, ext1_IN-, on the contrary then disconnect output.

In this present embodiment, the driving circuit 150 with multiple driven equipments for being connected, for driving each quilt Driving equipment is run.

In this present embodiment, as shown in Figures 2 and 3, the driving circuit 150 includes：Single phase ac electric drive circuit 151 With three-phase alternating current electric drive circuit 152.The three-phase alternating current electric drive circuit 152 for example provides 5 road triode ac switch three Phase alternating current exports, for directly driving three-phase induction motor equipment and powering for three-phase alternating current equipment；The single-phase alternating current Driving circuit 151 for example provides 4 road triode ac switch single phase ac electricity outputs, for directly driving single-phase alternating current power supply Equipment and single phase induction motor equipment.

In this present embodiment, as shown in figure 9, the single phase ac electric drive circuit 151 includes：Switching circuit 1511, it is single Phase electric drive circuit 1512, overload detection circuit 1513 and logic control circuit 1514.

As shown in Figure 10, the switching circuit 1511 (the field-effect transistor Q3 in Figure 10) and the FPGA integrated circuit boards 100 processor is connected, and the enable signal exported according to the processor of the FPGA integrated circuit boards 100 is connected and is closed It closes；The overload detection circuit 1513 is connected with the driven equipment and the logic control circuit 1514 respectively, detects institute State whether driven equipment occurs overload and the detection signal for whether overloading the driven equipment detected exports To the logic control circuit 1514；The logic control circuit 1514 (logic control chip) is electric with the overload detection respectively Road 1513 is connected with the single-phase electric drive circuit 1512, is generated according to the enabled control signal in outside and drives the driven equipment Operating enabled drive signal simultaneously the enabled drive signal is exported to the single-phase electric drive circuit 1512, while according to from The overload detection signals that the overload detection circuit 1513 receives stop exporting to the single-phase electric drive circuit 1512 described Enabled drive signal；Single-phase electric drive circuit 1512 is connected with the switching circuit 1511 and the driven equipment respectively, It receives the enabled drive signal from the logic control circuit 1514 and is generated when the switching circuit 1511 is connected and drive The singlephase drive signal of the dynamic driven equipment operation, stops driving the quilt when not receiving the enabled drive signal Driving equipment is run.

In this present embodiment, the overload detection circuit 1513 includes：Current sensor, with the driven equipment phase Even, the electric current in the driven equipment is detected；Comparator, respectively with the current sensor and the logic control circuit 1514 are connected, and the electric current that the current sensor detects are compared with default overload protection electric current, if the current sense The electric current of device detection is more than or equal to default overload protection electric current, then output overloading detects signal to the logic control circuit 1514, if the electric current of current sensor detection is less than default overload protection electric current, non-overload detection signals are exported to institute State logic control circuit 1514.

Wherein, the single-phase electric drive circuit 1512 include silicon-controlled photoelectrical coupler and with the silicon-controlled photoelectric coupling The triode ac switch of device connection.

As shown in Figure 10, the operation principle of the single phase ac electric drive circuit 151 is as follows：

En_1P_0 is connected with the pin in the BANK5 of FPGA, is used to form the enabled of single phase ac electric drive circuit 151 Signal, when En_1P_0 is high level, then field-effect transistor Q3 conductings are so that form the silicon-controlled light of series loop with Q3 The primary side of electric coupler U24 is connected, and then drives triode ac switch T3 conductings, output single-phase alternating current L1, N.Electric current Sensor U25 will be converted to analog voltage output by the ac current signal of itself, and sensing ratio is 100mv/A, works as nothing When current signal exports, current sensor U25 (such as model ACS714LLCTR-20A-T) exports the DC voltage of VCC/2, Supply voltage VCC is 5V, so the analog voltage signal of output is DC voltage 5/2 by the VIOUT pins of current sensor U25 =2.5V and the ac voltage signal for being superimposed with sensing ratio 100mv/A.Analog voltage signal after sensing is connected to comparator Compared with 2 feet of U23 (LM2903D) and the threshold voltage set using electric resistance partial pressure with 1 foot.As shown in Figure 10, comparator The threshold values that 1 foot of U23 (LM2903D) is set is [22K/ (22K+10K)] ≈ 3.5V, 3.5V-2.5V=1V, 1V/100mv/A= 10A, i.e., when the AC current values through over-current sensor U25 are more than 10A, comparator U23 is redirected, and by overload signal FPGA is inputted, the logic control circuit 1514 of FPGA detects overload signal according to some cycles always, if detecting overload Then 1514 count internal register of logic control circuit carries out accumulation operations to the overload signal that detection circuit 1513 is sent out, and every A counter register can be removed automatically every period certain time, then sentenced when counter register, which counts, to add up and be more than certain numerical value It is set to overload, and this state to master system and while is cancelled into enabled control signal by EtherCAT bus feedbacks En_1P_0, cut-out exchange electricity output.Once logic control circuit 1514 judges overload, then this state can not be eliminated, unless Host computer carries out reset processing by EtherCAT buses to this state.

In this present embodiment, as shown in figure 11, the three-phase alternating current electric drive circuit 152 includes：Switching circuit 1521, three Phase electric drive circuit 1522, overload detection circuit 1523 and logic control circuit 1524.

As shown in figure 12, the place of the switching circuit 1521 (field-effect transistor Q4) and the FPGA integrated circuit boards 100 It manages device to be connected, the enable signal exported according to the processor of the FPGA integrated circuit boards 100 is turned on and off；The mistake It carries detection circuit 1523 to be respectively connected with the driven equipment and the logic control circuit 1524, detection is described to be set by driving It is standby whether to occur to overload and export the detection the signal whether driven equipment detected overloads to the logic Control circuit 1524；The logic control circuit 1524 is electric with the overload detection circuit 1523 and the three-phase electric drive respectively Road 1522 is connected, and the enabled drive signal for driving the driven equipment operating is generated according to external enabled control signal and by institute It states enabled drive signal to export to the three-phase electric drive circuit 1522, while being received according to from the overload detection circuit 1523 To overload detection signals stop exporting the enabled drive signal to the three-phase electric drive circuit 1522；The three-phase electricity is driven Dynamic circuit 1522 is connected with the switching circuit 1521 and the driven equipment respectively, from the logic control circuit 1524 It receives the enabled drive signal and is generated when the switching circuit 1521 is connected and drive the driven equipment operation Three-phase driving signal stops driving the driven equipment operation when not receiving the enabled drive signal.

Wherein, as shown in figure 12, the overload detection circuit 1523 includes：First current sensor, the second current sense Device and third current sensor connect wires with the three-phase of driven equipment described in three-phase be connected respectively, and detection is described to be driven Electric current in equipment；First comparator, the second comparator and third comparator, respectively with first current sensor, institute It states the second current sensor and the third current sensor corresponds to and is connected, and be connected with the logic control circuit 1524, The electric current that each current sensor detects is compared with default overload protection electric current by corresponding to respectively, if the current sensor The electric current of detection is more than or equal to default overload protection electric current, then output overloading detection signal to the logic control circuit 1524, If the electric current of the current sensor detection is less than default overload protection electric current, non-overload detection signals are exported to the logic Control circuit 1524.

In this present embodiment, the three-phase electric drive circuit include three to be connected respectively with the switching circuit 1521 can Control silicon driving circuit, each described controllable silicon drive circuit include silicon-controlled photoelectrical coupler and with the silicon-controlled photoelectricity coupling The triode ac switch of clutch connection.

As shown in figure 12, the operation principle of the three-phase alternating current electric drive circuit 152 is as follows：

En_3P_0 is connected with the pin in the BANK5 of FPGA, is used to form the enabled of three-phase alternating current electric drive circuit 152 Signal, when En_3P_0 be high level when, then field-effect transistor Q4 conducting so that with Q4 formed series loop U26, U29, The primary side of tri- silicon-controlled photoelectrical couplers of U31 is connected, and then triode ac switch T4, T5, T6 is driven to be connected and pass through Current sensor ACS714LLCTR-20A-T output three-phase alternating currents U, V, W.Current sensor will pass through the alternating current of itself Stream signal is converted to analog voltage output, and sensing ratio is 100mv/A, when no signal current exports, current sensor (such as Model ACS714LLCTR-20A-T) U27, U30, U32, the DC voltage of VCC/2 is exported, supply voltage VCC is 5V, so The analog voltage signal of output is DC voltage 5/2=2.5V and is superimposed by the VIOUT pins of current sensor U27, U30, U32 The ac voltage signal of upper sensing ratio 100mv/A.Analog voltage signal after sensing is connected to comparator (such as model LM2903D compared with 2 feet of) U23, U24, U25 and the threshold voltage set using electric resistance partial pressure with 1 foot.As shown in Figure 12, The threshold values that 1 foot of comparator U23, U24, U25 are set is [22K/ (22K+10K)] ≈ 3.5V, 3.5V-2.5V=1V, 1V/ 100mv/A=10A, i.e., when the AC current values through over-current sensor are more than 10A, comparator redirects, and will overload Signal inputs FPGA, and logic control circuit 1524 detects overload signal according to some cycles always, if detecting overload inspection The overload signal that slowdown monitoring circuit 1523 is sent out then 1524 count internal register of logic control circuit carry out accumulation operations, and every Period certain time can remove a counter register automatically, then judge when counter register, which counts, to add up and be more than certain numerical value Occur for overload, and this state to master system and while being cancelled into enabled control signal by EtherCAT bus feedbacks En_3P_0, cut-out exchange electricity output.Once logic control circuit 1524 judges overload, then this state can not be eliminated, unless Host computer carries out reset processing by EtherCAT buses to this state.

In this present embodiment, as shown in Fig. 2 and Figure 13, the electrical integrated form controller further includes：Ic for energy metering 170, it is connected with the three phase mains powered for the FPGA integrated circuit boards 100, for 100 He of FPGA integrated circuit boards The power consumption of each circuit is measured.

In this present embodiment, the ic for energy metering 170 is three-phase four-wire system, electrical energy measurement electricity described in three-phase four-wire system Voltage and electric current are converted to binary message that slave station system can identify and processing through electric energy algorithm and then passed through by road 170 Corresponding current value, voltage value, active power value, reactive power value information state are transferred to upper owner by industrial field bus Station is processed and displayed.

The ic for energy metering 170 includes：Current Mutual Inductance circuit, voltage modulate circuit and electric energy computation chip.

The power input phase of the Current Mutual Inductance circuit and the three phase mains powered for the FPGA integrated circuit boards 100 Even, the current value for induction power supply input terminal per phase.

Specifically, the Current Mutual Inductance circuit includes the first current transformer A1, the second current transformer A2 and third Current transformer A3, respectively with for the FPGA integrated circuit boards 100 and each circuit power supply three phase mains three-phase connecting pin It is connected.First current transformer A1, the second current transformer A2 and third current transformer A3 are the electric current of Hall effect Mutual inductor, former pair side turn ratio is 1000:1, primary side maximum current capacity is 50A, i.e., secondary side maximum induced current is 50mA.

The power input phase of the voltage modulate circuit and the three phase mains powered for the FPGA integrated circuit boards 100 Even, every phase voltage value of the FPGA integrated circuit boards is input to for acquiring the power input.

Specifically, the voltage modulate circuit includes first resistor pressure divider circuit, second resistance pressure divider circuit and third Electric resistance partial pressure circuit, respectively with for the FPGA integrated circuit boards 100 and each circuit power supply three phase mains three-phase connecting pin It is connected.

The electric energy computation chip and the integrated electricity of the Current Mutual Inductance circuit, the voltage modulate circuit and the FPGA The processor of road plate 100 is connected, and is obtained according to the current value of the Current Mutual Inductance circuit inductance and the voltage modulate circuit Voltage value measures corresponding power consumption data, and the power consumption data of metering is sent to the FPGA integrated circuits The processor of plate 100；The external control devices are by the bus communication circuitry 110 from the FPGA integrated circuit boards 100 Processor obtain the power consumption data.

In this present embodiment, the electric energy computation chip has voltage acquisition channel and current acquisition channel.In this implementation In example, the electric energy computation chip is for example, by using ADE7880 electric energy computation chips.

ADE7880 electric energy computation chips are a high-precision of ADI companies, three phase metering IC, using serial port, and it is built-in Multiple second order sigma-delta type analog-to-digital converter, digital integrator, reference voltage source circuit and all required signal processing circuits, Realize total fundamental wave and harmonic wave it is active/apparent power measurement and virtual value calculate and fundamental active/wattless power measurement. ADE7880 chip interiors have special digital signal processor (DSP) to be responsible for realizing that signal processing, DSP programs are stored in inside In ROM memory.ADE7880 by current channel IAP IAN, IBP IBN, ICP ICN and voltage channel VAP, VBP, VCP, VCN acquires analog current and voltage signal, then carries out DA respectively and is converted to the digital quantity signal that ADE7880 can be identified, interior Portion DSP carries out algorithm process to these digital signals and is connected to FPGA by SPI universal serial bus.Host computer can pass through EtherCAT buses are read to FPGA in real time by the collected energy data information of ADE7880 electric energy computation chips.Electric current is adopted Collection channel will pass through the first current transformer A1, the second current transformer A2 and third electric current using the load resistor value of 5 Ω The real-time current signal that mutual inductor A3 pairs side senses becomes voltage signal and is transferred to ADE7880 chips, and voltage acquisition channel will Per phase voltage required three-phase alternating current is obtained in such a way that series connection 2.32M, 2.32M, 3.24M, 10K resistance value is divided Press signal.

In this present embodiment, as shown in Fig. 2 and Figure 14, the electrical integrated form controller further includes：Three-phase alternating current lacks Phase detecting circuit 180 is connected with the three-phase alternating current input port of the FPGA integrated circuit boards 100, is input to for detecting Three-phase alternating current in the FPGA integrated circuit boards 100 whether phase shortage.The three-phase alternating current lack detection circuit 180 wraps It includes：Detection circuit, the input for detecting three-phase alternating current；Phase shortage decision circuitry, for being sentenced according to the input of three-phase alternating current Break the three-phase alternating current whether phase shortage.

In this present embodiment, as shown in figure 14, the detection circuit includes：First photoelectrical coupler U21A, the second photoelectricity Coupler U21B and third photoelectrical coupler U21C, is connected and with the three-phase connecting pin of three-phase alternating current in input AC respectively It is connected when electric；The phase shortage decision circuitry includes：First comparator U20A, the second comparator U20B, third comparator U20C, Four comparator U20D, field-effect transistor Q1, capacitance C62, the 4th photoelectrical coupler U21D；First comparator U20A, the second ratio Input terminal compared with device U20B, third comparator U20C corresponds to and the first photoelectrical coupler U21A, the second photoelectrical coupler respectively U21B and third photoelectrical coupler U21C is connected, and output end is connected with the grid of the field-effect transistor Q1；The capacitance The both ends of C62 are connected with the source electrode and drain electrode of the field-effect transistor Q1 respectively；The drain electrode of the field-effect transistor Q1 connects Connect the electrode input end of the 4th comparator U20D；The output end of the 4th comparator U20D and the 4th photoelectric coupling Device U21D is connected.

Wherein, the processor phase of the output end and the FPGA integrated circuit boards 100 of the 4th photoelectrical coupler U21D Even, by whether the detection signal of phase shortage is exported to the processor of the FPGA integrated circuit boards 100；The external control devices are logical Crossing the bus communication circuitry 110, whether the detection of phase shortage is believed from described in the acquisition of the processor of the FPGA integrated circuit boards 100 Number.

As shown in figure 14, the testing principle of the three-phase alternating current lack detection circuit 180 is as follows：

When three-phase alternating-current supply input is normal, in any moment of AC power work period, U21A, U21B, U21C These three photoelectrical couplers can control signal Uc and be in low level signal, field effect always there are one in the conduction state always Transistor Q1 is answered to be not turned on, for example, the 9 foot voltages of third comparator U20C are higher than 8 foot voltages, third comparator U20C output ends 14 feet will export high level 12V, so photoelectrical coupler U21D is not turned on, to make phase shortage alarm signal Default_Phase For low level, not phase shortage is indicated.When three-phase voltage, which inputs, lacks any phase, line voltage will only have a phase, when the phases line voltage In near zero-crossing point, photoelectrical coupler U21A, U21B, U21C are not turned on, and control signal is in high level signal at the moment And field-effect transistor Q1 conductings are triggered, the capacitance C62 being connected across between field-effect transistor Q1 source electrode and drain electrodes will be bypassed And repid discharge, level become 0V, since the period to next zero passage point moment is 10ms, i.e., in this period of 10ms Interior, photoelectrical coupler U21A, U21B, U21C these three photoelectrical couplers always can there are one in the conduction state so that signal Uc is low level within this time, and Q1 shutdowns, power supply 12V charges to capacitance C62 by resistance R85, by formula Vt=V0+ (Vu-V0) * [1-e (- t/RC)], V0=0V, Vu=12V, t=10ms, R=10K, C=10uF can be calculated and passed through Vt ≈ 0.1Vu=1.2V after the 10ms times, thus the 9 foot voltages of comparator U20C within any time other than zero crossing always 8 foot voltage values are less than, so it is 0V that 14 feet of U20C export always, the primary side of such photoelectrical coupler U21D is connected, It through resistance R84 and is connected the 7th foot of photoelectrical coupler U21D by 12V power supplys and is connected with the 8th foot, so photoelectrical coupler U21D Secondary side conducting, 5V power supplys connect with R90 through resistance R89 divides export 3.3V level Default_Phase phase shortage report Alert signal to FPGA, and by EtherCAT buses by this feedback of status to host computer.

In this present embodiment, the power supply circuit 160 include power for the FPGA integrated circuit boards 100 it is independently-powered Circuit 161 and the multiple power supply sub-circuits powered for above-mentioned each circuit.

In this present embodiment, as shown in figure 15, the independently-powered circuit 161 includes：With the FPGA integrated circuit boards The low pressure difference linearity 100 processor connected adjusting and voltage-reduction switch power supply chip and be connected with the adjusting and voltage-reduction switch power supply chip Voltage-stablizer.

As shown in figure 15, in this present embodiment, the independently-powered circuit 161 has used LINEAR companies The switching power source chip of LT3507AEUHF, it is the switch power integrated circuit chip of a triple channel voltage-dropping type, this chip is also LDO low pressure difference linear voltage regulators all the way can be provided.Power input ranging from 6~36V exports the adjustable economize on electricity in 4 channels in total Pressure exports adjustable voltage calculation formula VOUT=[(RFBB800mv)/RFBT]+800mv, can convert out respectively This four groups of supply voltages of VCC3.3,3.3VPHY, VCC1.2, VCC2.5, and be filtered respectively by output capacitance, ensure defeated Go out minimum ripple voltage, output ripple voltage range only 10mv or so.Current driving ability VCC3.3 reaches 2.7A, 3.3VPHY reaches 1.8A, and VCC1.2 reaches 1.8A, and VCC2.5 (LDO) reaches 300mA, fully meet FPGA power demands and The power demands of part I/O peripheral.LT3507AEUHF switch power integrated circuit chips are that QFN encapsulates (5mm x 7mm), volume Very small, PCB surface product shared by entire independently-powered circuit 161 only has 2cm²Left and right.

In this present embodiment, the place of the pin of the adjusting and voltage-reduction switch power supply chip and the FPGA integrated circuit boards 100 It is connected with decoupling capacitor between the power pins of reason device.Decoupling capacitor can filter out the processor of FPGA integrated circuit boards 100 (i.e. Fpga core main control unit) generated high-frequency noise in the course of work, enhance the interference free performance of FPGA, will be gone in wiring Coupling capacitance makes the both ends lead of decoupling capacitor short as possible close proximity to power pins and ground pin.

In this present embodiment, as shown in figure 3, multiple power supply sub-circuits include 3.3V power supplies sub-circuit, 5V power supply sub-circuits 163,12V power supply sub-circuits 162 etc., are configured in the circuit of needs as needed.

As shown in figure 16, it is shown as the circuit structure of 12V power supplies sub-circuit 162 in the electrical integrated form controller of the present invention Figure.

In this present embodiment, the 12V power supplies sub-circuit 162 uses the switching power source chip of a voltage-dropping type of TI companies LM22676MR-ADJ, the acceptable input voltage range of the chip are 4.5V~42V, export adjustable voltage calculation formula VOUT=[(1.285vRFBT)/RFBB]+1.285v makes output electricity by the resistance value of resistance R78 and R77 in adjusting figure Pressure is adjusted to required 12V voltages, and is filtered respectively by output capacitance, ensures to export minimum ripple voltage, output Ripple voltage range only 10mv or so.The maximum current drive ability of LM22676MR-ADJ is 3A, is satisfied the use demand.

Shown in Figure 17, it is shown as the circuit structure diagram of 5V power supplies sub-circuit 163 in the electrical integrated form controller of the present invention. In this present embodiment, the 5V power supply sub-circuits 163 are using LDO chips NCP1117-5V.

In this present embodiment, the electrical integrated form controller further includes being integrated on the FPGA integrated circuit boards 100 's：Clock input circuit 190, program configuration circuit 1100 and extend out RAM chip 1120 at debugging interface circuit 1110.

In this present embodiment, as shown in figure 18, the clock input circuit 190 is the FPGA integrated circuit boards 100 Processor provides work clock.

As shown in figure 18, the processor (i.e. fpga core main control unit) of FPGA integrated circuit boards 100 by it is special when Clock input pin is connected with clock input circuit 190, and the source crystal oscillator that has of 25MHz is selected in clock input, and output terminal of clock needs The build-out resistor for concatenating one 33 Ω is connected to one of 16 special clock input terminals of FPGA, the 25MHz clocks through FPGA inside After PLL phaselocked loops improve clock quality and frequency multiplication, it is used as the work clock of entire clock input circuit 190, i.e. each clock Rising edge/failing edge all trigger the specific operation in FPGA.The FPGA of such Cyclone IV has CLK1~CLK15 totally 15 Root special clock input line, not used special clock input line can be used as input port, but cannot be configured as output to mouth.

In this present embodiment, as shown in figure 19, described program configuration circuit 1100 is by the FPGA integrated circuit boards 100 Configuration data is loaded into from nonvolatile external memory Flash or EEPROM in the FPGA integrated circuit boards 100.

As shown in figure 19, the pin ASDO of the processor (i.e. fpga core main control unit) of FPGA integrated circuit boards 100, NCSO, DATA0, DCLK and power supply VCC3.3, GND, be connected with EPCS16 programs configuration chip circuit e.The configuration of FPGA It is to be loaded into the configuration data of FPGA in FPGA from nonvolatile external memory Flash or EEPROM, the nCE of FPGA directly connects GND, nSTATUS and CONF_DONE are pulled to VCCIO with 10K resistance, and CONFIG is configuration control input pin, and FPGA is in When user mode, if the pin is driven externally as low level, FPGA immediately enters reset state, and all I/O pins are set to For high-impedance state, after which gets higher again, FPGA, which is proceeded by, to be reconfigured.Therefore, nCONFIG is also pulled to using 10K resistance VCCIO。

In this present embodiment, as shown in figure 20, the debugging interface circuit 1110 is the FPGA integrated circuit boards 100 Processor provides debugging interface.The debugging interface circuit 1110 is JTAG debugging interfaces circuit 1110.

As shown in figure 20, the processor (i.e. fpga core main control unit) of FPGA integrated circuit boards 100 passes through pin STDI, STDO, STCK, STMS and power supply VCC2.5, GND, be connected with debugging interface circuit 1110.The model selection of FPGA Input pin MSEL [2:0] external that GND or VCCA=2.5V are directly connected on without resistance to determine configuration mode.Because selecting EPCS Device uses the configuration level standard of 3.3V, therefore is selection AS (actively serial) configuration mode, and MSEL3 meets GND, and MSEL2 connects GND, MSEL1 meet 2.5V, and MSEL0 meets GND.The highest priority of JTAG configuration modes ignores MSEL when carrying out JTAG configurations [3:0] connection, i.e. JTAG configuration modes be not by MSEL [3:0] pin controls.The definition of JTAG pins is：When TCK is test Clock inputs, and TMS selects for test pattern, and TMS, which is used for that jtag interface is arranged, is in certain specific test pattern.TDI is test Data input, and data input jtag interface by TDI pins；TDO is test data output, and data are by TDO pins from JTAG Interface exports.

In this present embodiment, as shown in figure 21, described to extend out RAM chip 1120, it is carried for the FPGA integrated circuit boards 100 For external memory space.

As shown in figure 21 to extend out the schematic diagram of RAM chip 1120, to improve the working performance of FPGA, select ISSI public The capacity of department is 2MB, and speed is the RAM chip IS61WV6416EEBLL-10BI of 10ns, which can provide sufficiently fast Response time and larger memory space, meet the need of work of FPGA.The address wire SRAM_A0-SRAM_A15 of RAM chip, SRAM_CEn, SRAM_OEn, SRAM_WEn, SRAM_BHEn, SRAM_BLEn points of data line SRAM_D0-SRAM_D15, control line It is not connected with the parts the BANK2 pin of FPGA.

Using the electrical integrated form controller of the present embodiment, there is following advantage：

Manufacture end, by the present invention electrical integrated form industrial control unit (ICU) highly integrated and high consistency it is excellent Point can save a large amount of manpower operations and debugging service time, production efficiency is greatly improved when carrying out large-scale production With reduction production and operation cost.

It is held after sale in market, dispersion electric components up to a hundred of tens relative to conventional electrical scheme and its what is constituted answer Sundries manages connection line, and electrical integrated form industrial control unit (ICU) of the invention can substantially reduce the difficulty of Maintenance and Repair and the time disappears Consumption is safeguarded to market and brings great convenience, can greatly promote the operational efficiency of market terminal bed, reduces because of machine Bed maintenance time extend and give direct economic loss caused by client.

The accessible sensor of conventional electrical scheme is extremely limited, and can only provide hydraulic failure and hatch door does not close information, nothing Method knows the machine dependent failure and system protection information, and the electrical integrated form industrial control unit (ICU) of the present invention is also integrated with electric energy matter Many informations parameter such as monitoring, real-time power consumption, environment temperature, the machine temperature, real-time the machine operating status and failure are measured, are It realizes that intelligence manufacture is created more may.

In conclusion the present invention relies on FPGA integrated circuit boards, by traditional scheme controller, discrete movement device, Connection three functional units of rigid line are integrated on FPGA integrated circuit boards, based on the high processing speed of FPGA integrated circuit boards and A large amount of internal I/O resource and by the way of network communication, can carry a large amount of sensor resource, can be to high-rise MES The state and fault message of System Reports various field：State including the machine itself and failure, and the present invention is also pre- simultaneously Communication/the control interface for having stayed industrial robot, can arrange in pairs or groups third-party industrial machine person cooperative work, realize higher degree Factory automation, in addition, the present invention can be with main control room or host computer forming control system and the sensing for completing industry spot Device is matched with operator signals, has high electrical integrated, high reliability, high maintenance, inexpensive advantage.Institute With the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization.

The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause This, technical field includes that institute is complete without departing from the spirit and technical ideas disclosed in the present invention for usual skill such as At all equivalent modifications or change, should by the present invention claim be covered.

Claims

1. a kind of electrical integrated form controller, which is characterized in that including：

FPGA integrated circuit boards are integrated on the FPGA integrated circuit boards：

Bus communication circuitry, for being communicated with external control devices；

Driving circuit, for being connected with multiple driven equipments, for driving each driven equipment operation；

Power supply circuit includes the independently-powered circuit powered for the FPGA integrated circuit boards and is the more of above-mentioned each circuit power supply A power supply sub-circuit.

2. electrical integrated form controller according to claim 1, which is characterized in that the bus communication circuitry includes：If In the processor of the FPGA integrated circuit boards for communicated with the external control devices the soft cores of communication IP, be set to On the FPGA integrated circuit boards and with the soft nuclear phases of communication IP communication input interface even, communication output interface and connect Telecommunication circuit between the communication input interface, the communication output interface and the external control devices.

3. electrical integrated form controller according to claim 2, which is characterized in that the telecommunication circuit includes：

The communication input interface on communication physical layer chip, with the FPGA integrated circuit boards and the communication output interface It is connected；

Network transformer is connected with the communication physical layer chip, for the signal of communication of the communication physical layer chip into Row isolation and conversion；

Communication interface is connected with the network transformer and the external control devices, for the external control devices into Row communication.

4. electrical integrated form controller according to claim 1, which is characterized in that the electrical integrated form controller also wraps It includes and is integrated on the FPGA integrated circuit boards：

Multi-way switching values input circuit reads each output switch parameter equipment for being connected with multiple switch amount output equipment On-off signal state；

Multi-way switching values output circuit, it is defeated to each On-off signal equipment for being connected with multiple switch amount input equipment Enter switching value to control each On-off signal equipment；

Multichannel optocoupler secondary side output loop circuit is set for being connected with multiple signal circuit equipment to each signal circuit Standby output loop signal is to control the state of each signal circuit equipment.

5. electrical integrated form controller according to claim 4, which is characterized in that per the switching value input circuit described all the way Including：

Photoelectrical coupler, for being isolated and improving the On-off signal signal；

Wherein, the photoelectrical coupler has receiving terminal and transmission terminal；The receiving terminal corresponds to defeated with the switching value Go out the On-off signal signal that equipment is connected and reads each output switch parameter equipment；The transmission terminal and the FPGA collection It is connected at the processor of circuit board, extremely by the On-off signal signal transmission after the photoelectric coupler isolation and conditioning The processor of the FPGA integrated circuit boards.

6. electrical integrated form controller according to claim 4, which is characterized in that per the switching value output circuit described all the way Including：

Solid-state relay, for generating the drive control for driving the On-off signal equipment according to the On-off signal signal Signal；

Wherein, the solid-state relay has receiving terminal and leading-out terminal；The receiving terminal and the FPGA integrated circuits The processor of plate is connected, and receives the digital output modul signal of the processor output；The leading-out terminal and the switching value are defeated Enter equipment to be connected, the driving control signal for generating the solid-state relay is input to the On-off signal equipment To control the On-off signal equipment.

7. electrical integrated form controller according to claim 4, which is characterized in that per the secondary side output loop described all the way Circuit includes：

Buffer is connected with the processor of the FPGA integrated circuit boards, receives the loop control signal of the processor output；

Photoelectrical coupler, there is the primary side connecting pin that is connected with the buffer and there are two having leading-out terminal and with the letter The secondary side connecting pin of number circuit units forming circuit.

8. electrical integrated form controller according to claim 1, which is characterized in that the driving circuit includes：Blow-up Galvanic electricity driving circuit and three-phase alternating current electric drive circuit.

9. electrical integrated form controller according to claim 8, which is characterized in that the single phase ac electric drive circuit packet It includes：Switching circuit, single-phase electric drive circuit, overload detection circuit and logic control circuit；

The switching circuit is connected with the processor of the FPGA integrated circuit boards, according to the processing of the FPGA integrated circuit boards The enable signal of device output is turned on and off；

The overload detection circuit is connected with the driven equipment and the logic control circuit respectively, and detection is described to be driven Whether equipment, which occurs to overload and export the detection the signal whether driven equipment detected overloads to described, is patrolled Collect control circuit；

The logic control circuit is connected with the overload detection circuit and the single-phase electric drive circuit respectively, is made according to outside Can control signal generate the enabled drive signal for driving driven equipment operating and by the enabled drive signal export to The single-phase electric drive circuit, while being stopped to the list according to the overload detection signals received from the overload detection circuit Phase electric drive circuit exports the enabled drive signal；

Single-phase electric drive circuit is connected with the switching circuit and the driven equipment respectively, from the logic control circuit It receives the enabled drive signal and is generated when the switching circuit is connected and drive the single-phase of the driven equipment operation Drive signal stops driving the driven equipment operation when not receiving the enabled drive signal.

10. electrical integrated form controller according to claim 9, which is characterized in that the overload detection circuit includes：

Current sensor is connected with the driven equipment, detects the electric current in the driven equipment；

Comparator is connected with the current sensor and the logic control circuit respectively, and the current sensor is detected Electric current is compared with default overload protection electric current, if the electric current of current sensor detection is more than or equal to default overload protection Electric current, then output overloading detection signal to the logic control circuit, presets if the electric current of current sensor detection is less than Overload protection electric current then exports non-overload detection signals to the logic control circuit.

11. electrical integrated form controller according to claim 9, which is characterized in that the single-phase electric drive circuit includes Silicon-controlled photoelectrical coupler and the triode ac switch being connect with the silicon-controlled photoelectrical coupler.

12. electrical integrated form controller according to claim 8, which is characterized in that the three-phase alternating current electric drive circuit Including：Switching circuit, three-phase electric drive circuit, overload detection circuit and logic control circuit；

The logic control circuit is connected with the overload detection circuit and the three-phase electric drive circuit respectively, is made according to outside Can control signal generate the enabled drive signal for driving driven equipment operating and by the enabled drive signal export to The three-phase electric drive circuit, while being stopped to described three according to the overload detection signals received from the overload detection circuit Phase electric drive circuit exports the enabled drive signal；

The three-phase electric drive circuit is connected with the switching circuit and the driven equipment respectively, from the logic control Circuit, which receives the enabled drive signal and generated when the switching circuit is connected, drives the driven equipment operation Three-phase driving signal stops driving the driven equipment operation when not receiving the enabled drive signal.

13. electrical integrated form controller according to claim 12, which is characterized in that the overload detection circuit includes：

First current sensor, the second current sensor and third current sensor, respectively with driven equipment described in three-phase Three-phase connect wires connected, detect the electric current in the driven equipment；

First comparator, the second comparator and third comparator, respectively with first current sensor, second electric current Sensor and the third current sensor, which correspond to, to be connected, and is connected with the logic control circuit, will be each by correspondence respectively The electric current of current sensor detection is compared with default overload protection electric current, if the electric current of current sensor detection is more than Equal to default overload protection electric current, then output overloading detects signal to the logic control circuit, if the current sensor is examined The electric current of survey is less than default overload protection electric current, then exports non-overload detection signals to the logic control circuit.

14. electrical integrated form controller according to claim 12, which is characterized in that the three-phase electric drive circuit includes Three controllable silicon drive circuits being connected respectively with the switching circuit, each described controllable silicon drive circuit includes silicon-controlled Photoelectrical coupler and the triode ac switch being connect with the silicon-controlled photoelectrical coupler.

15. according to electrical integrated form controller according to claim 1, which is characterized in that the electrical integrated form control Device further includes：

Ic for energy metering is connected with the three phase mains powered for the FPGA integrated circuit boards, for integrated to the FPGA The power consumption of circuit board and each circuit is measured；The ic for energy metering includes：

Current Mutual Inductance circuit is connected with the power input for the three phase mains powered for the FPGA integrated circuit boards, for feeling Answer current value of the power input per phase；

Voltage modulate circuit is connected with the power input for the three phase mains powered for the FPGA integrated circuit boards, for adopting Collect every phase voltage value that the power input is input to the FPGA integrated circuit boards；

Electric energy computation chip, respectively with the Current Mutual Inductance circuit, the voltage modulate circuit and the FPGA integrated circuits The processor of plate is connected, the voltage value obtained according to the current value of the Current Mutual Inductance circuit inductance and the voltage modulate circuit Corresponding power consumption data is measured, and the power consumption data of metering is sent to the place of the FPGA integrated circuit boards Manage device；The external control devices are by the bus communication circuitry from described in the acquisition of the processor of the FPGA integrated circuit boards Power consumption data.

16. according to electrical integrated form controller according to claim 15, which is characterized in that the ic for energy metering is Three-phase four-wire system, the Current Mutual Inductance circuit include the first current transformer, the second current transformer and third Current Mutual Inductance Device is connected with the three-phase connecting pin for the FPGA integrated circuit boards and the three phase mains of each circuit power supply respectively；The voltage Modulate circuit includes first resistor pressure divider circuit, second resistance pressure divider circuit and 3rd resistor pressure divider circuit, respectively with for institute The three-phase connecting pin for stating the three phase mains that FPGA integrated circuit boards and each circuit are powered is connected.

17. according to electrical integrated form controller according to claim 15, which is characterized in that the electric energy computation chip tool There are voltage acquisition channel and current acquisition channel.

18. electrical integrated form controller according to claim 1, which is characterized in that the electrical integrated form controller is also Including：

Three-phase alternating current lack detection circuit is connected with the three-phase alternating current input port of the FPGA integrated circuit boards, is used for Detection be input to three-phase alternating current in the FPGA integrated circuit boards whether phase shortage；The three-phase alternating current lack detection circuit Including：

Detection circuit, the input for detecting three-phase alternating current；

Phase shortage decision circuitry, for according to the input of three-phase alternating current judge the three-phase alternating current whether phase shortage.

19. electrical integrated form controller according to claim 18, which is characterized in that

The detection circuit includes：First photoelectrical coupler, the second photoelectrical coupler and third photoelectrical coupler, respectively with three The three-phase connecting pin of phase alternating current is connected and is connected in input AC electricity；

The phase shortage decision circuitry includes：First comparator, the second comparator, third comparator, the 4th comparator, field-effect are brilliant Body pipe, capacitance, the 4th photoelectrical coupler；

The first comparator, second comparator, the input terminal of the third comparator are corresponding with first light respectively Electric coupler, second photoelectrical coupler and the third photoelectrical coupler are connected, output end and the field effect transistor The grid of pipe is connected；The both ends of the capacitance are connected with the source electrode and drain electrode of the field-effect transistor respectively；The field-effect The drain electrode of transistor connects the electrode input end of the 4th comparator；The output end of 4th comparator and the 4th light Electric coupler is connected.

20. electrical integrated form controller according to claim 19, which is characterized in that the 4th photoelectrical coupler it is defeated Outlet is connected with the processor of the FPGA integrated circuit boards, by whether the detection signal of phase shortage is exported to the integrated electricity of the FPGA The processor of road plate；The external control devices are by the bus communication circuitry from the processor of the FPGA integrated circuit boards Obtain described in whether the detection signal of phase shortage.

21. electrical integrated form controller according to claim 1, which is characterized in that the independently-powered circuit includes：With The connected adjusting and voltage-reduction switch power supply chip of the processors of the FPGA integrated circuit boards and with the adjusting and voltage-reduction switch power supply chip Connected low pressure difference linear voltage regulator.

22. electrical integrated form controller according to claim 21, which is characterized in that the adjusting and voltage-reduction switch power supply chip Pin and the FPGA integrated circuit boards processor power pins between be connected with decoupling capacitor.

23. electrical integrated form controller according to claim 1, which is characterized in that the electrical integrated form controller is also Including being integrated on the FPGA integrated circuit boards：

Clock input circuit, the processor for the FPGA integrated circuit boards provide work clock；

Program configuration circuit, by the configuration data of the FPGA integrated circuit boards from nonvolatile external memory Flash or EEPROM is loaded into the FPGA integrated circuit boards；

Debugging interface circuit, the processor for the FPGA integrated circuit boards provide debugging interface；

RAM chip is extended out, external memory space is provided for the FPGA integrated circuit boards.