CN108364929A - 半导体装置以及半导体装置的制造方法 - Google Patents
半导体装置以及半导体装置的制造方法 Download PDFInfo
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- CN108364929A CN108364929A CN201810039009.1A CN201810039009A CN108364929A CN 108364929 A CN108364929 A CN 108364929A CN 201810039009 A CN201810039009 A CN 201810039009A CN 108364929 A CN108364929 A CN 108364929A
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Abstract
本发明提供一种半导体装置以及半导体装置的制造方法。在多芯片WL-CSP中,不损害薄型性地实现半导体芯片间的连接的可靠性的提高。半导体装置包含:再布线,被设置在第一半导体芯片的主面上;绝缘膜,覆盖再布线的表面,具有使再布线分别局部地露出的第一开口部以及第二开口部;第一电极,被设置在绝缘膜上,在第一开口部与再布线连接,由与再布线相同的材料构成;以及第二电极,被设置在绝缘膜上,在第二开口部与再布线连接,由与第一电极不同的材料构成。
Description
技术领域
本发明涉及半导体装置以及半导体装置的制造方法。
背景技术
WL-CSP(晶圆级芯片尺寸封装)是利用晶圆工艺进行再布线、电极的形成、树脂密封以及切割的半导体装置的封装技术。另外,也已知有包含层叠的多个半导体芯片的多芯片WL-CSP。
对于多芯片WL-CSP而言,由于封装的平面尺寸与被收纳在封装内的任意一个半导体芯片的平面尺寸大致相同、以及封装的高度与被收纳在封装内的多个半导体芯片的层叠体的高度大致相同,所以能够实现半导体装置的高性能化,并且能够缩小封装尺寸。另外,由于通过倒装芯片键合来进行多个半导体芯片间的连接,所以无需引线键合,能够实现可抑制半导体芯片间的通信的延迟等性能的提高。
在专利文献1中记载有一种半导体装置的制造方法,该半导体装置的制造方法包含:在半导体晶圆上形成柱状电极的工序;在半导体晶圆上倒装芯片键合第二半导体芯片的工序;在半导体晶圆上形成以覆盖柱状电极和第二半导体芯片的方式进行密封的密封部的工序;以及对密封部和第二半导体芯片进行研磨以使柱状电极的上表面和第二半导体芯片的上表面露出的工序。
专利文献1:日本特开2008-218926号公报
在多芯片WL-CSP中,所层叠的第一半导体芯片与第二半导体芯片的连接的可靠性成为问题。第一半导体芯片与第二半导体芯片的接合例如通过使用包含SnAg的焊料端子,将第二半导体芯片倒装芯片键合到第一半导体芯片上来进行。焊料端子例如能够与通过再布线工艺形成在第一半导体芯片的表面的再布线或者电极接合。一般使用Cu来作为在第一半导体芯片的表面通过再布线工艺而形成的再布线或者电极的材料。然而,在该情况下,构成再布线或者电极的Cu会扩散到焊料端子内,对于再布线或者电极而言,在焊料接合部Cu消失,其结果是,有在第一半导体芯片与第二半导体芯片的连接上产生连接不良之虞。
作为抑制由朝向焊料端子内的Cu的扩散而引起的半导体芯片间的连接不良的方法,可举出加厚与焊料端子连接的再布线或者电极的厚度的方法。具体而言,可举出在第一半导体芯片与第二半导体芯片的接合部形成柱状电极的方法。然而,在该方法中,封装的厚度加厚,作为多芯片WL-CSP的特长的薄型性受到损害。
发明内容
本发明是鉴于上述的点而完成的,其目的在于在多芯片WL-CSP中,不损害薄型性地实现半导体芯片间的连接的可靠性的提高。
本发明的第一观点的半导体装置包含:再布线,被设置在第一半导体芯片的主面上;绝缘膜,覆盖上述再布线的表面,具有使上述再布线分别局部地露出的第一开口部以及第二开口部;第一电极,被设置在上述绝缘膜上,在上述第一开口部与上述再布线连接,由与上述再布线相同的材料构成;以及第二电极,被设置在上述绝缘膜上,在上述第二开口部与上述再布线连接,由与上述第一电极不同的材料构成。
本发明的第二观点的半导体装置包含:再布线,被设置在第一半导体芯片的主面上;绝缘膜,覆盖上述再布线的表面,具有使上述再布线分别局部地露出的第一开口部以及第二开口部;第一电极,被设置在上述绝缘膜上,在上述第一开口部经由导电膜与上述再布线连接;以及第二电极,被设置在上述绝缘膜上,在上述第二开口部与上述再布线连接,由与上述第一电极不同的材料构成。
本发明的第三观点的半导体装置包含:第一半导体芯片;第一绝缘膜,被设置于上述第一半导体芯片的主面;再布线,经由第一导电膜而设置于上述第一绝缘膜的表面;第二绝缘膜,覆盖上述再布线的表面,具有使上述再布线分别局部地露出的第一开口部以及第二开口部;第一电极,被设置在上述第二绝缘膜上,一端在上述第一开口部经由第二导电膜与上述再布线连接,另一端与外部连接端子连接;第二电极,被设置在上述第二绝缘膜上,在上述第二开口部经由上述第二导电膜与上述再布线连接,由与上述第一电极不同的材料构成;以及第二半导体芯片,在主面具有经由焊料与上述第二电极连接的第三电极。
本发明的半导体装置的制造方法包含:在第一半导体芯片的主面形成第一绝缘膜的工序;在上述第一绝缘膜的表面隔着第一导电膜形成再布线的工序;形成覆盖上述再布线的表面并具有使上述再布线分别局部地露出的第一开口部以及第二开口部的第二绝缘膜的工序;在上述第二绝缘膜上形成在上述第一开口部经由第二导电膜与上述再布线连接的第一电极的工序;在上述第二绝缘膜上形成在上述第二开口部经由上述第二导电膜与上述再布线连接的、由与上述第一电极不同的材料构成的第二电极的工序;以及将在主面具有第三电极的第二半导体芯片的上述第三电极与上述第二电极连接的工序。
根据本发明,在多芯片WL-CSP中,能够不损害薄型性地实现半导体芯片间的连接的可靠性的提高。
附图说明
图1是表示本发明的实施方式的半导体装置的结构的剖视图。
图2是放大地表示本发明的实施方式的半导体装置的局部结构的剖视图。
图3是表示本发明的实施方式的半导体装置的布线结构的一个例子的俯视图。
图4A是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4B是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4C是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4D是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4E是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4F是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4G是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4H是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4I是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4J是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4K是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4L是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4M是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4N是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4O是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4P是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4Q是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4R是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4S是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4T是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图4U是表示本发明的实施方式的半导体装置的制造工序的一个例子的剖视图。
图5A是表示本发明的实施方式的用于形成再布线的电镀处理所使用的电镀电极的结构的俯视图。
图5B是沿着图5A中的A-A′线的剖视图。
图6A是表示本发明的实施方式的用于形成芯片间接合电极以及柱状电极的电镀处理所使用的电镀电极的结构的俯视图。
图6B是沿着图6中的B-B′线的剖视图。
图7是表示比较例的半导体装置的结构的剖视图。
附图标记说明:1…半导体装置;21…下层绝缘膜;22…上层绝缘膜;31…第一UBM膜;32…第二UBM膜;34…芯片间接合电极;35…柱状电极;40…再布线;54…芯片间接合电极;60…焊料端子;70…密封树脂;80…外部连接端子;101…第一半导体芯片;102…第二半导体芯片;300、301…电镀电极。
具体实施方式
以下,参照附图对本发明的实施方式进行说明。此外,在各附图中,对实质相同或者等价的构成要素或者部分标注相同的参照符号。
图1是表示本发明的实施方式的半导体装置1的整体结构的剖视图。图2是放大地表示半导体装置1的局部结构的剖视图。
半导体装置1包含第一半导体芯片101、设置于第一半导体芯片101的主面上的再布线40以及经由再布线40与第一半导体芯片101连接的第二半导体芯片102。半导体装置1还包含以将第二半导体芯片102埋入内部的方式覆盖第一半导体芯片101的主面上的密封树脂70、贯通密封树脂70到达再布线40的柱状电极35以及设置于柱状电极35的顶部的外部连接端子80。此外,在图2中,对于密封树脂70以及外部连接端子80,省略图示。
半导体装置1的封装的方式具有多芯片WL-CSP的方式。即,半导体装置1的封装的平面尺寸与第一半导体芯片101的平面尺寸大致相同,并且封装的高度与第一半导体芯片和第二半导体芯片102的层叠体大致相同。
在构成第一半导体芯片101的半导体基板10的表面形成有晶体管、电阻元件以及电容器等电路元件(未图示)。半导体基板10的表面被由SiO2等绝缘体构成的层间绝缘膜11覆盖。在层间绝缘膜11的表面设置有与形成于半导体基板10的电路元件连接的芯片电极12和具有使芯片电极12的表面局部地露出的开口部的钝化膜(保护膜)13。
钝化膜13的表面被由聚酰亚胺或者PBO(聚苯并恶唑)等感光性有机绝缘部件构成的下层绝缘膜21覆盖。在下层绝缘膜21设置有使芯片电极12的表面局部地露出的开口部。
在下层绝缘膜21的表面隔着第一UBM(Under Bump Metallurgy:凸块下金属层)膜31设置有再布线40。第一UBM膜31例如由包含Ti膜和Cu膜的层叠膜构成。Ti膜作为用于提高下层绝缘膜21与再布线40的粘合性的粘合层发挥作用。Cu膜作为用于通过电解电镀法形成再布线40的电镀种子层发挥作用。再布线40例如由Cu等导电体构成,在下层绝缘膜21的开口部经由第一UBM膜31与芯片电极12连接。构成第一UBM膜31的Cu膜被纳入构成再布线40的Cu。因此,成为在下层绝缘膜21与再布线40之间夹有作为粘合层发挥作用的Ti膜的结构。
下层绝缘膜21以及再布线40的表面被由聚酰亚胺或者PBO等感光性有机绝缘部件构成的上层绝缘膜22覆盖。在上层绝缘膜22中,在柱状电极35的形成位置设置有使再布线40局部地露出的第一开口部22A,在芯片间接合电极34的形成位置设置有使再布线40局部地露出的第二开口部22B。
在上层绝缘膜22上设置有柱状电极35和芯片间接合电极34。柱状电极35形成于在俯视时内含上层绝缘膜22的第一开口部22A的区域。柱状电极35经由第二UBM膜32与再布线40的在第一开口部22A露出的部分连接。作为柱状电极35的材料,能够优选使用容易加工的Cu。柱状电极35例如具有圆柱形状。
芯片间接合电极34形成于在俯视时内含上层绝缘膜22的第二开口部22B的区域。芯片间接合电极34经由第二UBM膜32与再布线40的在第二开口部22B露出的部分连接。芯片间接合电极34例如由不产生朝向包含SnAg的焊料的扩散的金属构成。作为芯片间接合电极34的材料,例如能够优选使用Ni。即,芯片间接合电极34由与柱状电极35不同的材料构成。
第二UBM膜32被设置在再布线40与柱状电极35之间以及再布线40与芯片间接合电极34之间。第二UBM膜32与第一UBM膜31相同地,由包含作为粘合层发挥作用的Ti膜和作为电镀种子层发挥作用的Cu膜的层叠膜构成。构成第二UBM膜32的Cu膜被纳入构成柱状电极35的Cu。因此,成为在柱状电极35与再布线40之间夹有作为粘合层发挥作用的Ti膜的结构。另一方面,成为在芯片间接合电极34与再布线40之间夹有包含Ti膜和Cu膜的层叠膜的结构。
第二半导体芯片102以电路元件(未图示)的形成面与第一半导体芯片101对置的状态配置在第一半导体芯片101上。第二半导体芯片102具有与第一半导体芯片101相同或者类似的结构。即,在构成第二半导体芯片102的半导体基板50的表面设置有由聚酰亚胺或者PBO等感光性有机绝缘部件构成的下层绝缘膜51,在下层绝缘膜51上设置有再布线53。再布线53经由设置于半导体基板50的表面的芯片电极(未图示)与设置于半导体基板50的表面的晶体管等电路元件(未图示)连接。
下层绝缘膜51和再布线53的表面被由聚酰亚胺或者PBO等感光性有机绝缘部件构成的上层绝缘膜52覆盖。在上层绝缘膜52中,在芯片间接合电极54的形成位置设置有使再布线53局部地露出的开口部。
在上层绝缘膜52上设置有芯片间接合电极54。芯片间接合电极54形成于在俯视时内含上层绝缘膜52的开口部的区域。芯片间接合电极54经由UBM膜55与再布线53的露出部分连接。芯片间接合电极54例如由不产生朝向包含SnAg的焊料的扩散的金属构成。作为芯片间接合电极54的材料,例如能够优选使用Ni。UBM膜55由包含作为粘合层发挥作用的Ti膜和作为电镀种子层发挥作用的Cu膜的层叠膜构成。
第二半导体芯片102的芯片间接合电极54例如经由由SnAg等焊料构成的焊料端子60与第一半导体芯片101的芯片间接合电极34连接。形成于第二半导体芯片102的电路元件经由第一半导体芯片101侧的芯片间接合电极34和再布线40与形成于第一半导体芯片101的电路元件或者柱状电极35(外部连接端子80)电连接。
在第一半导体芯片101的与第二半导体芯片102的接合面的一侧,设置有密封树脂70,第二半导体芯片102和柱状电极35被埋入至密封树脂70内。柱状电极35的顶部从密封树脂70的表面露出。在柱状电极35的顶部设置有由SnAg等焊料构成的外部连接端子80。半导体装置1通过外部连接端子80与布线基板(未图示)连接,来安装于该布线基板。
此外,在图1所示的例子中,第二半导体芯片102的同与第一半导体芯片101的接合面相反侧的面(以下,称为背面)被密封树脂70覆盖,但第二半导体芯片102的背面也可以从密封树脂70露出。
图3是表示半导体装置1的布线结构的一个例子的俯视图。如图3所示,第一半导体芯片101的芯片电极12沿着具有矩形形状的第一半导体芯片101的各边配置。与芯片电极12连接的再布线40向第一半导体芯片101的平面方向的内侧引出,并与柱状电极35或者芯片间接合电极34连接。在本实施方式中,芯片间接合电极34被集中配置在第一半导体芯片101的中央部,柱状电极35被配置为包围芯片间接合电极34的外周。第二半导体芯片102在配置有芯片间接合电极34的第一半导体芯片101的中央部搭载在第一半导体芯片101上。
以下,参照图4A~图4U对本实施方式的半导体装置1的制造方法进行说明。图4A~图4U是表示半导体装置1的制造工序的剖视图。
首先,准备第一半导体芯片101的制造工艺完成了的半导体晶圆(图4A)。第一半导体芯片101的制造工艺包含:在半导体基板10上形成晶体管等电路元件(未图示)的工序;在半导体基板10的表面形成由SiO2等绝缘体构成的层间绝缘膜11的工序;在层间绝缘膜11的表面形成芯片电极12的工序;以及在层间绝缘膜11的表面以使芯片电极12局部地露出的方式形成钝化膜(保护膜)13的工序。
接下来,例如,使用旋涂法,在第一半导体芯片101的表面涂覆聚酰亚胺或者PBO等感光性有机绝缘部件,从而形成覆盖钝化膜13和芯片电极12的表面的下层绝缘膜21。接着,通过对下层绝缘膜21实施曝光和显影处理,在下层绝缘膜21形成使芯片电极12的表面局部地露出的开口部21A。之后,通过热处理使下层绝缘膜21固化(图4B)。
接下来,形成覆盖下层绝缘膜21的表面、在开口部21A露出的芯片电极12的表面的第一UBM膜31(图4C)。第一UBM膜31例如通过使用溅射法依次形成Ti膜和Cu膜而形成。Ti膜作为用于提高下层绝缘膜21与再布线40的粘合性的粘合层发挥作用。Cu膜作为用于利用电解电镀法形成再布线40的电镀种子层发挥作用。另外,在本工序中,在半导体晶圆的外周部形成与第一UBM膜31连接的电镀电极300(参照图5A、5B)。电镀电极300与第一UBM膜31相同地,例如通过依次形成Ti膜和Cu膜而形成。电镀电极在之后的工序中利用电解电镀法形成再布线40时使用。
接下来,使用公知的光刻技术,在第一UBM膜31的表面形成具有与再布线40的图案对应的开口部200A的抗蚀剂掩模200(图4D)。抗蚀剂掩模200通过在第一UBM膜31上涂覆感光性树脂,并对感光性树脂实施曝光和显影处理而形成。
接下来,使用电解电镀法,在第一UBM膜31的表面形成再布线40(图4E)。具体而言,将半导体基板10的表面浸入至电镀液,并向与第一UBM膜31连接的电镀电极300(参照图5A、5B)供给电流。由此,在第一UBM膜31(电镀种子层)的露出部分析出金属,在第一UBM膜31上形成再布线40。作为再布线40的材料,例如能够使用Cu。在该情况下,构成第一UBM膜31的电镀种子层被纳入再布线40的Cu。因此,成为在再布线40与下层绝缘膜21之间夹有作为粘合层发挥作用的Ti膜的结构。
在这里,图5A是表示用于形成再布线40的电镀处理所使用的电镀电极300的结构的俯视图。图5B是沿着图5A中的A-A′线的剖视图。如图5A所示,电镀电极300设置于形成有多个第一半导体芯片101的半导体晶圆400的外周部的多个位置。多个电镀电极300分别与第一UBM膜31连接。第一UBM膜31和电镀电极300由作为粘合层发挥作用的Ti膜31a和作为电镀种子层发挥作用的Cu膜31b的层叠膜构成。通过在将半导体基板10的表面浸入至电镀液的状态下,向电镀电极300供给电流,从而在第一UBM膜31上形成再布线40。
在形成再布线40之后,使用公知的灰化工艺或者有机溶剂等除去抗蚀剂掩模200。之后,以再布线40为掩模除去第一UBM膜31的被抗蚀剂掩模200覆盖的不要部分(图4F)。由此,用于形成再布线40的电镀处理所使用的电镀电极300也被除去。
接下来,例如,使用旋涂法,在通过经过上述各处理而形成的结构体的表面,涂覆聚酰亚胺或者PBO等感光性有机绝缘部件,从而形成覆盖下层绝缘膜21以及再布线40的表面的上层绝缘膜22。接着,通过对上层绝缘膜22实施曝光和显影处理,在上层绝缘膜22上形成使再布线40的表面局部地露出的第一开口部22A和第二开口部22B。第一开口部22A形成于在俯视时内含于形成柱状电极35的区域的区域。第二开口部22B形成于在俯视时内含于形成芯片间接合电极34的区域的区域。之后,通过热处理使上层绝缘膜22固化(图4G)。
接下来,形成覆盖上层绝缘膜22的表面、在第一开口部22A和第二开口部22B露出的再布线40的表面的第二UBM膜32(图4H)。第二UBM膜32例如使用溅射法,依次形成Ti膜和Cu膜而形成。Ti膜作为用于提高上层绝缘膜22与柱状电极35以及芯片间接合电极34的粘合性的粘合层发挥作用。Cu膜作为用于通过电解电镀法形成柱状电极35以及芯片间接合电极34的电镀种子层发挥作用。另外,在本工序中,在半导体晶圆的外周部形成与第二UBM膜32连接的电镀电极301(参照图6A、图6B)。电镀电极301与第二UBM膜32相同地,例如通过依次形成Ti膜和Cu膜而形成。电镀电极301在之后的工序中通过电解电镀法形成芯片间接合电极34和柱状电极35时使用。
接下来,使用公知的光刻技术,在第二UBM膜32的表面形成在芯片间接合电极34的形成区域具有开口部201A的抗蚀剂掩模201(图4I)。抗蚀剂掩模201通过在第二UBM膜32上涂覆感光性树脂,并对感光性树脂实施曝光和显影处理而形成。抗蚀剂掩模201的开口部201A内含上层绝缘膜22的第二开口部22B,使第二开口部22B露出。
接下来,使用电解电镀法,在抗蚀剂掩模201的开口部201A露出的第二UBM膜32的表面形成芯片间接合电极34(图4J)。具体而言,将半导体基板10的表面浸入至电镀液,并对与第二UBM膜32连接的电镀电极301(参照图6A、6B)供给电流。由此,在第二UBM膜32(电镀种子层)的露出部分析出金属,从而在第二UBM膜32上形成芯片间接合电极34。芯片间接合电极34经由第二UBM膜32与再布线40连接。作为芯片间接合电极34的材料,能够优选使用不产生朝向包含SnAg的焊料的扩散的Ni。在该情况下,成为在再布线40的表面的在第二开口露出的部分层叠有Ti、Cu以及Ni的结构。
接下来,使用公知的灰化工艺或者有机溶剂等除去抗蚀剂掩模201(图4K)。
接下来,以覆盖第二UBM膜32和芯片间接合电极34的表面的方式,在通过经过上述各处理而形成的结构体的表面粘贴第一层干膜211。第一层干膜211是具有感光性的膜状的抗蚀剂部件,例如,使用粘贴机进行粘贴。之后,对第一层干膜211实施曝光和显影处理,从而在柱状电极35的形成区域形成开口部211A。第一层干膜211的开口部211A内含上层绝缘膜22的第一开口部22A,使第一开口部22A露出(图4L)。
接下来,使用电解电镀法,在第一层干膜211的开口部211A露出的第二UBM膜32的表面形成柱状电极35(图4M)。具体而言,将半导体基板10的表面浸入至电镀液,并对与第二UBM膜32连接的电镀电极301(参照图6A、6B)供给电流。由此,在第二UBM膜32(电镀种子层)的露出部分析出金属,在第二UBM膜32上形成柱状电极35的下层部分35a。此外,优选以柱状电极35的下层部分35a的上表面的高度位置比第一层干膜211的上表面的高度位置低的方式形成下层部分35a。作为柱状电极35的材料,能够优选使用容易加工的Cu。在该情况下,构成第二UBM膜32的作为电镀种子层发挥作用的Cu膜被纳入构成柱状电极35的Cu。因此,成为在柱状电极35与再布线40之间夹有作为粘合层发挥作用的Ti膜的结构。
接下来,在第一层干膜211的表面粘贴第二层干膜212。第二层干膜212与第一层干膜211相同地,是具有感光性的膜状的抗蚀剂部件,例如使用粘贴机进行粘贴。之后,对第二层干膜212实施曝光和显影处理,从而在柱状电极35的形成区域形成开口部212A。即,第二层干膜212的开口部212A与第一层干膜的开口部211A连通,柱状电极35的下层部分35a在第二层干膜212的开口部212A露出(图4N)。
接下来,使用电解电镀法,在第二层干膜212的开口部212A中露出的柱状电极35的下层部分35a的表面形成柱状电极35的上层部分35b(图4O)。具体而言,将半导体基板10的表面浸入至电镀液,并对与第二UBM膜32连接的电镀电极301(参照图6A、图6B)供给电流。由此,在柱状电极35的下层部分35a的表面析出金属,而在柱状电极35的下层部分35a的表面形成柱状电极35的上层部分35b。此外,优选以柱状电极35的上层部分35b的上表面的高度位置比第二层干膜212的上表面的高度位置高的方式形成上层部分35b。
在这里,图6A是表示用于形成芯片间接合电极34和柱状电极35的电镀处理所使用的电镀电极301的结构的俯视图。图6B是沿着图6A中的B-B′线的剖视图。如图6A所示,电镀电极301与用于形成再布线40的电镀处理所使用的电镀电极300相同地,被设置在形成有多个第一半导体芯片101的半导体晶圆400的外周部的多个位置。多个电镀电极301分别与第二UBM膜32连接。第二UBM膜32和电镀电极301由作为粘合层发挥作用的Ti膜32a和作为电镀种子层发挥作用的Cu膜32b的层叠膜构成。在将半导体基板10的表面浸入至电镀液的状态下,对电镀电极301供给电流,从而在第二UBM膜32上形成芯片间接合电极34,之后,在将半导体基板10的表面浸入至其它电镀液的状态下,对电镀电极301供给电流,从而在第二UBM膜32上形成柱状电极35。
在形成柱状电极35之后,使用有机剥离液等除去第一层干膜211和第二层干膜212(图4P)。
接下来,以柱状电极35和芯片间接合电极34为掩模来除去第二UBM膜32的被第一层干膜211覆盖的不要部分(图4Q)。由此,用于形成芯片间接合电极34和柱状电极35的电镀处理所使用的电镀电极301也被除去。
接下来,将第二半导体芯片102搭载在第一半导体芯片101上(图4R)。第二半导体芯片102包含半导体基板50、下层绝缘膜51、再布线53、上层绝缘膜52以及芯片间接合电极54而构成。第一半导体芯片101与第二半导体芯片102的接合例如使用包含SnAg的焊料端子60。具体而言,在第二半导体芯片102侧的芯片间接合电极54处形成焊料端子60,之后,在使焊料端子60与第一半导体芯片101侧的芯片间接合电极34接触的状态下进行回流处理。由于芯片间接合电极34和54由不产生朝向焊料端子60的扩散的Ni构成,所以与芯片间接合电极34和54包含柱状电极35的构成材料亦即Cu的情况相比较,能够提高第一半导体芯片101与第二半导体芯片102的连接的可靠性。此外,在本实施方式中,例示出了由Ni构成第一半导体芯片101侧的芯片间接合电极34的情况,但也能够由对Ni和SnAg层叠而成的层叠膜来构成芯片间接合电极34。
接下来,例如,使用丝网印刷法,在通过经过上述各处理而形成的结构体的表面涂覆密封树脂70。柱状电极35和第二半导体芯片102被埋入密封树脂70内。之后,通过热处理使密封树脂70固化(图4S)。
接下来,通过使用研磨机对密封树脂70的表面进行研磨,来使柱状电极35的顶部露出。也可以根据需要对第一半导体芯片101的背面(与搭载第二半导体芯片102的一侧相反侧的面)进行研磨来进行半导体装置1的薄膜化(图4T)。另外,在本实施方式中,第二半导体芯片102的背面(同与第一半导体芯片101的接合面相反侧的面)被密封树脂70覆盖,但也可以使第二半导体芯片102的背面从密封树脂70露出。
接下来,在从密封树脂70露出的柱状电极35的顶部形成外部连接端子80(图4U)。外部连接端子80例如通过在柱状电极35的顶部搭载例如包含SnAg的焊球之后进行回流处理而形成。另外,也能够在通过丝网印刷在柱状电极35的顶部形成例如包含SnAg的导体膏之后进行回流处理,从而形成外部连接端子80。
根据本发明的实施方式的半导体装置1及其制造方法,由于柱状电极35包含Cu而构成,所以柱状电极35的加工变得容易。另一方面,由于与包含SnAg的焊料端子60连接的芯片间接合电极34和54不包含容易产生朝向焊料端子60的扩散的Cu,而是包含不产生朝向焊料端子60的扩散的Ni来作为主要材料,所以能够排除因长期使用而芯片间接合电极34和54消失的风险。即,根据本实施方式的半导体装置1,能够不损害薄型性地实现半导体芯片间的连接的可靠性的提高。
如上述那样,在本实施方式的半导体装置1中,柱状电极35和芯片间接合电极34由相互不同的材料构成。因此,需要分别实施用于形成柱状电极35的电镀处理和用于形成芯片间接合电极34的电镀处理。即,在柱状电极35和芯片间接合电极34由相互不同的材料构成的情况下,与由相同的材料构成这些电极的情况相比较,电镀处理的次数增加。
在这里,图7是表示比较例的半导体装置1X的结构的剖视图。比较例的半导体装置1X不具备本发明的实施方式的半导体装置1所具有的上层绝缘膜22,并将柱状电极35和芯片间接合电极34设置在再布线40上。比较例的半导体装置1X与本发明的实施方式的半导体装置1相同地,柱状电极35由Cu构成,芯片间接合电极34由Ni构成。
根据比较例的半导体装置1X,用于形成再布线40的电镀处理、用于形成芯片间接合电极34的电镀处理以及用于形成柱状电极35的电镀处理均使用与设置于再布线40的下层的UBM膜31连接的电镀电极来实施。
在这里,在电解电镀处理中,每当进行电镀处理时,都会产生电镀电极被电镀液蚀刻的现象。因此,在电镀处理的次数增加的情况下,存在电镀电极被除去而不能适当地实施电镀处理之虞。
另外,在电镀电极例如由Ti膜和Cu膜的层叠膜构成的情况下,也考虑到因电镀液而Cu膜被蚀刻,Ti膜未被蚀刻而剩下来,通过剩余的Ti膜来维持作为电镀电极的功能的情况。然而,由于Ti膜与Cu膜相比电阻值大,所以在使用仅由Ti膜构成的电镀电极来进行电镀处理的情况下,与使用由Ti膜和Cu膜的层叠膜构成的电镀电极来进行电镀处理的情况相比较,通过电镀处理析出的金属的生长速度降低。
另外,在半导体晶圆内混合有仅由Ti膜构成的电镀电极以及由Ti膜和Cu膜的层叠膜构成的电镀电极的情况下,通过电镀处理析出的金属的生长速度在半导体晶圆内不均匀,其结果是,存在再布线40的厚度、芯片间接合电极34的厚度、柱状电极35的高度在半导体晶圆内不均匀之虞。
在再布线40的厚度、芯片间接合电极34的厚度在半导体晶圆内不均匀的情况下,形成再布线40和芯片间接合电极34的电阻值在半导体装置的个体间产生偏差的结果。另外,由于需要利用密封树脂70将柱状电极35完全覆盖,所以在柱状电极35的高度在半导体晶圆内不均匀的情况下,需要加厚密封树脂70的厚度。密封树脂70的厚膜化使半导体晶圆的翘曲增加。若半导体晶圆的翘曲增加,则存在在形成了密封树脂70之后进行的密封树脂70的研磨、半导体基板10的研磨、半导体晶圆的切割(单片化)的各工序中,向工作台上固定半导体晶圆变得困难,无法实施上述各工序中的处理之虞。
根据比较例的半导体装置1X,用于形成再布线40的电镀处理、用于形成芯片间接合电极34的电镀处理以及用于形成柱状电极35的电镀处理均使用与设置于再布线40的下层的UBM膜31连接的电镀电极来实施,所以电镀电极的蚀刻过度地进展的风险较高,产生上述不良的风险较高。
另一方面,根据本发明的实施方式的半导体装置1,设置在第一半导体芯片101上的绝缘膜为下层绝缘膜21和上层绝缘膜22的两层结构,与形成在下层绝缘膜21上的第一UBM膜31连接的电镀电极300在用于形成再布线40的电镀处理时使用,与形成在上层绝缘膜22上的第二UBM膜32连接的电镀电极301在用于形成芯片间接合电极34和柱状电极35的电镀处理时使用。像这样,由于用于形成再布线40的电镀处理所使用的电镀电极和用于形成芯片间接合电极34和柱状电极35的电镀处理所使用的电镀电极不同,所以能够抑制电镀电极的蚀刻过度地进展的风险,能够抑制产生上述不良的风险。
像这样,根据本发明的实施方式的半导体装置1及其制造方法,柱状电极35和芯片间接合电极34由相互不同的材料构成,所以与这些电极由相同的材料构成的情况相比较,电镀处理的次数增加,但能够抑制伴随着电镀处理的次数的增加的电镀电极被过度蚀刻的风险,能够避免在电镀电极被过度蚀刻的情况下所产生的不良的产生。
此外,第一半导体芯片101是本发明中的第一半导体芯片的一个例子。第二半导体芯片102是本发明中的第二半导体芯片的一个例子。再布线40是本发明中的再布线的一个例子。下层绝缘膜21是本发明中的第一绝缘膜的一个例子。上层绝缘膜22是本发明中的绝缘膜或者第二绝缘膜的一个例子。柱状电极35是本发明中的第一电极的一个例子。芯片间接合电极34是本发明中的第二电极的一个例子。芯片间接合电极54是本发明中的第三电极的一个例子。第一UBM膜31是本发明中的第一导电膜的一个例子。第二UBM膜32是本发明中的导电膜或者第二导电膜的一个例子。电镀电极300是本发明中的第一电镀电极的一个例子。电镀电极301是本发明中的第二电镀电极的一个例子。
Claims (13)
1.一种半导体装置,包含:
再布线,被设置在第一半导体芯片的主面上;
绝缘膜,覆盖所述再布线的表面,具有使所述再布线分别局部地露出的第一开口部以及第二开口部;
第一电极,被设置在所述绝缘膜上,在所述第一开口部与所述再布线连接,由与所述再布线相同的材料构成;以及
第二电极,被设置在所述绝缘膜上,在所述第二开口部与所述再布线连接,由与所述第一电极不同的材料构成。
2.一种半导体装置,包含:
再布线,被设置在第一半导体芯片的主面上;
绝缘膜,覆盖所述再布线的表面,具有使所述再布线分别局部地露出的第一开口部以及第二开口部;
第一电极,被设置在所述绝缘膜上,在所述第一开口部经由导电膜与所述再布线连接;以及
第二电极,被设置在所述绝缘膜上,在所述第二开口部与所述再布线连接,由与所述第一电极不同的材料构成。
3.根据权利要求1所述的半导体装置,其中,
所述第一电极以及所述第二电极经由导电膜与所述再布线连接。
4.根据权利要求2所述的半导体装置,其中,
所述第二电极经由所述导电膜与所述再布线连接。
5.根据权利要求1~4中任一项所述的半导体装置,其中,
所述第一电极包含铜,
所述第二电极包含镍。
6.根据权利要求1~5中任一项所述的半导体装置,其中,
还包含第二半导体芯片,所述第二半导体芯片在主面具有与所述第二电极连接的第三电极。
7.根据权利要求6所述的半导体装置,其中,
所述第二电极和所述第三电极经由焊料连接。
8.一种半导体装置,包含:
第一半导体芯片;
第一绝缘膜,被设置于所述第一半导体芯片的主面;
再布线,经由第一导电膜而设置于所述第一绝缘膜的表面;
第二绝缘膜,覆盖所述再布线的表面,具有使所述再布线分别局部地露出的第一开口部以及第二开口部;
第一电极,被设置在所述第二绝缘膜上,一端在所述第一开口部经由第二导电膜与所述再布线连接,另一端与外部连接端子连接;
第二电极,被设置在所述第二绝缘膜上,在所述第二开口部经由所述第二导电膜与所述再布线连接,由与所述第一电极不同的材料构成;以及
第二半导体芯片,在主面具有经由焊料与所述第二电极连接的第三电极。
9.一种半导体装置的制造方法,包含:
在第一半导体芯片的主面形成第一绝缘膜的工序;
在所述第一绝缘膜的表面隔着第一导电膜形成再布线的工序;
形成覆盖所述再布线的表面并具有使所述再布线分别局部地露出的第一开口部以及第二开口部的第二绝缘膜的工序;
在所述第二绝缘膜上形成在所述第一开口部经由第二导电膜与所述再布线连接的第一电极的工序;
在所述第二绝缘膜上形成在所述第二开口部经由所述第二导电膜与所述再布线连接的、由与所述第一电极不同的材料构成的第二电极的工序;以及
将在主面具有第三电极的第二半导体芯片的所述第三电极与所述第二电极连接的工序。
10.根据权利要求9所述的半导体装置的制造方法,其中,
通过使用了与所述第一导电膜连接的第一电镀电极的电解电镀处理来形成所述再布线,
通过使用了与所述第二导电膜连接的第二电镀电极的电解电镀处理来形成所述第一电极以及所述第二电极。
11.根据权利要求9或者10所述的半导体装置的制造方法,其中,
所述第一电极包含铜,
所述第二电极包含镍。
12.根据权利要求9~11中任一项所述的半导体装置的制造方法,其中,
通过多次电解电镀处理来形成所述第一电极。
13.根据权利要求9~12中任一项所述的半导体装置的制造方法,其中,还包含:
以将所述第一电极和所述第二半导体芯片埋入内部的方式形成密封树脂的工序;
对所述密封树脂的表面进行研磨而使所述第一电极的表面露出的工序;以及
在露出的所述第一电极的表面形成外部连接端子的工序。
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