CN108321203B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN108321203B
CN108321203B CN201711381037.3A CN201711381037A CN108321203B CN 108321203 B CN108321203 B CN 108321203B CN 201711381037 A CN201711381037 A CN 201711381037A CN 108321203 B CN108321203 B CN 108321203B
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region
insulating film
recess
semiconductor device
isolation trench
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CN108321203A (zh
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藤井宏基
森隆弘
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本发明提供一种半导体器件及其制造方法。在填埋p+源极区域(SC)与p+漏极区域(DC)之间的隔离槽(TNC)的内部的隔离绝缘膜(SIS)的上表面形成有凹部(HL)。p‑漂移区(DFT)位于隔离槽(TNC)的下侧且与p+漏极区域(DC)连接。门电极(GE)填埋凹部(HL)的内部。n型杂质区域(NH)位于p‑漂移区(DFT)的下侧且凹部(HL)的正下方。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件及其制造方法。
背景技术
为了实现高耐压化，已知在高耐压LDMOS(Laterally Diffused Metal OxideSemiconductor，横向扩散金属氧化物半导体)晶体管的门极与漏极之间采用STI(ShallowTrench Isolation，浅沟道隔离)结构。例如在日本特开2015-162581号公报、日本特开2009-278100号公报等中公开有上述结构。
上述两份公报中公开了，在填埋隔离槽内的隔离绝缘膜的上表面形成有槽，门电极的一部分埋入于该槽内的结构。
上述两份公报所记载的结构能够改善被称作热载流子注入(HCI：Hot CarrierInjection)的现象。在此，热载流子注入是指：被LDMOS晶体管的漏极电场加速而具有较高能量的载流子(热载流子)注入到门极绝缘膜从而导致晶体管的特性(Ids、Vth)发生变化的现象。
发明内容
然而，上述两份公报所记载的技术存在抑制热载流子注入到门极绝缘膜的效果有时不够充分的问题。
其他问题及新的特征通过本说明书中的记载及附图变得明朗。
根据一种实施方式所涉及的半导体器件，在填埋第一导电型的源极区域与漏极区域之间的隔离槽内的隔离绝缘膜的上表面形成有凹部。第一导电型的漂移区位于隔离槽的下侧且与漏极区域连接。门电极填埋凹部内。第二导电型的第一杂质区域位于漂移区的下侧且凹部的正下方。
根据一种实施方式所涉及的半导体器件的制造方法，形成隔离绝缘膜，所述隔离绝缘膜填埋隔离槽内，并且在所述隔离绝缘膜的上表面具有凹部。接着，形成第二导电型的第一杂质区域，所述第二导电型的第一杂质区域位于漂移区的下侧且凹部的正下方。接着，形成门电极，所述门电极在夹在源极区域与漂移区之间的主表面之上夹着门极绝缘膜与该主表面对置，并且所述门电极填埋凹部内。
本发明的上述及其他目的、特征、局势、优点通过参考附图进行说明的本发明的下述详细说明将变得明朗。
附图说明
图1是概略地表示第1实施方式的芯片状态的半导体器件的结构的平面图。
图2是表示图1所示半导体器件的结构的剖视图。
图3是表示图2所示LDpMOS晶体管部的结构的平面图。
图4是沿图3的Ⅳ-Ⅳ线剖切的示意剖视图。
图5是表示沿图4的V-V线的杂质浓度分布的图。
图6是用于说明凹槽下的n型杂质区域的位置的局部放大剖视图。
图7是用于说明凹槽下的n型杂质区域的位置的局部放大剖视图。
图8是表示图4所示半导体器件的制造方法的第一工序的剖视图。
图9是表示图4所示半导体器件的制造方法的第二工序的剖视图。
图10是表示图4所示半导体器件的制造方法的第三工序的剖视图。
图11是表示图4所示半导体器件的制造方法的第四工序的剖视图。
图12是表示图4所示半导体器件的制造方法的第五工序的剖视图。
图13是表示图4所示半导体器件的制造方法的第六工序的剖视图。
图14是表示图4所示半导体器件的制造方法的第七工序的剖视图。
图15是表示图4所示半导体器件的制造方法的第八工序的剖视图。
图16是表示比较例的半导体器件的碰撞离化率分布的图。
图17是表示第1实施方式的半导体器件的碰撞离化率分布的图。
图18是表示沿图16及图17的A-A线的电场强度的图。
图19是表示沿图16及图17的A-A线的碰撞离化发生率的图。
图20是表示第1实施方式及比较例中的导通电阻Rsp与门极电流Ig之间的关系的图。
图21是表示第1实施方式及比较例中的关态击穿电压BVoff与门极电流Ig之间的关系的图。
图22是表示比较例的半导体器件的等位线的图。
图23是表示第1实施方式的半导体器件的等位线的图。
图24是表示第2实施方式的半导体器件的结构的剖视图。
图25是表示图24所示半导体器件的制造方法的剖视图。
图26是表示第1实施方式、第2实施方式及比较例中的导通电阻Rsp与门极电流Ig之间的关系的图。
图27是表示第1实施方式、第2实施方式及比较例中的关态击穿电压BVoff与门极电流Ig之间的关系的图。
图28是表示第3实施方式的半导体器件的结构的剖视图。
图29是表示图28所示半导体器件的制造方法的第一工序的剖视图。
图30是表示图28所示半导体器件的制造方法的第二工序的剖视图。
图31是表示图28所示半导体器件的制造方法的第三工序的剖视图。
图32是表示图28所示半导体器件的制造方法的第四工序的剖视图。
图33是表示图28所示半导体器件的制造方法的第五工序的剖视图。
图34是表示比较例的半导体器件的制造方法的第一工序的剖视图。
图35是表示比较例的半导体器件的制造方法的第二工序的剖视图。
图36是表示第3实施方式的变形例的半导体器件的结构的剖视图。
图37是表示图36所示半导体器件的制造方法的剖视图。
图38是用于说明第1实施方式的结构也能够适用于LDnMOS晶体管的情况的剖视图。
具体实施方式
以下，根据附图，对实施方式进行说明。
(第1实施方式)
如图1所示，本实施方式的半导体器件CH例如为芯片状态，且具有半导体基板。在半导体基板的表面配置有驱动电路DRI、预驱动电路PDR、模拟电路ANA、电源电路PC、逻辑电路LC、输入/输出电路1OC等的形成区域。
另外，本实施方式的半导体器件并不限定于半导体芯片，也可以是晶片状态或被密封树脂密封的封装状态。
如图2所示，本实施方式的半导体器件包括：高耐压CMOS(Complementary MetalOxide Semiconductor，互补型金属氧化物半导体)晶体管、逻辑CMOS晶体管及双极晶体管。
高耐压CMOS晶体管具有n沟道型LD(Laterally Diffused，横向扩散)MOS晶体管LNT及p沟道型LDMOS晶体管LPT。并且，逻辑CMOS晶体管具有n沟道型MOS晶体管NTR及p沟道型MOS晶体管PTR。
以下，将n沟道型LDMOS晶体管称作nLDMOS晶体管，将p沟道型LDMOS晶体管称作pLDMOS晶体管。并且，将n沟道型MOS晶体管称作nMOS晶体管，将p沟道型MOS晶体管称作pMOS晶体管。
各个晶体管形成于半导体基板SUB的主表面MS上。各个晶体管的形成区域通过DTI(Deep Trench Isolation，深沟道隔离)而被电隔离。DTI具有形成在半导体基板SUB的主表面MS的槽DTR及填埋该槽DTR内的绝缘膜BIL。
在逻辑CMOS晶体管的形成区域中，在半导体基板SUB的基板区域SB之上排列配置有p型阱区PWL及n型阱区NWL。在p型阱区PWL配置有nMOS晶体管NTR，在n型阱区NWL配置有pMOS晶体管PTR。
nMOS晶体管NTR的形成区域和pMOS晶体管PTR的形成区域通过STI(ShallowTrench Isolation，浅沟道隔离)而被电隔离。STI具有形成在半导体基板SUB的主表面MS的隔离槽TNC及填埋该隔离槽TNC内的隔离绝缘膜SIS。
STI的隔离槽TNC配置成其从主表面MS的深度浅于DTI的槽DTR从主表面MS的深度。STI的隔离槽TNC配置成其深度浅于p型阱区PWL及n型阱区NWL。
上述nMOS晶体管NTR具有n+源极区域SC、n+漏极区域DC、门极绝缘膜GI及门电极GE。n+源极区域SC及n+漏极区域DC彼此隔着间隔地配置在半导体基板SUB的主表面MS。门电极GE经由门极绝缘膜GI配置在夹在n+源极区域SC与n+漏极区域DC之间的半导体基板SUB的主表面MS上。
上述pMOS晶体管PTR具有p+源极区域SC、p+漏极区域DC、门极绝缘膜GI及门电极GE。p+源极区域SC及p+漏极区域DC彼此隔着间隔地配置在半导体基板SUB的主表面MS。门电极GE经由门极绝缘膜GI配置在夹在p+源极区域SC与p+漏极区域DC之间的半导体基板SUB的主表面MS上。
在双极晶体管的配置区域中，在半导体基板SUB的基板区域SB之上配置有n+埋入区BL。在该n+埋入区BL之上配置有n-阱区HWL。在该n-阱区HWL之上配置有p型阱区PWL及n型阱区NWL。p型阱区PWL和n型阱区NWL夹着n-阱区HWL的一部分而彼此相邻。
在p型阱区PWL配置有p+基极区域BC及n+发射极区域EC。在n型阱区NWL配置有n+集电极区域CC。由p+基极区域BC、n+发射极区域EC及n+集电极区域CC构成双极晶体管BTR。
在p+基极区域BC与n+发射极区域EC之间以及在n+发射极区域EC与n+集电极区域CC之间配置有STI。由此，p+基极区域BC、n+发射极区域EC及n+集电极区域CC彼此电隔离。
各个杂质区域(n+源极区域SC、n+漏极区域DC、p+基极区域BC、n+发射极区域EC、n+集电极区域CC)与配线层INC电连接。
具体而言，以覆盖半导体基板SUB的主表面MS上的方式配置有层间绝缘膜(未图示)。在该层间绝缘膜配置有到达各个杂质区域的接触孔CN。在该接触孔CN内埋入有柱形导电层PL。在层间绝缘膜之上，以与柱形导电层PL接触的方式配置有配线层INC。由此，配线层INC经由柱形导电层PL与各个杂质区域电连接。
以下，参照图3及图4对高耐压CMOS晶体管的pLDMOS晶体管进行说明。
如图3及图4所示，在pLDMOS晶体管的配置区域中，在半导体基板SUB的基板区域SB之上配置有n+埋入区BL。在该n+埋入区BL之上配置有n-阱区HWL(第一阱区)。在该n-阱区HWL之上配置有p-漂移区DFT及n型阱区NWL(第二阱区域)。n-阱区HWL的n型杂质浓度低于n型阱区域NWL的n型杂质浓度。
p-漂移区DFT及n型阱区NWL彼此相邻以形成pn结。由p-漂移区DFT及n型阱区NWL构成的pn结从半导体基板SUB的主表面MS朝向深度方向延伸。
在半导体基板SUB的主表面MS配置有STI。该STI具有隔离槽TNC及隔离绝缘膜SIS。隔离槽TNC配置在p-漂移区DFT。即，p-漂移区DFT包围隔离槽TNC的周围且位于隔离槽TNC的下侧。隔离绝缘膜SIS填埋隔离槽TNC。在隔离绝缘膜SIS的上表面配置有凹部HL。该凹部HL的底面位于隔离绝缘膜SIS内。即，凹部HL的底部并未抵达p-漂移区DFT。
在n型阱区NWL内的主表面MS配置有p+源极区域SC及n+接触区域WC。p+源极区域SC与n+接触区域WC彼此相邻。p+源极区域SC与n型阱区NWL及n+接触区域WC均形成pn结。n+接触区域WC的n型杂质浓度高于n型阱区NWL的n型杂质浓度。
在p-漂移区DFT内的主表面MS配置有p+漏极区域DC。p+漏极区域DC与隔离槽TNC相邻。p+漏极区域DC的p型杂质浓度高于p-漂移区DFT的p型杂质浓度。隔离槽TNC夹在p+漏极区域DC与p+源极区域SC之间。
在夹在p+源极区域SC与p-漂移区DFT之间的主表面MS之上，经由门极绝缘膜GI配置有门电极GE。门电极GE以与夹在p+源极区域SC与p-漂移区DFT之间的主表面MS处于绝缘状态的方式与该主表面MS对置。
门电极GE搭载于STI隔离绝缘膜SIS之上且填埋隔离绝缘膜SIS的凹部HL内。门电极GE从填埋凹部HL内的部分进一步向漏极区域DC侧延伸。该门电极GE隔着隔离绝缘膜SIS分别与p-漂移区DFT及n-阱区HWL对置。
在p-漂移区DFT的下侧配置有n型杂质区域NH(第一杂质区域)，并且该n型杂质区域NH配置成具有位于凹部HL的正下方的部分。n型杂质区域NH可以与p-漂移区DFT相接触，但是也可以不与p-漂移区DFT相接触。
如图5所示，n型杂质区域NH例如具有1×1017cm-3～6×1017cm-3的n型杂质浓度CA。另一方面，n-阱区HWL例如具有5×1015cm-3的n型杂质浓度CB。n型杂质区域NH与n-阱区HWL的边界为具有例如1×1016cm-3的n型杂质浓度的部分。
如图6所示，在本发明中，凹部HL的正下方是指：在俯视状态下将凹部HL放大与从凹部HL的底面到隔离槽TNC的底面为止的距离H相同的尺寸H后所得区域RDB(图3中虚线表示的区域)内的正下方区域。
在此，将从凹部HL的漏极区域DC侧的端部HLD向漏极区域DC侧位移上述尺寸H的位置设为位置P1。此时，n型杂质区域NH的漏极区域DC侧的端部NHD位于比位置P1更靠源极区域SC侧。
并且，将从凹部HL的源极区域SC侧的端部HLS向源极区域SC侧位移上述尺寸H的位置设为位置P2。此时，优选n型杂质区域NH的源极区域SC侧的端部NHS位于比位置P2更靠漏极区域DC侧。
并且，优选n型杂质区域NH仅位于凹部HL的正下方。具体而言，优选n型杂质区域NH配置在上述区域RDB内而在俯视视时未超出所述区域RDB。另外，俯视是指：例如，如图3所示，从与半导体基板SUB的主表面MS正交的方向观察时的情况。
并且，n型杂质区域NH的源极区域SC侧的端部NHS位于比隔离槽TNC的源极区域SC侧的端部TNCS更靠漏极区域DC侧。并且，n型杂质区域NH的源极区域SC侧的端部NHS位于比p-漂移区DFT的源极区域SC侧的端部DFTS更靠漏极区域DC侧。
但是，如图7所示，n型杂质区域NH的源极区域侧端部NHS也可以位于比隔离槽TNC的源极区域SC侧的端部TNCS更靠源极区域SC侧。并且，n型杂质区域NH的源极区域侧端部NHS也可以位于比p-漂移区DFT的源极区域SC侧的端部DFTS更靠源极区域SC侧。
如图4所示，从源极区域SC朝向漏极区域DC的方向(源极-漏极方向)上的隔离槽TNC的长度为Ld。凹部HL位于隔离槽TNC的源极区域SC侧的端部TNCS到自隔离槽TNC的源极区域SC侧的端部TNCS位移上述长度Ld的1/3的距离的位置的范围内。
具体而言，凹部HL的漏极区域DC侧的端部HLD与隔离槽TNC的源极区域SC侧的端部TNCS之间的尺寸Lh为上述长度Ld的1/3以下。
并且，n型杂质区域NH也位于隔离槽TNC的源极区域SC侧的端部TNCS到自隔离槽TNC的源极区域SC侧的端部TNCS位移隔离槽TNC的长度Ld的1/3的距离的位置的范围内。
具体而言，n型杂质区域NH的漏极区域DC侧的端部NHD与隔离槽TNC的源极区域SC侧的端部TNCS之间的上述源极-漏极方向上的尺寸为上述长度Ld的1/3以下。
并且，n型杂质区域NH的源极区域SC侧的端部NHS与隔离槽TNC的源极区域SC侧的端部TNCS之间的上述源极-漏极方向上的尺寸为上述长度Ld的1/3以下。
并且，凹部HL的源极区域SC侧的端部HLS与隔离槽TNC的源极区域SC侧的端部TNCS之间的尺寸Ls为门极绝缘膜GI的膜厚尺寸以上。
在半导体基板SUB的主表面MS之上配置有层间绝缘膜IS。在层间绝缘膜IS配置有多个接触孔CN1、CN2、CN3。接触孔CN1到达p+源极区域SC及n+接触区域WC这双方。接触孔CN2到达门电极GE。接触孔CN3到达p+漏极区域DC。
在各个接触孔CN1、CN2、CN3中分别埋入有柱形导电层PL。在层间绝缘膜IS之上配置有多个配线层INC。多个配线层分别与柱形导电层PL相接触。
由此，一个配线层INC经由柱形导电层PL与p+源极区域SC及n+接触区域WC这两者电连接。另一个配线层INC经由柱形导电层PL与门电极GE电连接。而且，又一个配线层INC经由柱形导电层PL与p+漏极区域DC电连接。
接下来，参照图8至图15对本实施方式的半导体器件的制造方法进行说明。
如图8所示，在p-基板区域SB之上形成n-阱区HWL。在n-阱区HWL之上形成n型阱区NWL及p型漂移区DFT。由此，制备出在内部具有p-基板区域SB、n-阱区HWL、n型阱区HWL及p型漂移区DFT的半导体基板SUB。
如图9所示，在半导体基板SUB的主表面之上形成例如由氧化硅膜形成的门极绝缘膜GI。门极绝缘膜GI形成为例如几μm～几十μm的膜厚。在所述门极绝缘膜GI之上形成例如由掺杂了杂质的多晶硅(掺杂多晶硅)形成的导电膜GE1。在该导电膜GE1之上形成例如由氮化硅膜形成的硬掩模层HM。导电膜GE1及硬掩模层HM分别形成为例如几十nm的膜厚。
接着，利用通常的照相制版技术及蚀刻技术对硬掩模层HM进行图案化。将该图案化的硬掩模层HM作为掩模对导电膜GE1、门极绝缘膜GI及半导体基板SUB进行蚀刻。通过该蚀刻，在半导体基板SUB的主表面MS形成隔离槽TNC。
如图10所示，以填埋隔离槽TNC内的方式形成例如由氧化硅膜形成的绝缘膜BI(埋入绝缘膜)。在形成该绝缘膜BI时，例如以填埋隔离槽TNC内的方式在半导体基板SUB的整个主表面上形成绝缘膜BI。接着，例如利用CMP(Chemical Mechanical Polishing，化学机械研磨)对绝缘膜BI进行研磨直至硬掩模层HM的表面露出。由此，绝缘膜BI仅残留在隔离槽TNC内。
接着，利用通常的照相制版技术形成光致抗蚀剂图案PR1。该光致抗蚀剂图案PR1具有使绝缘膜BI的一部分表面暴露的开口。将该光致抗蚀剂图案PR1作为掩模对绝缘膜BI进行蚀刻。该蚀刻之后，例如通过灰化等去除光致抗蚀剂图案PR1。
如图11所示，通过上述蚀刻，在绝缘膜BI形成有贯穿该绝缘膜BI而到达p型漂移区DFT的贯穿孔TH。经由该贯穿孔TH将n型杂质注入半导体基板SUB。n型杂质的离子注入的条件例如为：注入能量为几百keV～几MeV，剂量为1012～1013cm-2。通过该n型杂质的注入，在p型漂移区DFT的下侧且在贯穿孔TH的正下方区域形成n型杂质区域NH。
如图12所示，以覆盖贯穿孔TH的内壁面且覆盖硬掩模层HM及绝缘膜BI的上表面的方式形成例如由氧化硅膜形成的绝缘膜IL(包覆绝缘膜)。绝缘膜IL形成为例如贯穿孔TH的深度的1/3左右的膜厚。由覆盖贯穿孔TH内壁面的绝缘膜IL的外表面构成凹部HL的内壁面。
接着，以填埋凹部HL内且覆盖绝缘膜IL的上表面的方式形成由掺杂多晶硅形成的导电膜GE2。导电膜GE2形成为例如几百nm的膜厚。接着，例如利用CMP对导电膜GE2进行研磨直至绝缘膜IL的表面露出。
如图13所示，通过上述CMP，导电膜GE2仅残留在凹部HL的内部。接着，例如通过蚀刻去除绝缘膜IL的一部分及硬掩模层HM。
如图14所示，通过上述蚀刻去除，暴露出导电膜GE1的表面。并且，通过上述蚀刻去除，绝缘膜IL仅残留在贯穿孔TH内。由该残留在贯穿孔TH内的绝缘膜IL及绝缘膜BI构成隔离绝缘膜SIS。
接着，在半导体基板SUB的整个主表面MS之上形成例如由掺杂多晶硅形成的导电膜GE3。导电膜GE3形成为例如几十nm的膜厚。接着，利用通常的照相制版技术及蚀刻技术对导电膜GE3、GE1进行图案化。由此，形成由导电膜GE1、GE2及GE3构成的门电极GE。
如图15所示，在门电极GE的侧壁上形成侧壁绝缘膜SW。接着，通过离子注入等将n型杂质及p型杂质注入半导体基板SUB的主表面MS。由此，在半导体基板SUB的主表面MS形成p+源极区域SC、p+漏极区域DC及n+接触区域WC。
如图4所示，通过形成层间绝缘膜IS、柱形导电层PL、配线层INC等，制造出本实施方式的半导体器件。
另外，图15中的导电膜GE1、GE2、GE3在图4中表示为一个门电极GE。并且，图15中的绝缘膜IL、BI在图4中表示为一个隔离绝缘膜SIS。并且，在图4中省略了图15中的侧壁绝缘膜SW。
并且，图2中的nLDMOS晶体管LNT与上述pLDMOS晶体管LPT为导电型相反的结构。具体而言，在n+埋入区BL之上配置有p-阱区HWL(第一阱区)。在该p-阱区HWL之上配置有n-漂移区DFT及p型阱区PWL(第二阱区)。在p型阱区PWL内的主表面MS上形成有n+源极区域SC及p+接触区域WC。在n-漂移区DFT内的主表面MS上形成有n+漏极区域DC。在n-漂移区DFT的下侧，以具有位于凹部HL的正下方的部分的方式配置有p型杂质区域PH(第一杂质区域)。
接下来，通过对比不具有图4中的n型杂质区域NH的比较例，对本实施方式的作用效果进行说明。
在BiC-DMOS(Bipolar Complementary Metal Oxide Semiconductor，双极互补型金属氧化物半导体)领域中，如图2所示，混合搭载有LDMOS晶体管、CMOS晶体管以及双极晶体管。在这种领域中，其设计也在不断进化。由此，STI逐渐取代以往的LOCOS(LoCalOxidation of Silicon，硅局部氧化隔离)。
此时，在LDMOS晶体管的漂移区也会应用STI。在STI中，隔离槽的角部的形状是尖锐的。因此，在高电压施加于漏极的情况下，电场容易集中在隔离槽的角部。根据该电场的集中，在STI的端部容易产生碰撞离化。通过碰撞离化而产生的电子-空穴对会生成界面态，或电子-空穴对通过散射会注入到氧化膜中。由此，热载流子波动变大的问题变得显著。尤其，在pLDMOS晶体管中，若电子注入到门极绝缘膜中，则会引起门极绝缘膜的绝缘击穿。
对此，本发明人通过器件模拟试验对图4中的本实施方式的结构及不具有图4中的n型杂质区域NH的比较例的结构的碰撞离化的抑制效果进行了调查。其结果在图16及图17中示出。
图16中示出比较例中的半导体器件的碰撞离化率分布，图17中示出本实施方式中的半导体器件的碰撞离化率分布。从其结果可知，在比较例中，如图16所示，在STI的源极区域侧的下端，碰撞离化率变高。与此相对，在本实施方式中，如图17所示，在STI的源极区域侧的下端，碰撞离化率低于比较例。
并且，本发明人对沿图16及图17中的A-A线的电场强度及碰撞离化发生率进行了调查。其结果在图18及图19中示出。
图18中示出沿图16及图17中的A-A线的电场强度，图19中示出沿图16及图17中的A-A线的碰撞离化发生率。根据图18及图19的结果可知，在本实施方式中，电场强度及碰撞离化发生率这两者均低于比较例。尤其，在STI的源极区域侧的下端附近，本实施方式的电场强度及碰撞离化发生率低于比较例。
而且，本发明人还对本实施方式及比较例中的导通电阻Rsp与门极电流Ig之间的关系以及关态击穿电压BVoff与门极电流Ig之间的关系进行了调查。其结果在图20及图21中示出。
图20中示出本实施方式及比较例中的导通电阻Rsp与门极电流Ig之间的关系，图21中示出本实施方式及比较例中的关态击穿电压BVoff与门极电流Ig之间的关系。根据图20及图21的结果可知，与比较例相比，在本实施方式中，导通电阻Rsp虽然增加了1～2％，但能够在维持关态击穿电压BVoff的状态下降低门极电流Ig。
在此，门极电流Ig是指：在半导体基板SUB与门电极GE之间存在门极绝缘膜GI等的情况下流过的电流。因此，门极电流Ig较小意味着从半导体基板SUB注入到门电极GE的载流子的量较少。由此，从门极电流Ig减少的上述结果可知，与比较例相比，本实施方式能够抑制热载流子注入到门电极GE内。
而且，本发明人针对本实施方式和比较例还调查了对测量元件施加了一定的应力时的半导体基板内的电位分布。其结果在图22及图23中示出。
图22中示出比较例中的半导体器件的等位线，图23中示出本实施方式中的半导体器件的等位线。在该模拟试验中，针对开态击穿电压为80V的元件，将门极电压Vg设为-1.3V，将漏极电压Vd设为-80V，并观察了电位分布。
根据图22及图23的结果可知，在比较例中，STI的源极区域侧的下端成为了-10V，而在本实施方式中，STI的源极区域侧的下端成为了-8V。并且，与比较例相比，在本实施方式中，在STI的源极区域侧的端部附近，等位线之间的间隔变宽，可知电场变得缓和。
根据上述结果可以认为，在本实施方式中，由于配置有n型杂质区域NH(图4)，因而STI的端部处的电场变得缓和，由此碰撞离化得到了抑制，热载流子向门电极GE的注入得到了进一步抑制。
如上所述，在本实施方式中，如图4所示，在p型漂移区DFT的下侧且凹部HL的正下方区域配置有n型杂质区域NH。因此，如上所述，能够在维持关态击穿电压BVoff的状态下进一步抑制热载流子注入到门电极GE，其结果能够抑制门极电流Ig。
并且，在本实施方式中，在仅在凹部HL的正下方区域配置有n型杂质区域NH的情况下，能够抑制热载流子注入到门电极GE，并且基于RESURF(Reduced SURface Field，降低表面电场)效果而得到高耐压。以下，对此进行说明。
在图4的结构中，假设凹部HL未设置在隔离绝缘膜SIS且n型杂质区域NH配置在隔离槽TNC正下方区域的整个区域。此时，由于n型杂质区域NH设置在隔离槽TNC正下方区域的整个区域，因此不能得到基于p-漂移区DFT与n-阱区HWL沿着横向接合而得到的RESURF效果。其结果，容易产生电场集中，会导致耐压下降。
要想抑制上述耐压的下降，需要提高p-漂移区DFT的p型杂质浓度。然而，若提高p-漂移区DFT的p型杂质浓度，则会促进STI端部附近处的电场集中。由此会促进热载流子注入到门电极GE。
相对于此，在本实施方式中，仅在凹部HL的正下方区域配置有n型杂质区域NH。因此，能够确保足够的p-漂移区DFT与n-阱区HWL沿着横向接合的长度。由此，基于RESURF效果而能够得到高耐压。
也就是说，耗尽层从p-漂移区DFT与n-阱区HWL之间的pn结部上下扩展，由此，电场分布变得均匀，电场集中变得缓和，其结果耐压得到提高。
并且，不需要为了获得高耐压而提高p-漂移区DFT的p型杂质浓度。因此，也不会产生提高了p-漂移区DFT的p型杂质浓度时产生的促进热载流子注入的现象。
如上所述，能够抑制热载流子注入到门电极GE，并且还能够基于RESURF效果而得到高耐压。
并且，在本实施方式中，n型杂质区域NH位于隔离槽TNC的源极区域SC侧的端部TNCS到自隔离槽TNC的源极区域SC侧的端部TNCS位移隔离槽TNC的长度Ld的1/3的距离的位置的范围内。通过使n型杂质区域NH位于上述范围内，能够维持上述基于RESURF效果而得到的高耐压。
并且，若凹部HL的源极区域SC侧的端部HLS与隔离槽TNC的源极区域SC侧的端部TNCS之间的尺寸Ls小于门极绝缘膜GI的膜厚，则热载流子容易通过该较薄的隔离绝缘膜SIS部分而注入到门电极GE。因此，通过将上述尺寸Ls设为门极绝缘膜GI的膜厚以上，能够抑制热载流子通过该较薄的隔离绝缘膜SIS部分而注入到门电极GE。
并且，n型杂质区域NH的源极区域SC侧的端部NHS与隔离槽TNC的源极区域SC侧的端部TNCS之间的上述源极-漏极方向上的尺寸为上述隔离槽TNC的长度Ld的1/3以下。由此，通过n型杂质区域NH充分能够抑制热载流子注入到门电极GE。
并且，如图6所示，n型杂质区域NH的漏极区域DC侧的端部NHD位于比上述位置P1更靠源极区域SC侧。由此，能够抑制热载流子注入到门电极GE，并且还能够得到上述RESURF效果。
并且，如图4所示，n型杂质浓度比n型阱区NWL的n型杂质浓度低的n+阱区沿着横向与p+漂移区DFT连接从而构成pn结。由此，能够得到上述RESURF效果。
(第2实施方式)
如图24所示，本实施方式的结构与第1实施方式的结构的不同点在于，本实施方式的结构还具有p型杂质区域PH(第二杂质区域)。p型杂质区域PH的p型杂质浓度高于p-漂移区DFT的p型杂质浓度。优选该p型杂质区域PH的浓度峰值低于n型杂质区域NH的浓度峰值。
p型杂质区域PH配置在凹部HL的正下方区域。只要p型杂质区域PH配置在p-漂移区DFT内，其与隔离绝缘膜SIS接触或不与隔离绝缘膜SIS接触均可。优选p型杂质区域PH配置成在深度方向上与n型杂质区域NH之间隔着间隔。
p型杂质区域PH的漏极区域DC侧的端部PHD位于比图6中说明的位置P1更靠源极区域SC侧。优选p型杂质区域PH的源极区域SC侧的端部PHS位于比图6中说明的位置P2更靠漏极区域DC侧。
并且，优选p型杂质区域PH仅配置在凹部HL的正下方区域。具体而言，优选p型杂质区域PH在俯视时配置在图3中说明的区域RDB内而不超出所述区域RDB。
并且，p型杂质区域PH的源极区域SC侧的端部PHS位于比隔离槽TNC的源极区域SC侧的端部TNCS更靠漏极区域DC侧。并且，p型杂质区域PH的源极区域SC侧的端部PHS位于比p-漂移区DFT的源极侧端部DFTS更靠漏极区域DC侧。
但是，与图7所示的n型杂质区域NH相同，p型杂质区域PH的源极侧端部PHS也可以位于比隔离槽TNC的源极区域SC侧的端部TNCS更靠源极区域SC侧。并且，p型杂质区域PH的源极侧端部PHS也可以位于比p-漂移区DFT的源极区域SC侧的端部DFTS更靠源极区域SC侧。
并且，p型杂质区域PH位于隔离槽TNC的源极区域SC侧的端部TNCS到自隔离槽TNC的源极区域SC侧的端部TNCS位移隔离槽TNC的长度Ld的1/3的距离的位置的范围内。
具体而言，p型杂质区域PH的漏极区域DC侧的端部PHD与隔离槽TNC的源极区域SC侧的端部TNCS之间的上述源极-漏极方向上的尺寸为上述隔离槽TNC的长度Ld的1/3以下。
并且，p型杂质区域PH的源极区域SC侧的端部PHS与隔离槽TNC的源极区域SC侧的端部TNCS之间的上述源极-漏极方向上的尺寸为上述隔离槽TNC的长度Ld的1/3以下。
另外，本实施方式中的除了上述结构以外的结构与上述第1实施方式的结构基本相同，因此对相同的要件标注相同的符号，并不再进行重复说明。
接下来，参照图25对本实施方式的半导体器件的制造方法进行说明。
在本实施方式的制造方法中，首先进行与图8～图10所示的第1实施方式的工序相同的工序。接着，在本实施方式中，如图25所示，经由绝缘膜BI的贯穿孔TH将n型杂质及p型杂质注入半导体基板SUB。由此，在半导体基板SUB形成n型杂质区域NH及p型杂质区域PH。
用于形成p型杂质区域PH的p型杂质的离子注入条件例如为：注入能量为几十keV，剂量为1011～1012cm-2。为了防止注入离子的撞击，优选在用于形成n型杂质区域NH的n型杂质的离子注入之前进行所述p型杂质的离子注入。
接着，在本实施方式的制造方法中，进行与图12～图15所示的第1实施方式的工序相同的工序。由此，制造出图24所示的本实施方式的半导体器件。
接下来，对本实施方式的作用效果进行说明。
本发明人对本实施方式中的导通电阻Rsp与门极电流Ig之间的关系以及关态击穿电压BVoff与门极电流Ig之间的关系进行了调查。其结果在图26和图27中示出。
图26中示出本实施方式、第1实施方式及比较例中的导通电阻Rsp与门极电流Ig之间的关系。并且，图27中示出了本实施方式、第1实施方式及比较例中的关态击穿电压BVoff与门极电流Ig之间的关系。根据图26及图27的结果可知，与比较例相比，在本实施方式中能够降低门极电流Ig，并且与第1实施方式相比，在本实施方式中能够进一步降低导通电阻Rsp。
如上所述，根据本实施方式，由于在凹部HL的正下方追加了p型杂质区域PH，因而能够降低门极电流Ig，并且能够进一步降低导通电阻Rsp。
并且，若p型杂质区域PH的浓度峰值高于n型杂质区域NH的浓度峰值，则由n型杂质区域NH带来的电场缓和效果可能会被p型杂质区域PH抵消。
在本实施方式中，p型杂质区域PH的浓度峰值低于n型杂质区域NH的浓度峰值。由此，抑制了由n型杂质区域NH带来的电场缓和效果被p型杂质区域PH抵消。
并且，p型杂质区域PH的漏极区域DC侧的端部PHD位于比从凹部HL朝向漏极区域DC侧位移尺寸H(从凹部HL的底部到隔离槽TNC的底部为止的深度方向上的尺寸)的位置更靠源极区域SC侧。由此，能够抑制热载流子注入到门电极GE，并且还能够得到上述RESURF效果。
(第3实施方式)
如图28所示，本实施方式的半导体器件的结构与第1实施方式的半导体器件的结构的不同之处在于，凹部HL具有多个凹部分HLP且n型杂质区域NH具有多个n型区域部分(第一区域部分)NHP。
在俯视时，多个凹部分HLP配置成彼此隔着间隔而并排延伸。即，在俯视时，多个凹部分HLP形成为所谓的长条状。多个凹部分HLP各自的宽度WA大于多个凹部分HLP中彼此相邻的凹部分HLP之间的距离WB。
并且，多个n型区域部分NHP彼此隔着间隔而配置。多个n型区域部分NHP分别配置在各个凹部分HLP的正下方区域。
本实施方式中的除了上述结构之外的结构与第1实施方式的结构基本相同，因此对相同的要件标注相同的符号，并不再进行重复说明。
接下来，参照图29～图33对本实施方式的半导体器件的制造方法进行说明。另外，图29～图33中只示出了两个凹部分HLP及两个n型区域部分，但是如图28所示，也可以设置有三个凹部分HLP及三个n型区域部分。
在本实施方式的制造方法中，首先进行与图8及图9所示的第1实施方式的工序相同的工序。接着，在本实施方式中，如图29所示，利用通常的照相制版技术形成光致抗蚀剂图案PR2。该光致抗蚀剂图案PR2具有使绝缘膜BI的一部分表面暴露的开口。将该光致抗蚀剂图案PR2作为掩模对绝缘膜BI进行蚀刻。该蚀刻之后，例如通过灰化等去除光致抗蚀剂图案PR2。
如图30所示，通过上述蚀刻，在绝缘膜BI上形成有贯穿绝缘膜BI而到达p型漂移区DFT的多个贯穿孔部THP。经由该多个贯穿孔部THP将n型杂质注入半导体基板SUB。n型杂质的离子注入的条件例如为：注入能量为几百keV～几MeV，剂量为1012～1013cm-2。通过注入该n型杂质，在各个贯穿孔部THP的正下方区域且在p型漂移区DFT的下侧形成多个n型区域部分NHP。由多个n型区域部分NHP构成n型杂质区域NH。
如图31所示，以覆盖多个贯穿孔部THP的内壁面且覆盖硬掩模层HM及绝缘膜BI的上表面的方式形成例如由氧化硅膜形成的绝缘膜IL。绝缘膜IL形成为例如贯穿孔部THP的深度的约1/3左右的膜厚。由覆盖贯穿孔部THP的内壁面的绝缘膜IL的外表面构成凹部分HLP的内壁面。
接着，以填埋多个凹部分HLP内且覆盖绝缘膜IL的上表面的方式形成由掺杂多晶硅形成的导电膜GE2。导电膜GE2形成为例如几百nm的膜厚。接着，例如利用CMP对导电膜GE2进行研磨直至绝缘膜IL的表面露出。
如图32所示，通过上述CMP，导电膜GE2仅残留在多个凹部分HLP的内部。接着，例如通过蚀刻去除绝缘膜IL的一部分及硬掩模层HM。
如图33所示，通过上述蚀刻，暴露出导电膜GE1的表面。并且，通过上述蚀刻，绝缘膜IL仅残留在贯穿孔TH内。由该残留在贯穿孔TH内的绝缘膜IL及绝缘膜BI构成隔离绝缘膜SIS。
在半导体基板SUB的主表面MS的整个表面之上形成例如由掺杂多晶硅形成的导电膜GE3。导电膜GE3形成为例如几十nm的膜厚。接着，利用通常的照相制版技术及蚀刻技术对导电膜GE3、GE1进行图案化。由此，形成由导电膜GE1、GE2及GE3构成的门电极GE。
接着，在本实施方式的制造方法中，进行与图15所示的第1实施方式的工序相同的工序。由此，制造出与图28所示的本实施方式的半导体器件。
接下来，通过对比图34～图35所示的比较例，对本实施方式的作用效果进行说明。
在比较例中，如图34所示，形成有一个宽度较宽的凹部HL。此时，若形成导电膜GE2，并且如图35所示对导电膜GE2进行蚀刻，则导电膜GE2无法填埋凹部HL。此时，导电膜GE2以侧壁形状仅残留在凹部HL的侧壁上。
相对于此，在本实施方式中，如图28所示，凹部HL具有多个凹部分HLP。因此，能够减小一个凹部分HLP的宽度WA的同时能够将多个凹部分HLP的整体宽度(例如3×WA+2×WB)确保为较大。
因此，能够抑制热载流子注入到门电极GE，并且能够用导电膜GE2填埋各个凹部分HLP。
并且，与第1实施方式相比，本实施方式的制造方法无需追加光掩模即可形成多个凹部分HLP。
并且，若凹部HL的宽度Lt(参考图4)变大，则电场变得缓和会导致使用寿命(ΔTTF)变长(参考下述论文)。因此，从延长使用寿命的观点出发，凹部HL的宽度优选较大。
论文：H.Fujii et al.,“A Recessed Gate LDMOSFET for Alleviating HCIEffects”,Proceedings of the 2016 28th ISPSD,June 12-16,2016,Prague,CzechRepublic,pp.167-170
对此，在本实施方式中，多个凹部分HLP各自的宽度WA设定为大于多个凹部分HLP中彼此相邻的凹部分HLP之间的距离WB。由此，能够将多个凹部HLP的宽度WA的总和确保为尽可能大，从而延长使用寿命。
另外，如图36所示，也可以在第3实施方式的结构中追加p型杂质区域PH。p型杂质区域PH具有多个p型区域部分PHP。多个p型区域部分PHP分别配置在各个凹部分HLP的正下方区域。
在该变形例中，取代图30所示的第3实施方式的制造工序而如图37所示注入n型杂质的同时还注入p型杂质从而制造出半导体器件。上述变形例中的除此之外的制造方法与第3实施方式的制造方法基本相同，因此不再进行重复说明。
在该变形例中，通过追加具有多个p型区域部分PHP的p型杂质区域PH，能够获得与第2实施方式相同的作用效果。
另外，在第1实施方式～第3实施方式中对pLDMOS晶体管进行了说明，但本发明也可以适用于如图38所示的nLDMOS晶体管。此时也能够获得与上述相同的作用效果。
并且，以上对pLDMOS晶体管及nLDMOS晶体管进行了说明。但是，本发明也同样可以适用于pLDMIS(Laterally Diffused Metal Insulator Semiconductor，横向扩散金属绝缘体半导体)晶体管或nLDMIS晶体管等门极绝缘膜GI由除了氧化硅膜以外的材质形成的晶体管。
以上，根据实施方式对本发明进行了具体说明，但是本发明并不只限于上述实施方式，在不脱离本发明宗旨的范围内可进行各种变化。

Claims (11)

1.一种半导体器件，其特征在于，具备：
半导体基板，其具有主表面，且在所述主表面具有隔离槽；
第一导电型的源极区域，其配置在所述半导体基板的所述主表面上；
第一导电型的漏极区域，其配置在所述主表面上，并且在所述第一导电型的漏极区域与所述源极区域之间夹着所述隔离槽；
第一导电型的漂移区，其位于所述隔离槽的下侧并且与所述漏极区域连接；
隔离绝缘膜，其填埋所述隔离槽的内部，并且在所述隔离绝缘膜的上表面具有凹部；
门电极，其以与夹在所述源极区域和所述漂移区之间的所述主表面绝缘的方式与该主表面对置，并且所述门电极填埋所述凹部的内部；
第二导电型的第一杂质区域，其具有位于所述漂移区的下侧且位于所述凹部的正下方的部分，
所述第一杂质区域仅位于所述凹部的正下方。
2.根据权利要求1所述的半导体器件，其特征在于，
将从所述源极区域朝向所述漏极区域的方向上的所述隔离槽的长度设为Ld，
所述第一杂质区域位于所述隔离槽的所述源极区域侧的端部到自所述隔离槽的所述源极区域侧的端部位移所述长度Ld的1/3的距离的位置的范围内。
3.根据权利要求1所述的半导体器件，其特征在于，
所述第一杂质区域的所述漏极区域侧的端部位于比从所述凹部朝向所述漏极区域侧位移相当于从所述凹部的底部到所述隔离槽的底部为止的深度方向上的尺寸的距离的位置更靠所述源极区域侧。
4.根据权利要求1所述的半导体器件，其特征在于，还具备：
第二导电型的第一阱区，其位于所述漂移区的下侧；
第二导电型的第二阱区，其位于所述源极区域与所述漂移区之间的主表面，
其中，所述第一阱区的杂质浓度低于所述第二阱区的杂质浓度。
5.根据权利要求1所述的半导体器件，其特征在于，还具备：
第一导电型的第二杂质区域，其位于所述漂移区内且所述凹部的正下方。
6.根据权利要求5所述的半导体器件，其特征在于，
所述第二杂质区域的浓度峰值低于所述第一杂质区域的浓度峰值。
7.根据权利要求5所述的半导体器件，其特征在于，
所述第二杂质区域的所述漏极区域侧的端部位于比从所述凹部朝向所述漏极区域侧位移相当于从所述凹部的底部到所述隔离槽的底部为止的深度方向上的尺寸的距离的位置更靠所述源极区域侧。
8.根据权利要求5所述的半导体器件，其特征在于，
所述凹部具有多个凹部分，
所述第二杂质区域具有多个第二区域部分，所述多个第二区域部分分别位于各个凹部分的正下方区域。
9.根据权利要求1所述的半导体器件，其特征在于，
所述凹部具有多个凹部分，
所述第一杂质区域具有多个第一区域部分，所述多个第一区域部分分别位于各个凹部分的正下方区域。
10.根据权利要求9所述的半导体器件，其特征在于，
所述多个凹部分各自的宽度大于所述多个凹部分中彼此相邻的凹部分之间的距离。
11.一种半导体器件的制造方法，其特征在于，具备如下工序：
形成半导体基板的工序，所述半导体基板具有主表面、隔离槽，其位于所述主表面、第一导电型的源极区域，其位于所述主表面、第一导电型的漏极区域，其位于所述主表面且在所述漏极区域与所述源极区域之间夹着所述隔离槽、第一导电型的漂移区，其位于所述隔离槽的下侧且与所述漏极区域连接；
形成隔离绝缘膜的工序，所述隔离绝缘膜填埋所述隔离槽的内部，并且在所述隔离绝缘膜的上表面具有凹部；
形成第二导电型的第一杂质区域的工序，所述第二导电型的第一杂质区域位于所述漂移区的下侧且所述凹部的正下方；及
形成门电极的工序，所述门电极在夹在所述源极区域与所述漂移区之间的所述主表面之上夹着门极绝缘膜与该主表面对置，并且所述门电极填埋所述凹部的内部，
形成在所述上表面具有所述凹部的所述隔离绝缘膜的工序具有如下工序：
形成填埋所述隔离槽的内部的埋入绝缘膜的工序；
形成贯穿所述埋入绝缘膜的贯穿孔的工序；
形成覆盖所述贯穿孔的内壁的包覆绝缘膜的工序，
形成所述第一杂质区域的工序具有如下工序：
经过所述贯穿孔将所述第二导电型的杂质导入到所述半导体基板的工序。
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