CN108233884A - A kind of adjustable signal and programmable gain amplifier circuit and its control method - Google Patents
A kind of adjustable signal and programmable gain amplifier circuit and its control method Download PDFInfo
- Publication number
- CN108233884A CN108233884A CN201711316106.2A CN201711316106A CN108233884A CN 108233884 A CN108233884 A CN 108233884A CN 201711316106 A CN201711316106 A CN 201711316106A CN 108233884 A CN108233884 A CN 108233884A
- Authority
- CN
- China
- Prior art keywords
- switch
- vout
- output terminal
- voltage value
- capacitance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 11
- 238000005070 sampling Methods 0.000 claims abstract description 33
- 101100102627 Oscarella pearsei VIN1 gene Proteins 0.000 claims description 12
- 230000005611 electricity Effects 0.000 claims description 8
- 230000009286 beneficial effect Effects 0.000 claims description 2
- 230000003321 amplification Effects 0.000 abstract description 13
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 13
- 230000003750 conditioning effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 8
- 230000009711 regulatory function Effects 0.000 description 7
- 230000007423 decrease Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000006698 induction Effects 0.000 description 3
- 230000035807 sensation Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 238000012935 Averaging Methods 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 108010076504 Protein Sorting Signals Proteins 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
- H03G1/0029—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier using FETs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/001—Digital control of analog signals
Landscapes
- Amplifiers (AREA)
Abstract
The invention discloses a kind of adjustable signal and programmable gain amplifier circuit and its control methods, the circuit includes operational amplifier, input, output end, sampling capacitance, feedback capacity, first switch, second switch and third switch, wherein, one end of feedback capacity is connect with sampling capacitance, the other end is connect with one end that second switch, third switch, the other end connection output terminal of second switch, the other end connection reference voltage of third switch；One end connection sampling capacitance of first switch, other end connection output terminal；The reverse input end connection sampling capacitance of operational amplifier, positive input connection common-mode voltage, other end connection output terminal.The present invention can simplify circuit design, reduce Design of Amplifiers difficulty, save the power consumption brought by reference voltage and area, by changing sampled point, the present invention can eliminate the offset voltage of operational amplifier, realize high-precision amplification function.
Description
Technical field
The present invention relates to technical field of integrated circuits, and in particular to a kind of adjustable signal and programmable gain amplifier
Circuit and its control method.
Background technology
Programmable gain amplifier circuit abbreviation PGA, be it is a kind of by input analog voltage signal amplify setting multiple after it is defeated
The analog amplifier circuit gone out, amplification factor are determined by sampling capacitance and feedback capacity ratio.It is realized by switching capacity mode
PGA circuits be fully compatible with the CMOS technology technology of present standard, thus be widely used in present standard CMOS chip
In, for amplified analog voltage signal.
Fig. 1 is a typical PGA circuit application scheme, and analog voltage signal amplifies the multiple of setting after PGA circuits
Afterwards, it exports and gives Analog-digital Converter (ADC) circuit, exported after adc circuit is converted into digital signal and give Digital Signal Processing mould
Block (DSP), carries out a series of Digital Signal Processing.One is cmos image sensor chip than more typical example, by picture
The optical signal received is converted into analog voltage signal by first photosensitive unit Pixel, is exported to PGA, to ADC after PGA amplifies
Output is achieved in image sensing to DSP processing outputs to chip exterior after being converted into digital signal.
Since the analog input signal of the PGA adc circuits subsequently connect generally has amplitude limitation, i.e. ADC simulation inputs are believed
Number less than its input signal amplitude minimum or during beyond input signal amplitude peak, adc circuit cannot be correctly converted into
Corresponding digital code.And in some present chip systems, in cmos image sensor system, the input simulation of PGA
In voltage signal, the i.e. output voltage signal of pixel unit pixel in addition to comprising required light sensation induction signal, also contain dark current
Caused useless signal, the Signal averaging export to ADC after PGA amplifies in normal light sensation induction signal, can account for one
Partial ADC input signal amplitudes so that the normal photoinduction range of signal that ADC can be converted becomes smaller.Such as ADC's is defeated
Enter signal amplitude for 1V, and garbage signal amplitude peak caused by dark current is 0.1V, then ADC can be converted out normal
Light sensation induction signal amplitude peak is 1V-0.1V=0.9V.The peak signal width that chip system can sense just is resulted in this way
Degree becomes smaller, and chip system dynamic range is caused to reduce accordingly.In order to solve this problem, a kind of way is at PGA
Signal conditioning functions are added in, i.e., are subtracted the garbage signal of the 0.1V included in input signal at PGA, the PGA inputs made are
0~1V is exported during 0.1V~1.1V, the input reference signal of such ADC is not wasted on garbage signal, is improved entire
The dynamic range of system.The PGA circuits of band signal regulatory function have practical application demand as a result,.
However, since the chips such as present sensor are widely used in portable mobile apparatus, thus the area of chip
Become the critically important performance indicator of chip with power consumption, be largely affected by the competitiveness of chip.Foregoing PGA circuits
It applies in this kind of chip, needs to consider its area and power consumption, particularly now widely used switching capacity PGA, capacitance
The area considerable using chip can be accounted for, while considerable electric current is also required to drive used capacitance.Before so
The PGA circuits for the band signal regulatory function mentioned are expected to not save valuable area and power consumption using excessive capacitance.
Fig. 2 show a kind of traditional PGA circuit structures that can only be realized input signal and amplify by setting multiple, signal
Amplification factor is Cs '/Cf ', Cs or Cf capacitances can make tunable capacitor to realize the function of gain-variable in practice, not have herein
It indicates.Feedback factor β=Cf ' of the PGA circuit loops/(Cs '+Cf '), wherein, Cs ' be the corresponding capacitances of capacitance Cs, Cf '
For the corresponding capacitances of capacitance Cf.
Fig. 3 is a kind of PGA circuit structures of traditional band signal regulatory function, by increasing capacitance Cos and two ginsengs
Voltage signal Vos1, Vos2 are examined, coordinates the switching signal sequential of response, to realize the amplification of input signal and adjusting, wherein S1
It is complementary signal with S1B.For its work schedule as shown in figure 4, SW, S1 are height, respective switch conducting, PGA is in reset state,
Output terminal VOUT output valves are VCM ', and V2 points voltage is Vos1 ', and input terminal VIN voltage is VIN1 ', and then SW becomes low from height,
Subsequent S1 becomes low from height, i.e. S1B is increased by low, and V2 point voltage values become Vos2 ' from Vos1 ', input terminal VIN voltage by
VIN1 ' becomes VIN2 ', and the voltage value of output terminal VOUT becomes VCM '+Δ VIN '+Δ Vos ' from VCM ', and wherein Δ VIN '=
(VIN2 '-VIN1 ') * Cs '/Cf ', Δ Vos '=(Vos2 '-Vos1 ') * Cos '/Cf '.The PGA loop feedbacks coefficient for β=
Cf’/(Cs’+Cf’+Cos’)。
Circuit shown in Fig. 3 can realize signal amplification and regulatory function, but it has the shortcomings that several apparent：1st, it is more traditional
PGA increases a capacitance Cos, increases area；2nd, two reference voltages Vos1, Vos2 have been increased newly, have increased answering for circuit
Miscellaneous degree, while two noise sources of Vos1, Vos2 have also been introduced；3rd, PGA loop feedbacks factor beta=Cf '/(Cs '+Cf '+Cos ')
β=Cf '/(Cs '+Cf ') less than traditional PGA, the reduction of feedback factor cause the design difficulty of operational amplifier to increase, power consumption
Increase.
Invention content
In order to overcome the above problem, the technical problems to be solved by the invention is provide a kind of adjustable signal and may be programmed
Gain amplifier circuit and its control method, can simplify circuit design, reduce Design of Amplifiers difficulty, save by
The power consumption and area that reference voltage is brought.
To achieve these goals, the present invention adopts the following technical scheme that：A kind of adjustable signal and programmable gain
Amplifier circuit, including：Operational amplifier (OTA), input terminal (VIN), output terminal (VOUT), sampling capacitance (Cs), feedback electricity
Hold (Cf), first switch (S1), second switch (S2) and third switch (S1D), wherein, one end of feedback capacity (Cf) and sampling
Capacitance (Cs) connects, and one end that the other end and second switch (S2), third switch (S1D) is connect, second switch (S2) it is another
End connection output terminal (VOUT), the other end connection reference voltage (Vos) of third switch (S1D)；One end of first switch (S1)
Connect sampling capacitance (Cs), other end connection output terminal (VOUT)；The reverse input end connection sampling of operational amplifier (OTA)
Capacitance (Cs), positive input connection common-mode voltage (VCM), other end connection output terminal (VOUT).
Further, the operational amplifier (OTA) is using five pipe operational amplifiers.
Further, the circuit structure of the operational amplifier specifically includes：First NMOS tube, the 2nd NMOS are closed, third
PMOS tube, the 4th PMOS tube and tail current NMOS tube；Wherein, the source electrode of the 4th PMOS tube and the source electrode of third PMOS tube connect
Power supply；The grid of 4th PMOS tube and the grid of third PMOS tube be connected and jointly with the drain electrode of third PMOS tube and the first NMOS
The drain electrode of pipe is connected；The drain electrode of 4th PMOS tube is connected with the drain electrode of the 2nd NMOS pipes and is commonly connected to output terminal
(VOUT)；The source electrode of second NMOS tube and the source electrode of the first NMOS tube are connected and are commonly connected to the leakage of tail current NMOS tube
Pole；The grid of second NMOS tube connects reverse input end (VN)；The grid of first NMOS tube connects common-mode voltage (VCM), tail current
The grid connection bias voltage (VB) of NMOS tube, the source electrode ground connection of tail current NMOS tube.
Further, the first NMOS tube, the 2nd NMOS passes, the 3rd PMOS pipes, the 4th in the circuit of the operational amplifier
The source electrode and drain electrode of PMOS tube and tail current NMOS tube can be interchanged.
Further, feedback factor β=Cf ' in gain amplifier circuit/(Cs '+Cf '), wherein, Cs ' is sampling electricity
The capacitance of appearance, Cf ' are the capacitance of feedback capacity.
Further, the second switch (S2) and third switch (S1D) are realized by one-way conduction transistor.
Further, the second switch (S2) and third switch (S1D) are single knife switch.
The control method of a kind of adjustable signal provided by the invention and programmable gain amplifier circuit, including following
Step：
S01：First switch (S1) and third switch (S1D) are in the conduction state, and second switch (S2) disconnects, at this point, defeated
Outlet (VOUT) voltage value is operational amplifier reverse input end voltage VN ', and voltage value is VIN1 ' to input terminal (VIN) at this time, the
Two switches (S2) and the voltage value of third switch (S1D) junction are Vos '；
S02：First opens the disconnection in succession of (S1) and third switch (S1D), and then second switch (S2) is connected, at this time output terminal
(VOUT) voltage value is Vos '；
S03：Input terminal (VIN) voltage value becomes VIN2 ' from VIN1 ', and output terminal (VOUT) voltage value is Δ VIN ' at this time
The sum of with Vos ', wherein, Δ VIN '=(VIN2 '-VIN1 ') * Cs '/Cf ', Cs ' is the capacitance of sampling capacitance, and Cf ' is feedback
The capacitance of capacitance；
S04：Output terminal (VOUT) voltage value in output terminal (VOUT) voltage value and step S01 in step S03 is asked
Difference, i.e.,：Δ VOUT '=Δ VIN '+Vos '-VN ', wherein, Vos '-VN ' is the adjustment item to output signal.
The control method of a kind of adjustable signal provided by the invention and programmable gain amplifier circuit, including following
Step：
S01：First switch (S1) and third switch (S1D) are in the conduction state, and second switch (S2) disconnects, at this point, defeated
Outlet (VOUT) voltage value is operational amplifier reverse input end voltage VN ', and voltage value is VIN1 ' to input terminal (VIN) at this time, the
Two switches (S2) and the voltage value of third switch (S1D) junction are Vos '；
S02：First opens extension and the disconnection in succession of third switch, and then second switch is connected, at this time output terminal (VOUT) voltage
It is worth for Vos '；
S03：Input terminal (VIN) voltage value becomes VIN2 ' from VIN1 ', and output terminal (VOUT) voltage value is Δ VIN ' at this time
The sum of with Vos ', wherein, Δ VIN '=(VIN2 '-VIN1 ') * Cs '/Cf ', Cs ' is the capacitance of sampling capacitance, and Cf ' is feedback
The capacitance of capacitance；
S04：Output terminal (VOUT) voltage value in output terminal (VOUT) voltage value and step S02 in step S03 is asked
Difference, i.e.,：Δ VOUT '=Δ VIN '.
Beneficial effects of the present invention are：The use of the capacitance of reduction, saves area；Reduce reference voltage quantity, letter
Change circuit design, while reduce area, power consumption and noise；The feedback factor of PGA loops is increased, alleviates operational amplifier
Design difficulty, while reduce power consumption；By timing Design, it can be configured to the PGA of only enlarging function, but PGA can be eliminated
Imbalance, be advantageously implemented high-precision, function is more flexible.
Description of the drawings
Fig. 1 is the typical PGA circuit diagrams of a tradition.
Fig. 2 is a kind of traditional PGA circuit diagrams that can only be realized input signal and amplify by setting multiple.
Fig. 3 is a kind of achievable signal amplification of tradition and the PGA circuit diagrams adjusted.
Fig. 4 is the switching sequence schematic diagram of the normal work of PGA circuits shown in Fig. 3.
Fig. 5 is the PGA circuit diagrams of the preferred embodiment of the present invention.
Switching signal time diagram when Fig. 6 is the PGA circuits normal work of the preferred embodiment of the present invention.
Fig. 7 is the PGA circuit diagrams of the preferred embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with the accompanying drawings to the specific reality of the present invention
The mode of applying is described in further detail.
In the present embodiment, signal and programmable gain amplifier circuit is adjusted, using PGA circuits, is put including operation
Big device, input, output end, sampling capacitance, feedback capacity, first switch, second switch and third switch, wherein, feedback electricity
One section held is connect with sampling capacitance, and the other end is connect with one end that second switch, third switch, and the other end of second switch connects
Connect output terminal, the other end connection reference voltage of third switch；One end connection sampling capacitance of first switch, other end connection are defeated
Outlet.Three switches can also connect respective switching sequence device, the signal that switching sequence device control output end is exported according to
The value of setting rises or falls.
As shown in Figure 5, a kind of adjustable signal provided by the invention and programmable gain amplifier circuit, it is specific to wrap
It includes operational amplifier OTA, input terminal VIN, output terminal VOUT, sampling capacitance Cs, feedback capacity Cf, first switch S1, second open
S2 and third switch S1D are closed, wherein, one section of feedback capacity Cf is connect with sampling capacitance Cs, the other end and second switch S2, the
One end connection of three switch S1D, the other end connection output terminal VOUT of second switch S2, the other end connection of third switch S1D
Reference voltage Vos；One end connection sampling capacitance Cs of first switch S1, other end connection output terminal VOUT；Operational amplifier OTA
Reverse input end connection sampling capacitance Cs, positive input connection common-mode voltage VCM, other end connection output terminal VOUT.This
Invention is to disconnect the feedback capacity in traditional PGA and operational amplifier output connecting pin, inserts second switch S2 and third
S1D is switched, wherein, right side pole plate V2 nodes and the operational amplifier output terminal VOUT of second switch S2 connection feedback capacities Cf,
The right side pole plate V2 nodes and newly-increased voltage end Vos of third switch S1D connection feedback capacities Cf.Capacitance Cs is traditional PGA
Sampling capacitance, be connected between the reverse input end VN nodes of signal output end VIN and OTA.First switch S1 is is connected across fortune
Calculate the output terminal and reverse input end of amplifier OTA.The S1D control signals of third switch control signal slightly for first switch S1
It is delayed and obtains, and earlier than the rise time of second switch S2 control signals.The common-mode voltage VCM of operational amplifier, to circuit
Suitable operating point is provided.
Circuit structure shown in comparison diagram 3 and Fig. 5 can see, compared to the PGA of traditional band signal regulatory function, this hair
The structure of bright proposition eliminates capacitance Cos, reduces total circuit area.Due to merely adding a reference voltage Vos, compare
In two reference voltages Vos1, Vos2 that the PGA of conventional belt signal conditioning functions is increased newly, structure proposed by the present invention simplifies electricity
Road is designed, and saves the power consumption brought by reference voltage and area, decreases the noise of a reference voltage contribution.In addition,
Structure loop feedback factor proposed by the present invention is β=Cf '/(Cs '+Cf '), more than the PGA of conventional belt signal conditioning functions
Feedback factor β=Cf '/(Cs '+Cf '+Cos ').Thus it can reduce Design of Amplifiers difficulty, so as to further save work(
Consumption and area.
Referring to Fig. 7, operational amplifier uses five pipe operational amplifiers in the present invention, five pipe amplifiers specifically include：The
One NMOS tube M1, the 2nd NMOS close M2, third PMOS tube M3, the 4th PMOS tube M4, tail current NMOS pipes M0；Wherein, the 4th
The source electrode of PMOS tube M4 and the source electrode of third PMOS tube M3 connect power supply；The grid of 4th PMOS pipes M4 and third PMOS tube M3
Grid be connected and be connected jointly with the drain electrode and the drain electrode of the first NMOS tube M1 of third PMOS tube M3；4th PMOS tube M4
Drain electrode be connected with the drain electrode of the second NMOS tube M2 and be commonly connected to output terminal VOUT；The source electrode and first of second NMOS tube M2
The source electrode of NMOS tube M1 is connected and is commonly connected to the drain electrode of tail current NMOS tube M0；The grid of second NMOS tube M2 it is reversed to
Input terminal VN；The grid of first NMOS tube M1 meets common-mode voltage VCM, the grid connection bias voltage VB of tail current NMOS tube M0,
The source electrode ground connection of tail current NMOS tube M0.I.e.：Added bias voltage VB is converted into electric current so that M1 by tail current NMOS tube M0
~M4 pipes are operated in saturation region, M1 pipes and M2 pipes and are inputted for the NMOS operational amplifiers realized to pipe, and M1 pipe grid ends are put for operation
Big device positive input connects VCM voltages, and M2 pipes grid end is operational amplifier reverse input end, connects VN nodes, and M3 pipes and M4 pipes are
The active electric current mirror load that PMOS is realized, M3 pipes grid end and drain terminal short circuit, M4 pipes grid end and M3 pipe grid end short circuits, M4 pipe drain terminals
With M2 pipe drain terminal short circuits, become operational amplifier output terminal, wherein, the first NMOS tube M1, the 2nd NMOS close M2, third PMOS tube
Source electrode and drain electrode in M3, the 4th PMOS tube M4, tail current NMOS tube M0 can be interchanged.
Referring to Fig. 6, for the corresponding sequential control method of circuit of the present invention, wherein, the corresponding output terminal VOUT of VOUT '
Voltage value, the voltage value of the corresponding input terminal VIN of VIN ', the voltage value of the corresponding second switches of V2 ' and third switch junction.The
The time that three switch S1D signals are begun to decline is more late than the time that first switch S1 signals are begun to decline, to realize feedback capacity Cf
Bottomplanksampling.The time that second switch S2 is begun to ramp up is more late than the time that third switch S1D is begun to decline, input terminal VOUT
Time for beginning to ramp up of signal of the signal changed time than second switch S2 it is late.It is right in PGA course of normal operation
It should become high in t0 moment, first switch S1 control signals and third switch S1D control signals, PGA is in reset state, VOUT
End output is VN ', does not consider the non-ideal factor of OTA, and size is equal to VCM ', and it is low electricity that second switch S2, which controls signal, at this time
Flat, corresponding second switch S2 is disconnected, and V2 points voltage is Vos ', and voltage is set as VIN1 ' to input signal VIN at this time.PGA resets terminate
When, corresponding to the t1 moment, first switch S1 control signals become low from height, then correspond to t2 moment, third switch S1D controls
Signal also becomes low from height, then correspondes to the t3 moment, second switch S2 controls signal to become high from low, by V2 nodes and PGA
Output terminal VOUT is connected, and output terminal VOUT output voltages size is Vos ' at this time, then correspondes to t5 moment, input terminal
VIN voltage starts to become VIN2 ' from VIN1 ', until the t6 moment becomes VIN2 ', VN nodes are due to the short spy of void of operational amplifier
Property be maintained as VCM ', V2 nodes due to second switch S2 is connected and with the feedback capacity of output terminal VOUT short circuits, at this time PGA
Size is Cf ', and by charge after sampling capacitance Cs is transferred to feedback capacity Cf, voltage will be after PGA output terminals VOUT stablizes
VCM '+Δ VIN '+Δ Vos ', wherein Δ VIN '=(VIN2 '-VIN1 ') * Cs '/Cf ' are that gain amplifier circuit believes input
The output item that obtains after number amplification, amplification factor are determined that Δ Vos ' is by sampling capacitance Cs and the capacitance ratio of feedback capacity Cf
To the adjustment item of output signal, size is determined by reference voltage Vos ' and common-mode voltage VCM '.
Specifically, if the double sampling point design of subsequent conditioning circuit is the t0 and t7 in Fig. 6, subsequent conditioning circuit double sampling obtains
The difference of the signal arrived is Δ VOUT '=Δ VIN '+Vos '-VN '=(VIN2 '-VIN1 ') * Cs '/Cf '+Vos '-VN ', by
This, PGA completes input signal amplification and Signal Regulation process, and amplification factor Cs '/Cf ' is identical with traditional PGA, signal tune
Section size is Vos '-VN ', does not consider the non-ideal factor of OTA, and VN ' sizes are equal to VCM '.By setting the value of Vos '-VN ',
It can be on the basis of PGA realizes normal amplification plus or minus a value, signal sequence proposed by the invention are conveniently carried
The programmable gain amplifier circuit structure of the band signal regulatory function gone out, can while signal amplification is realized with regulatory function
The adverse effect brought to avoid some non-ideal factors to circuit performance.
If the double sampling point design of subsequent conditioning circuit is the t4 and t7 in Fig. 6, the letter that subsequent conditioning circuit double sampling obtains
Number difference for Δ VOUT '=Δ VIN '+Vos '-Vos '=(VIN2 '-VIN1 ') * Cs '/Cf ', circuit realizes normal PGA
Enlarging function, amplification factor Cs '/Cf '.Since in actual circuit, there are offset voltages by PGA, and VN node voltages is caused to differ
In VCM, so the absolute value of voltage of traditional PGA circuit outputs can change with offset voltage size variation, this is to more
It is typically can not be ignored the problem of under the higher application environment of a PGA output voltages coherence request.And if in the present invention
T4 and t7 instance samples in the sequential of proposition, then the output voltage of PGA is Vos ' and Δ VIN '+Vos ' always, two voltages
Absolute value do not change with the transformation of PGA offset voltages, when using multiple PGA have good consistency.
In addition, second switch S2 in Fig. 5 is constantly on, third switch S1D is disconnected always, then circuit configuration is passed into one
The programmable gain amplifier circuit of the cloth bag signal conditioning functions of system is fully equivalent to a traditional programmable automation controller
Device circuit can't bring any adverse effect.
The foregoing is merely the preferred embodiment of the present invention, the embodiment is not intended to limit the patent protection of the present invention
Range, therefore the equivalent structure variation that every specification and accompanying drawing content with the present invention is made, similarly should be included in this
In the protection domain of invention appended claims.
Claims (9)
1. a kind of adjustable signal and programmable gain amplifier circuit, which is characterized in that including：Operational amplifier (OTA),
Input terminal (VIN), output terminal (VOUT), sampling capacitance (Cs), feedback capacity (Cf), first switch (S1), second switch (S2)
(S1D) is switched with third, wherein, one end of feedback capacity (Cf) is connect with sampling capacitance (Cs), the other end and second switch
(S2), one end connection of third switch (S1D), the other end connection output terminal (VOUT) of second switch (S2), third switch
(S1D) other end connection reference voltage (Vos)；One end connection sampling capacitance (Cs) of first switch (S1), other end connection
Output terminal (VOUT)；The reverse input end connection sampling capacitance (Cs) of operational amplifier (OTA), positive input connection common mode electricity
It presses (VCM), other end connection output terminal (VOUT).
2. a kind of adjustable signal according to claim 1 and programmable gain amplifier circuit, which is characterized in that institute
Operational amplifier (OTA) is stated using five pipe operational amplifiers.
3. a kind of adjustable signal according to claim 1 or 2 and programmable gain amplifier circuit, feature exist
In the circuit structure of the operational amplifier specifically includes：First NMOS tube, the 2nd NMOS passes, third PMOS tube, the 4th PMOS
Pipe and tail current NMOS tube；Wherein, the source electrode of the 4th PMOS tube and the source electrode of third PMOS tube connect power supply；4th PMOS tube
Grid and the grid of third PMOS tube are connected and are connected jointly with the drain electrode of third PMOS tube and the drain electrode of the first NMOS tube；The
The drain electrode of four PMOS tube is connected with the drain electrode of the second NMOS tube and is commonly connected to output terminal (VOUT)；The source electrode of second NMOS tube
It is connected and is commonly connected to the drain electrode of tail current NMOS tube with the source electrode of the first NMOS tube；The grid of second NMOS tube it is reversed to
Input terminal (VN)；The grid of first NMOS tube connects common-mode voltage (VCM), the grid connection bias voltage of tail current NMOS tube
(VB), the source electrode ground connection of tail current NMOS tube.
4. a kind of adjustable signal according to claim 3 and programmable gain amplifier circuit, which is characterized in that institute
State the first NMOS tube in the circuit of operational amplifier, the 2nd NMOS passes, third PMOS tube, the 4th PMOS tube and tail current NMOS tube
Source electrode and drain electrode can be interchanged.
5. a kind of adjustable signal according to claim 1 and programmable gain amplifier circuit, which is characterized in that increase
Feedback factor β=Cf '/(Cs '+Cf ') in beneficial amplifier circuit, wherein, Cs ' is the capacitance of sampling capacitance, and Cf ' is feedback
The capacitance of capacitance.
6. a kind of adjustable signal according to claim 1 and programmable gain amplifier circuit, which is characterized in that institute
It states second switch (S2) and third switch (S1D) is realized by one-way conduction transistor.
7. a kind of adjustable signal according to claim 1 and programmable gain amplifier circuit, which is characterized in that institute
It is single knife switch to state second switch (S2) and third switch (S1D).
8. the control method of a kind of adjustable signal and programmable gain amplifier circuit, which is characterized in that including following step
Suddenly：
S01：First switch (S1) and third switch (S1D) are in the conduction state, and second switch (S2) disconnects, at this point, output terminal
(VOUT) voltage value is operational amplifier reverse input end voltage VN ', and voltage value is VIN1 ' to input terminal (VIN) at this time, and second opens
The voltage value for closing (S2) and third switch (S1D) junction is Vos '；
S02：First opens the disconnection in succession of (S1) and third switch (S1D), and then second switch (S2) is connected, at this time output terminal
(VOUT) voltage value is Vos '；
S03：Input terminal (VIN) voltage value becomes VIN2 ' from VIN1 ', at this time output terminal (VOUT) voltage value for Δ VIN ' with
The sum of Vos ', wherein, Δ VIN '=(VIN2 '-VIN1 ') * Cs '/Cf ', Cs ' is the capacitance of sampling capacitance, and Cf ' is feedback electricity
The capacitance of appearance；
S04：Poor is asked to output terminal (VOUT) voltage value in output terminal (VOUT) voltage value and step S01 in step S03,
I.e.：Δ VOUT '=Δ VIN '+Vos '-VN ', wherein, Vos '-VN ' is the adjustment item to output signal.
9. the control method of a kind of adjustable signal and programmable gain amplifier circuit, which is characterized in that including following step
Suddenly：
S01：First switch (S1) and third switch (S1D) are in the conduction state, and second switch (S2) disconnects, at this point, output terminal
(VOUT) voltage value is operational amplifier reverse input end voltage VN ', and voltage value is VIN1 ' to input terminal (VIN) at this time, and second opens
The voltage value for closing (S2) and third switch (S1D) junction is Vos '；
S02：First opens extension and the disconnection in succession of third switch, and then second switch is connected, and output terminal (VOUT) voltage value is at this time
Vos’；
S03：Input terminal (VIN) voltage value becomes VIN2 ' from VIN1 ', at this time output terminal (VOUT) voltage value for Δ VIN ' with
The sum of Vos ', wherein, Δ VIN '=(VIN2 '-VIN1 ') * Cs '/Cf ', Cs ' is the capacitance of sampling capacitance, and Cf ' is feedback electricity
The capacitance of appearance；
S04：Poor is asked to output terminal (VOUT) voltage value in output terminal (VOUT) voltage value and step S02 in step S03,
I.e.：Δ VOUT '=Δ VIN '.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711316106.2A CN108233884A (en) | 2017-12-12 | 2017-12-12 | A kind of adjustable signal and programmable gain amplifier circuit and its control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711316106.2A CN108233884A (en) | 2017-12-12 | 2017-12-12 | A kind of adjustable signal and programmable gain amplifier circuit and its control method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108233884A true CN108233884A (en) | 2018-06-29 |
Family
ID=62652029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711316106.2A Withdrawn CN108233884A (en) | 2017-12-12 | 2017-12-12 | A kind of adjustable signal and programmable gain amplifier circuit and its control method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108233884A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110120806A (en) * | 2019-06-24 | 2019-08-13 | 上海菲戈恩微电子科技有限公司 | A kind of switched-capacitor integrator offset voltage eliminates circuit and its removing method |
| CN111263090A (en) * | 2020-03-02 | 2020-06-09 | 上海集成电路研发中心有限公司 | Reading circuit structure and working time sequence control method thereof |
| CN111510090A (en) * | 2020-05-19 | 2020-08-07 | 成都微光集电科技有限公司 | Operational amplifier with high voltage slew rate and wide output range |
| CN114339093A (en) * | 2021-12-31 | 2022-04-12 | 重庆电子工程职业学院 | Programmable gain amplifier for image sensor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030201824A1 (en) * | 2002-04-16 | 2003-10-30 | M.C. Ramesh | Method and apparatus for exponential gain variations with a linearly varying input code |
| CN101132177A (en) * | 2006-08-24 | 2008-02-27 | 凌阳科技股份有限公司 | Programmable gain amplifier |
| CN101986559A (en) * | 2009-07-29 | 2011-03-16 | 比亚迪股份有限公司 | Analog signal processing circuit |
| CN106534729A (en) * | 2016-11-11 | 2017-03-22 | 中国电子科技集团公司第四十四研究所 | Programmable gain amplifier and method for reducing column fixed mode noise |
| CN106712730A (en) * | 2016-11-30 | 2017-05-24 | 上海集成电路研发中心有限公司 | Programmable gain amplifier capable of adjusting signals |
-
2017
- 2017-12-12 CN CN201711316106.2A patent/CN108233884A/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030201824A1 (en) * | 2002-04-16 | 2003-10-30 | M.C. Ramesh | Method and apparatus for exponential gain variations with a linearly varying input code |
| CN101132177A (en) * | 2006-08-24 | 2008-02-27 | 凌阳科技股份有限公司 | Programmable gain amplifier |
| CN101986559A (en) * | 2009-07-29 | 2011-03-16 | 比亚迪股份有限公司 | Analog signal processing circuit |
| CN106534729A (en) * | 2016-11-11 | 2017-03-22 | 中国电子科技集团公司第四十四研究所 | Programmable gain amplifier and method for reducing column fixed mode noise |
| CN106712730A (en) * | 2016-11-30 | 2017-05-24 | 上海集成电路研发中心有限公司 | Programmable gain amplifier capable of adjusting signals |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110120806A (en) * | 2019-06-24 | 2019-08-13 | 上海菲戈恩微电子科技有限公司 | A kind of switched-capacitor integrator offset voltage eliminates circuit and its removing method |
| CN111263090A (en) * | 2020-03-02 | 2020-06-09 | 上海集成电路研发中心有限公司 | Reading circuit structure and working time sequence control method thereof |
| CN111263090B (en) * | 2020-03-02 | 2022-02-22 | 上海集成电路研发中心有限公司 | Reading circuit structure and working time sequence control method thereof |
| CN111510090A (en) * | 2020-05-19 | 2020-08-07 | 成都微光集电科技有限公司 | Operational amplifier with high voltage slew rate and wide output range |
| CN111510090B (en) * | 2020-05-19 | 2023-03-31 | 成都微光集电科技有限公司 | Operational amplifier with high voltage slew rate and wide output range |
| CN114339093A (en) * | 2021-12-31 | 2022-04-12 | 重庆电子工程职业学院 | Programmable gain amplifier for image sensor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108233884A (en) | A kind of adjustable signal and programmable gain amplifier circuit and its control method | |
| CN106712730B (en) | Signal-adjustable programmable gain amplifier | |
| CN102195652B (en) | A sample-and-hold amplifier | |
| CN101917195B (en) | High-precision and low-offset charge comparator circuit | |
| TWI355797B (en) | Digitally programmable transconductance amplifier | |
| CN109587419B (en) | Low-power-consumption reading circuit structure of image sensor and working time sequence control method | |
| CN107888850A (en) | Ramp signal generator for double slanted A/D converter | |
| CN104168025B (en) | A kind of charge type streamline gradual approaching A/D converter | |
| CN103532501A (en) | Complementary switched capacitor amplifier for pipelined ADs and other applications | |
| US8610422B2 (en) | Dynamic biasing of an amplifier using capacitive driving of internal bias voltages | |
| CN101447790A (en) | Discrete-time programmable-gain analog-to-digital converter (adc) input circuit and method | |
| CN103518323B (en) | Auto-zero offset buffer amplifier and auto-zero offset correction method thereof | |
| Liu et al. | Design of single-stage folded-cascode gain boost amplifier for 14bit 12.5 Ms/S pipelined analog-to digital converter | |
| CN101986557A (en) | Method and structure for eliminating offset voltage of operational amplifier by using lining bias effect | |
| WO2020042436A1 (en) | Buffer circuit and buffer | |
| CN107276592A (en) | It is directly coupled to the system and method for the analog-digital converter referred to low voltage | |
| CN103107791B (en) | Gain linear variable gain amplifier with constant bandwidth | |
| US6097248A (en) | Switched capacitor amplifier with one-clock delay | |
| CN104135243B (en) | A kind of programmable gain amplifier | |
| CN103107789B (en) | The variable gain amplifier that a kind of common-mode feedback resistor shares | |
| CN108880548A (en) | Improved low-power switching type capacitor device integrator, A/D converter and switching type capacitor device amplifier | |
| CN206413094U (en) | A kind of row level adc circuit for cmos image sensor | |
| CN105391409A (en) | Low-ripple switched-capacitor common-mode feedback structure | |
| CN101277094B (en) | Operation amplifier capable of compensating migration voltage | |
| TW202008731A (en) | Analog-to-digital converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20180629 |
|
| WW01 | Invention patent application withdrawn after publication |