CN108233799A - A kind of circuit that d.c. motor output is controlled to stablize FG signals - Google Patents
A kind of circuit that d.c. motor output is controlled to stablize FG signals Download PDFInfo
- Publication number
- CN108233799A CN108233799A CN201810164851.8A CN201810164851A CN108233799A CN 108233799 A CN108233799 A CN 108233799A CN 201810164851 A CN201810164851 A CN 201810164851A CN 108233799 A CN108233799 A CN 108233799A
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- signal
- signals
- commutation
- output
- low level
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- 230000003111 delayed effect Effects 0.000 claims abstract description 6
- 230000005611 electricity Effects 0.000 claims description 4
- 230000000630 rising effect Effects 0.000 abstract description 4
- 230000002159 abnormal effect Effects 0.000 description 4
- 230000005284 excitation Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 206010044565 Tremor Diseases 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P7/00—Arrangements for regulating or controlling the speed or torque of electric DC motors
- H02P7/06—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current
- H02P7/18—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power
- H02P7/24—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices
- H02P7/28—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Control Of Motors That Do Not Use Commutators (AREA)
Abstract
The present invention provides a kind of circuit that d.c. motor output is controlled to stablize FG signals, including：One drive module, commutation signal when it is according to motor running exports corresponding drive signal, when commutation signal becomes low level from high level, drive signal synchronously becomes high level from low level, when commutation signal becomes high level from low level, drive signal is delayed relative to commutation signal after one section of predetermined delay time becomes low level from high level；And the output control module for being connected to drive module, corresponding FG signals are exported according to drive signal, when drive signal is low level, the FG signals of output are low level, and when drive signal is high level, the FG signals of output are high level.The present invention by the way that FG rising edges is controlled to have delay with respect to commutation with respect to commutation no-delay synchronization, failing edge, so as to fulfill voltage instability inside during commutation export in the case of, output that FG can stablize, so as to ensure that external equipment system being capable of normal operation.
Description
Technical field
The present invention relates to d.c. motor circuit fields, and in particular to a kind of electricity that d.c. motor output is controlled to stablize FG signals
Road.
Background technology
Motor has been widely used in the fields such as communication, industry, instrument manufacturing, in the application of various motors
In, d.c. motor is the most frequently used and most common.FG (frequency generator, frequency generator) is d.c. motor
One of critical function, FG signals represent the information such as the rotating speed of motor, position, are exported with impulse form from FG.External equipment can be with
Calculate the operating condition of motor according to FG signals, such as speed, flow, whether failure stalls, multiple FG signals can also realize
Electromagnetism coding regulates and controls device systems, therefore the intellectualized operation of equipment can be realized by FG signals.And realize intelligence
The premise for changing operation is to need stable FG signals.
At present, in DC motor drive chip in the market, FG signals follow directly after motor commutation information and change.Such as figure
Shown in 1, while two output signal OUT1, OUT2 commutations of motor chip, FG changes.In practical applications, by
Negative current can be generated when the external inductance of OUT1, OUT2 of motor chip, commutation, triggering parasitic triode conducting leads to inside
Power supply is unstable, if FG signals become low level by high level at this time, i.e. the efferent duct of FG is connected, then unstable power supply can export FG
The driving of pipe is insufficient, and FG is caused to become high level again by low level；After signal OUT1, OUT2 to be output stablize, internal electric source is stablized,
The efferent duct driving of FG is sufficient, and FG signals then become low level from high level again, so as to cause FG abnormal signals.To realize horse
The muting function reached, if the output termination capacitor of driving chip, when output signal OUT1, OUT2 switches, capacitance meeting charge and discharge,
Internal electric source shakiness is equally caused, causes FG abnormal signals, can not work normally so as to cause external equipment.
Invention content
In view of the above shortcomings of the prior art, the purpose of the present invention is to provide a kind of control d.c. motor outputs to stablize FG
The circuit of signal, so as to effectively avoid the problem that leading to external equipment cisco unity malfunction because of FG abnormal signals.
To achieve the above object, the present invention adopts the following technical scheme that：
A kind of circuit that d.c. motor output is controlled to stablize FG signals, including：
One drive module, commutation signal during according to motor running export corresponding drive signal, wherein, it is changed when described
When phase signals become low level from high level, the drive signal synchronously becomes high level from low level, when the commutation is believed
When number becoming high level from low level, the drive signal relative to the commutation signal be delayed after one section of predetermined delay time by
High level becomes low level；And
One is connected to the output control module of the drive module, and exporting corresponding FG according to the drive signal believes
Number, wherein, when the drive signal is low level, the FG signals of output are low level, when the drive signal is high level
When, the FG signals of output are high level.
Further, the drive module includes：
One first delayer, receives the commutation signal, and the timing since receive after the commutation signal, works as meter
When reach the predetermined delay time after export a clock signal；And
One first trigger, input end of clock connect the output terminal of first delayer, and set termination VDD power supplys are multiple
Position end receives the commutation signal, and reversed-phase output exports the drive signal.
Further, the drive module includes：
One second delayer, receives the commutation signal, and the timing since receive after the commutation signal, works as meter
When reach the predetermined delay time after export a clock signal；
One second trigger, input end of clock connect the output terminal of second delayer, and set end receives the commutation
Signal；
One phase inverter, input terminal receive the commutation signal；And
One or door, first input end connects the output terminal of the phase inverter, and the second input terminates second trigger
Reversed-phase output, output terminal export the drive signal.
Further, the output control module includes：
One first NMOS tube, drain electrode export the FG signals, source electrode ground connection；
One pull-up resistor, one termination VCC power supplys, the drain electrode of another termination first NMOS tube；
One current source, input termination VDD power supplys；
One second NMOS tube, drain and gate connect the output terminal of the current source, source electrode ground connection；And
One third NMOS tube, grid connect the output terminal of the drive module, source electrode ground connection, and drain electrode meets the first NMOS
The grid of pipe and the second NMOS tube.
Due to the adoption of the above technical scheme, it is no-delay in rising edge, failing edge with prior art FG signals and easily occur
Abnormal pulsers are compared, of the invention by the way that FG rising edges is controlled to have delay with respect to commutation with respect to the no-delay synchronization of commutation, failing edge, from
And realize during commutation is exported in the case of internal voltage instability, the output that FG can stablize, so as to ensure external equipment
System being capable of normal operation.
Description of the drawings
Fig. 1 is oscillogram of the prior art FG signals during motor exports commutation；
Fig. 2 is a kind of schematic diagram for the circuit that d.c. motor output is controlled to stablize FG signals of the present invention；
Fig. 3 is the schematic diagram of second embodiment of drive module of the present invention；
Fig. 4 is oscillogram of the FG signals of the invention generated during motor exports commutation.
Specific embodiment
Below in conjunction with the accompanying drawings, the preferable real example of the present invention is provided, and is described in detail.
As shown in Fig. 2, of the invention, i.e., a kind of circuit that d.c. motor output is controlled to stablize FG signals includes drive module 1
With output control module 2.Wherein, commutation signal Drive when drive module 1 is for according to motor running exports corresponding driving
Signal CTR_FG, wherein, when commutation signal Drive becomes low level from high level, drive signal CTR_FG is synchronously by low
Level becomes high level, and when commutation signal Drive becomes high level from low level, drive signal CTR_FG believes relative to commutation
Number Drive is delayed after one section of predetermined delay time T becomes low level from high level；Output control module 2 is used to be believed according to driving
Number CTR_FG exports corresponding FG signals, wherein, when drive signal CTR_FG is low level, the FG signals of output are low electricity
Flat, when drive signal CTR_FG is high level, the FG signals of output are high level.
In the embodiment of fig. 2, drive module 1 includes one first delayer 101 and one first trigger 102, wherein, the
Commutation signal Drive when one delayer 101 is used to receive motor running, and count since receive after commutation signal Drive
When, a clock signal Td is exported after timing reaches predetermined delay time T, for the clock demand of the first trigger 102；First
The input end of clock of trigger 102 connects the output terminal of delayer 101, set termination VDD power supplys, and reset terminal receives commutation signal
Drive, reversed-phase output QB export a drive signal CTR_FG, and driving enable signal is provided for follow-up output control module 2, with
Determine the low and high level of the FG signals of its output.
In the embodiment of fig. 2, output control module 2 includes one first NMOS tube NM1, drain electrode output FG signals, source
Pole is grounded；One pull-up resistor RL, one termination VCC power supplys, the drain electrode of the first NMOS tube of another termination；One current source I0, it is defeated
Enter to terminate VDD power supplys；One second NMOS tube NM2, drain and gate connect the output terminal of current source I0, source electrode ground connection；And one
Third NMOS tube NM3, grid connect the output terminal of drive module 1, source electrode ground connection, and drain electrode meets the first NMOS tube NM1 and second
The grid of NMOS tube NM2.
The work step of Fig. 2 embodiments is as follows：
When motor generation commutation, when Drive becomes low level from high level, first and second step is performed：
The first step, the Drive that the reset terminal of the first trigger 102 receives at this time is low level, and the first trigger 102 is in
State is reset to, no longer receives the clock signal Td of the first delayer 101 output；Meanwhile inverse output terminal QB outputs
CTR_FG is high level, and signal CTR_FG is synchronous with Drive to be changed.
Second step, under the excitation of the CTR_FG high level of synchronous variation, NM3 is connected in output control module 2, causes
The grid of NM1 is low level, and NM1 pipes are closed, and output signal FG becomes high level from low level, then FG synchronizes Drive variations.This
When, if exporting commutation, internal current source I0 will be caused unstable, i.e. the grid voltage of NM2 is unstable, since NM3 is synchronized with
Drive preferentially drags down NM1 grids, it is made no longer to be influenced by internal current source variation, the FG signals of output will steadily by
Low level becomes high level.
When motor generation commutation, when Drive becomes high level from low level, above-mentioned first and second step is skipped, is directly sequentially held
Row third and fourth, five steps：
Third walks, and under the changed excitations of Drive, 101 reclocking of the first delayer, timing reaches predetermined delay
After time T, clock signal Td is exported.
4th step, the Drive that the reset terminal of the first trigger 102 receives at this time is high level, can be worked.Believe in clock
Under the excitation of number Td, high level VDD is exported, then the drive signal CTR_FG of the inverse output terminal QB outputs of trigger is low electricity
It is flat, change the time T that has been delayed with respect to Drive.After delay, commutation at this time is completed, and power supply is stable.
5th step, under the low level excitations of drive signal CTR_FG of delay, NM3 is closed in output control module 2,
NM2 and NM1 forms current mirror, i.e.,：NM2 provides gate drive voltage, NM1 conductings for NM1, and output FG is low level.Then FG by
High level becomes low level and has been delayed time T with respect to commutation signal Drive.It avoids during commutation, FG outputs are unstable.
Fig. 3 gives second embodiment of drive module 1 of the present invention to realize that CTR_FG signal rising edges are no-delay same
Walk the function of mutually having delay in Drive in commutation signal Drive, failing edge.In the present embodiment, drive module 1 includes：One
Two delayers 103 receive commutation signal Drive, and the timing since receive after commutation signal Drive, when timing reaches
A clock signal Td is exported after predetermined delay time T；One second trigger 104, input end of clock connect the second delayer 103
Output terminal, set end receive commutation signal Drive；One phase inverter 105, input terminal receive commutation signal Drive；And one or
Door 106, first input end connect the output terminal of phase inverter 105, and the second input terminates the reversed-phase output of the second trigger 104,
Output terminal output drive signal CTR_FG.
From fig. 4, it can be seen that FG signals of the present invention are synchronized with Drive signal intensities when becoming high level from low level；By
Relative to changing after Drive delay times T when high level becomes low level, FG signal stabilizations, errorless pulse, so as to fulfill in horse
In the case of internal voltage instability during output commutation, output that FG signals can be stablized, so as to ensure external equipment system
System being capable of normal operation.
It is above-described, only presently preferred embodiments of the present invention, and non-limiting the scope of the present invention, above-mentioned reality of the invention
Applying example can also make a variety of changes.The letter that i.e. every claims applied according to the present invention and description are made
Single, equivalent changes and modifications fall within the claims of patent of the present invention.The not detailed description of the present invention is normal
Advise content.
Claims (4)
1. a kind of circuit that d.c. motor output is controlled to stablize FG signals, which is characterized in that including：
One drive module, commutation signal during according to motor running export corresponding drive signal, wherein, when the commutation is believed
When number becoming low level from high level, the drive signal synchronously becomes high level from low level, when the commutation signal by
When low level becomes high level, the drive signal is delayed after one section of predetermined delay time relative to the commutation signal by high electricity
It is flat to become low level；And
One is connected to the output control module of the drive module, and corresponding FG signals are exported according to the drive signal,
In, when the drive signal is low level, the FG signals of output are low level, defeated when the drive signal is high level
The FG signals gone out are high level.
2. the circuit of FG signals is stablized in control d.c. motor output according to claim 1, which is characterized in that the driving
Module includes：
One first delayer, receives the commutation signal, and the timing since receive after the commutation signal, when timing reaches
A clock signal is exported after to the predetermined delay time；And
One first trigger, input end of clock connect the output terminal of first delayer, set termination VDD power supplys, reset terminal
The commutation signal is received, reversed-phase output exports the drive signal.
3. the circuit of FG signals is stablized in control d.c. motor output according to claim 1, which is characterized in that the driving
Module includes：
One second delayer, receives the commutation signal, and the timing since receive after the commutation signal, when timing reaches
A clock signal is exported after to the predetermined delay time；
One second trigger, input end of clock connect the output terminal of second delayer, and set end receives the commutation signal；
One phase inverter, input terminal receive the commutation signal；And
One or door, first input end connects the output terminal of the phase inverter, and the second input terminates the reverse phase of second trigger
Output terminal, output terminal export the drive signal.
4. the circuit of FG signals is stablized in control d.c. motor output according to any one of claim 1-3, feature exists
In the output control module includes：
One first NMOS tube, drain electrode export the FG signals, source electrode ground connection；
One pull-up resistor, one termination VCC power supplys, the drain electrode of another termination first NMOS tube；
One current source, input termination VDD power supplys；
One second NMOS tube, drain and gate connect the output terminal of the current source, source electrode ground connection；And
One third NMOS tube, grid connect the output terminal of the drive module, source electrode ground connection, drain electrode connect first NMOS tube and
The grid of second NMOS tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810164851.8A CN108233799B (en) | 2018-02-27 | 2018-02-27 | Circuit for controlling output of DC motor to stabilize FG signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810164851.8A CN108233799B (en) | 2018-02-27 | 2018-02-27 | Circuit for controlling output of DC motor to stabilize FG signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108233799A true CN108233799A (en) | 2018-06-29 |
| CN108233799B CN108233799B (en) | 2024-02-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810164851.8A Active CN108233799B (en) | 2018-02-27 | 2018-02-27 | Circuit for controlling output of DC motor to stabilize FG signal |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07192357A (en) * | 1993-12-27 | 1995-07-28 | Sony Corp | Phase servo circuit for control single |
| US20030231875A1 (en) * | 2002-06-13 | 2003-12-18 | Halliburton Energy Services, Inc. | Digital adaptive sensorless commutational drive controller for a brushless dc motor |
| CN101789739A (en) * | 2010-03-15 | 2010-07-28 | 河海大学常州校区 | Method for controlling phase shifting stagger angle of doubly salient motor |
| CN102340273A (en) * | 2010-07-16 | 2012-02-01 | 安森美半导体贸易公司 | Motor driving circuit |
| JP2013200460A (en) * | 2012-03-26 | 2013-10-03 | Konica Minolta Inc | Image forming apparatus |
| CN106452059A (en) * | 2016-09-30 | 2017-02-22 | 北京兆易创新科技股份有限公司 | Drive circuit and charge pump circuit |
| CN106505918A (en) * | 2016-12-02 | 2017-03-15 | 四川英杰电气股份有限公司 | A kind of Brushless DC Motor Position detection method and system |
| CN207968360U (en) * | 2018-02-27 | 2018-10-12 | 上海灿瑞科技股份有限公司 | The circuit of FG signals is stablized in a kind of control d.c. motor output |
-
2018
- 2018-02-27 CN CN201810164851.8A patent/CN108233799B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07192357A (en) * | 1993-12-27 | 1995-07-28 | Sony Corp | Phase servo circuit for control single |
| US20030231875A1 (en) * | 2002-06-13 | 2003-12-18 | Halliburton Energy Services, Inc. | Digital adaptive sensorless commutational drive controller for a brushless dc motor |
| CN101789739A (en) * | 2010-03-15 | 2010-07-28 | 河海大学常州校区 | Method for controlling phase shifting stagger angle of doubly salient motor |
| CN102340273A (en) * | 2010-07-16 | 2012-02-01 | 安森美半导体贸易公司 | Motor driving circuit |
| JP2013200460A (en) * | 2012-03-26 | 2013-10-03 | Konica Minolta Inc | Image forming apparatus |
| CN106452059A (en) * | 2016-09-30 | 2017-02-22 | 北京兆易创新科技股份有限公司 | Drive circuit and charge pump circuit |
| CN106505918A (en) * | 2016-12-02 | 2017-03-15 | 四川英杰电气股份有限公司 | A kind of Brushless DC Motor Position detection method and system |
| CN207968360U (en) * | 2018-02-27 | 2018-10-12 | 上海灿瑞科技股份有限公司 | The circuit of FG signals is stablized in a kind of control d.c. motor output |
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| CN108233799B (en) | 2024-02-09 |
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