CN113794357A

CN113794357A - Fault processing circuit, chip, intelligent power module and household appliance

Info

Publication number: CN113794357A
Application number: CN202110863561.4A
Authority: CN
Inventors: 兰昊; 苏宇泉
Original assignee: Midea Group Co Ltd; Guangdong Midea White Goods Technology Innovation Center Co Ltd
Current assignee: Midea Group Co Ltd; Guangdong Midea White Goods Technology Innovation Center Co Ltd
Priority date: 2021-07-29
Filing date: 2021-07-29
Publication date: 2021-12-14

Abstract

The application discloses a fault processing circuit, a chip, an intelligent power module and a household appliance, wherein the fault processing circuit comprises a detection circuit, a fault recovery time circuit and a logic control circuit, and the detection circuit is used for detecting circuit faults and outputting control signals; the fault recovery time circuit is connected with the detection circuit and is configured to input a power supply signal and output a first detection signal according to the power supply signal and the control signal; the fault recovery time circuit comprises a first resistor, a first capacitor and a current amplification circuit, wherein the current amplification circuit is connected with the first resistor and the first capacitor and is used for amplifying current flowing through the first resistor; and the logic control circuit is connected with the fault recovery time circuit and used for outputting a fault signal according to the first detection signal. By means of the mode, the fault recovery time can be prolonged, and loss in a fault recovery circuit is reduced.

Description

Fault processing circuit, chip, intelligent power module and household appliance

Technical Field

The application relates to the technical field of circuits, in particular to a fault processing circuit, a chip, an intelligent power module and a household appliance.

Background

At present, functions such as overcurrent protection, overtemperature protection, undervoltage protection, input interlock, fault output, soft turn-off and the like are integrated in a chip. Fault output pulse width (i.e., fault recovery time t)_FLTCLR) Usually determined by the resistor R and capacitor C of the RCIN port, which are located outside the chip. In order to reduce the number of smart power template package components and reduce the complexity of IPM packaging, R and C need to be integrated into the chip. Generally, the resistance of the resistor R may be increased to extend the fault recovery time, but this results in almost all of the current flowing through the resistor R, making the fault recovery circuit more lossy at R.

Disclosure of Invention

The application mainly provides a fault processing circuit, a chip, an intelligent power module and a household appliance, and can solve the problem that the fault recovery time is short in the prior art and reduce the loss in the fault recovery time circuit.

To solve the above technical problem, a first aspect of the present application provides a fault handling circuit, including: the detection circuit is used for detecting circuit faults and outputting control signals; a fault recovery time circuit connected to the detection circuit and configured to input the power supply signal for outputting a first detection signal according to the power supply signal and the control signal; the fault recovery time circuit comprises a first resistor, a first capacitor and a current amplification circuit, wherein the current amplification circuit is connected with the first resistor and the first capacitor and is used for amplifying current flowing through the first resistor; and the logic control circuit is connected with the fault recovery time circuit and used for outputting a fault signal according to the first detection signal.

In order to solve the above technical problem, a second aspect of the present application provides a chip, which includes a control circuit and the aforementioned fault processing circuit, where the fault processing circuit is configured to output a fault signal, and the control circuit is connected to the fault processing circuit and configured to start or stop operation of the chip according to the fault signal.

In order to solve the above technical problem, a third aspect of the present application provides an intelligent power module, which includes the foregoing chip.

In order to solve the above technical problem, a fourth aspect of the present application provides a household appliance, which includes the foregoing smart power module.

The beneficial effect of this application is: different from the situation of the prior art, the fault processing circuit comprises a detection circuit, a fault recovery time circuit and a logic control circuit, wherein the detection circuit is used for detecting circuit faults and outputting control signals; the fault recovery time circuit is connected with the detection circuit and is configured to input a power supply signal for outputting a first detection signal according to the power supply signal and the control signal; the logic control circuit is connected with the fault recovery time circuit and used for outputting a fault signal according to the first detection signal; the fault recovery time circuit comprises a first resistor, a first capacitor and a current amplifying circuit, wherein the current amplifying circuit is connected with the first resistor and the first capacitor and used for amplifying the current flowing through the first resistor, so that the fault recovery time of the fault recovery time circuit can be prolonged by increasing the resistance value of the first resistor, and meanwhile, the current flowing through the first resistor is amplified through the current amplifying circuit, and the loss of the output current of the fault recovery time circuit can be reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:

fig. 1 is a schematic structural diagram of a first embodiment of a driving circuit provided in the present application;

fig. 2 is a schematic structural diagram of a second embodiment of a driving circuit provided in the present application;

fig. 3 is a schematic structural diagram of a third embodiment of a driving circuit provided in the present application;

fig. 4 is a schematic structural diagram of a fourth embodiment of a driving circuit provided in the present application;

fig. 5 is a schematic structural diagram of a fifth embodiment of a driving circuit provided in the present application;

fig. 6 is a schematic structural diagram of a sixth embodiment of a driving circuit provided in the present application;

fig. 7 is a schematic structural diagram of a seventh embodiment of a driving circuit provided in the present application;

FIG. 8 is a schematic block diagram of a first embodiment of a fault handling circuit provided herein;

FIG. 9 is a schematic diagram of a second embodiment of a fault handling circuit provided in the present application;

FIG. 10 is a schematic diagram of an embodiment of the fault recovery time circuit of FIG. 9;

FIG. 11 is a schematic diagram of an embodiment of the filter shaping circuit of FIG. 9;

FIG. 12 is a schematic diagram of a chip according to an embodiment of the present disclosure;

FIG. 13 is a schematic diagram of another embodiment of a chip provided herein;

FIG. 14 is a schematic block diagram of an embodiment of a smart power module provided herein;

FIG. 15 is a schematic structural diagram of an embodiment of a household appliance provided herein;

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first" and "second" in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

Referring to fig. 1 to 3, fig. 1 is a schematic structural diagram of a first embodiment of a driving circuit provided in the present application, fig. 2 is a schematic structural diagram of a second embodiment of the driving circuit provided in the present application, and fig. 3 is a schematic structural diagram of a third embodiment of the driving circuit provided in the present application.

As shown in fig. 1, in the present embodiment, the driving circuit 10 is configured to amplify a control signal output by a control circuit (not shown), so that the control signal can drive the power device 13, and drive and control the power device 13. The driving circuit 10 may include a switching unit 11 and a driving adjustment unit 12. The switching unit 11 is used for outputting a driving signal, and the driving adjustment unit 12 is used for adjusting the driving efficiency of the driving circuit 10. The driving adjustment unit 12 includes a first resistor Rg1 and a current amplification circuit 121, a first end of the first resistor Rg1 is connected to the switch unit 11, a first end of the current amplification circuit 121 is connected to the first resistor Rg1, and a second end of the current amplification circuit 121 is connected to the power device 13, and is configured to amplify the current flowing through the first resistor Rg 1.

The power device 13 may be a power semiconductor device, and is configured to act as a power switch. Power semiconductor devices can be classified into three categories, i.e., diodes (diodes), thyristors (Silicon controlled rectifiers), and Controllable switches (Controllable switches). The switching state of the diode is controlled by the main circuit (power circuit) itself, and is therefore also called passive switching, uncontrollable switching. A Thyristor, also called a Thyristor, can be turned on by a low power control signal, but can only be turned off by the main circuit (power circuit) itself and cannot be turned off by the control signal, and is therefore also called a semi-controllable switch. The on and off of the controllable switch can be realized by a low-power control signal. Controllable switches include, for example, GTO (Gate Turn-Off Thyristor), IGCT (integrated Gate Commutated Thyristor), IGBT (Insulated Gate Bipolar Transistor), VMOS (vertical conductive V-groove MOS Transistor). In some embodiments, the power device 13 may be a controllable switch.

The IGBT is a composite fully-controlled voltage-driven power Semiconductor device composed of BJT (Bipolar Junction Transistor) and MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and has the advantages of both high input impedance of MOSFET and low on-state voltage drop of GTR (Transistor). The GTR saturation voltage is reduced, the current carrying density is high, but the driving current is large; the MOSFET has small driving power, high switching speed, large conduction voltage drop and small current carrying density. The IGBT integrates the advantages of the two devices, and has small driving power and reduced saturation voltage. As a mainstream device of a novel power semiconductor device, the IGBT has been widely used in the conventional industrial fields of industry, 4C (communication, computer, consumer electronics, automotive electronics), aerospace, national defense, military industry, and the like, and in strategic emerging industrial fields of rail transit, new energy, smart grid, new energy automobile, and the like. Three poles of the IGBT are a G-base electrode, a C-collector electrode and an E-emitter electrode respectively. In this embodiment, the power device 13 is described as an IGBT as an example.

As shown in fig. 2, the switching unit 11 may be configured to input a power supply signal VCC and a control signal, and output a driving signal according to the power supply signal VCC and the control signal. The switching unit 11 may be composed of a transistor, for example, a MOS transistor.

A first input terminal (in) of the switch unit 11 may be connected to a control circuit (not shown), the control circuit is configured to output a control signal to the switch unit 11, a second input terminal of the switch unit 11 may be connected to a power supply, and the power supply may provide a high-level power supply signal. When the switching unit 11 inputs the control signal, the switching unit 11 outputs a driving signal according to the control signal and the power supply signal to drive the power device 13. The control circuit may be a microprocessor (e.g., MPU), and the control signal may be a pwm (pulse Width modulation) pulse signal. The power supply voltage of the power supply is, for example, 10-15V, but the embodiment is not limited thereto.

As shown in fig. 2, the driving adjustment unit 12 may be connected to the switching unit 11 and the power device 13, and configured to process the driving signal to drive the power device 13 with the processed driving signal. The driving adjustment unit 12 includes a first resistor Rg1 and a current amplification circuit 121, a first end of the first resistor Rg1 is connected to the switch unit 11, a first end of the current amplification circuit 121 is connected to the first resistor Rg1, and a second end of the current amplification circuit 121 is connected to the power device 13, and is configured to amplify the current flowing through the first resistor Rg 1. Alternatively, the first terminal of the current amplifying circuit 121 may be connected to the first terminal of the first resistor Rg1, or may be connected to the second terminal of the first resistor Rg1, as long as the current flowing through the first resistor Rg1 can be amplified.

In some embodiments, as shown in fig. 2, the current amplifying circuit 121 includes a first switch transistor T1, a first terminal of the first switch transistor T1 is connected to a first terminal of a first resistor Rg1, a second terminal of the first switch transistor T1 is connected to the power device 13, and a control terminal of the first switch transistor T1 is connected to a second terminal of a first resistor Rg 1. The first switch tube T1 can perform a current amplification function, so that the current flowing through the first resistor Rg1 can be amplified.

In some embodiments, the current amplifying circuit 121 includes a first capacitor C1, a first terminal of the first capacitor C1 is connected to a second terminal of the first resistor Rg1, and a second terminal of the first capacitor C1 is grounded. The first capacitor C1 and the first resistor Rg1 are used to control the gain of the first switch transistor T1, that is, the amplification factor of the first switch transistor T1 on the current flowing through the first resistor Rg 1.

In some embodiments, the amplification factor of the first switch tube T1 is a (a >1), and the equivalent capacitance of the first resistor Rg1, the first capacitor C1, the first switch tube T1 and the constituent driving adjustment unit 12 is a × C1. In this embodiment, the current magnitude of the control terminal of the first switch transistor T1 is determined by the states of the first resistor Rg1 and the first capacitor C1, so that under the condition that the normal driving power device 13 is satisfied, the current of the control terminal of the first switch transistor T1 can be relatively small, so the first resistor Rg1 can be appropriately large, the first capacitor C1 can be appropriately small, and the occupied areas of the first capacitor C1 and the first resistor Rg1 can be reduced. It can be understood that the resistance of the resistor is increased, the volume of the resistor is reduced, and the area of the driving circuit 10 is also reduced. Since the area occupied by the first switching transistor T1 is much smaller than that occupied by the gate resistor, the area occupied by the driving adjustment unit 12 as a whole in the driving circuit is reduced although the first switching transistor T1 is increased.

In some embodiments, the first switch transistor T1 may be a transistor or the like capable of amplifying current. The first switch transistor T1 is exemplified as a triode in the present embodiment. A transistor, i.e., a semiconductor transistor, also called a bipolar transistor or a transistor, is a semiconductor device for controlling current, and functions to amplify a weak signal into an electrical signal with a large amplitude. The triode has three electrodes of base electrode, collector electrode and emitter electrode, and the current amplification effect of the triode actually utilizes the tiny change of the base electrode current to control the huge change of the collector electrode current. The triode can be divided into a germanium tube and a silicon tube according to the material. The triode is formed by manufacturing two PN junctions which are very close to each other on a semiconductor substrate, the whole semiconductor is divided into three parts by the two PN junctions, the middle part is a base region, the two side parts are an emitter region and a collector region, and the arrangement modes include PNP and NPN. Currently, the more used triodes are silicon NPN and germanium PNP. In this embodiment, the type of the transistor is not limited, and for example, the transistor may be an NPN type transistor, and the material is silicon.

In this embodiment, the first terminal of the first switch transistor T1 is a collector of the transistor, the second terminal of the first switch transistor T1 is an emitter of the transistor, and the control terminal of the first switch transistor T1 is a base of the transistor. The connection relationship between the triode and other devices or units is described as follows: a collector of the NPN transistor may be connected to the switching unit 11, an emitter of the NPN transistor may be connected to the power device 13, a base of the NPN transistor may be connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 may be connected to a ground level (i.e., grounded). Correspondingly, a first end of the first resistor Rg1 may be connected to a collector of the NPN transistor, a second end of the first resistor Rg1 is connected to a base of the NPN transistor, a first end of the first capacitor C1 is also connected to the base of the NPN transistor, and a second end of the first capacitor C1 is grounded.

In some embodiments, as shown in fig. 2, the switching unit 11 may include a second switching tube T2 and a third switching tube T3. The second switching tube T2 and the third switching tube T3 may be different kinds of switching tubes. For example, the switching characteristics of the second switching tube T2 and the third switching tube T3 may be reversed. The control terminal of the second switch transistor T2 may be connected to the control circuit for inputting the control signal, the first terminal of the second switch transistor T2 may be connected to the power supply for inputting the power supply signal, and the second terminal of the second switch transistor T2 may be connected to the input terminal of the driving adjustment unit 12. A control terminal of the third switching transistor T3 may be connected to the control circuit, a first terminal of the third switching transistor T3 may be connected to the output terminal of the driving adjustment unit 12, and a second terminal of the third switching transistor T3 may be grounded. It is understood that the kinds and parameters (breakdown voltage, power consumption, etc.) of the second switch transistor T2 and the third switch transistor T3 may be selected according to practical situations, and are not limited herein.

The MOS tube has the advantages of high input impedance, low noise, large dynamic range, low power consumption, easy integration and the like. The MOS tube can comprise an N-type MOS tube (NMOS tube) and a P-type MOS tube (PMOS tube). In some embodiments, the switching unit 11 may be a complementary MOS circuit composed of two transistors, an NMOS transistor and a PMOS transistor, i.e., a CMOS circuit. The second switch transistor T2 may be a P-type MOS transistor, and the third switch transistor T3 may be an N-type MOS transistor. It can be understood that this embodiment only illustrates the switch unit 11 composed of a pair of MOS transistors, and in other embodiments, the switch unit 11 may include a plurality of pairs of MOS transistors, and specifically may include a plurality of complementary pairs of MOS transistors (P-type MOS transistor and N-type MOS transistor), which is not described herein again.

In some embodiments, as shown in fig. 2, the gate of the PMOS transistor is connected to a control circuit (not shown) for inputting a control signal, the source of the PMOS transistor is connected to the power supply for inputting a power signal VCC, and the drain of the PMOS transistor is connected to the collector of the transistor; the grid electrode of the NMOS tube is connected with the control circuit to input a control signal, the source electrode of the NMOS tube is connected with the emitting electrode of the triode to be connected with the base electrode of the IGBT, and the drain electrode of the NMOS tube is grounded. When the control signal is at a high level, the PMOS transistor is turned on, a source electrode of the PMOS transistor inputs a power supply signal VCC, a drain electrode of the PMOS transistor outputs a driving signal, a part of current of the driving signal passes through the first resistor Rg1, the first capacitor C1 is charged through the first resistor Rg1, the first end of the first capacitor C1 is connected to a base electrode of the triode, and the second end of the first capacitor C1 is grounded, so that a base current of the triode can be formed after charging for a period of time, and a collector electrode and an emitter electrode of the triode are turned on, at this time, another part of current of the driving signal is output to the power device 13 after being amplified by the triode, and specifically, the triode can amplify the current by a time (a > 1). Under the unchangeable condition of the electric current size of drive signal, because the triode has passed through some electric currents, first resistance Rg1 has passed through some electric currents, compares in the direct condition of acting on first resistance Rg1 of whole electric currents, and the reliability and the life-span of first resistance Rg1 are better among the drive regulating unit 12 that this embodiment provided.

In some embodiments, as shown in fig. 3, the driving circuit 10 may further include a turn-off unit 14. A first terminal of the turn-off unit 14 is connected to a first terminal of the third switching tube T3, and a second terminal of the turn-off unit 14 is connected to a second terminal of the first switching tube T1. The shutdown unit 14 is used for adjusting the driving efficiency of the driving circuit 10 when the control signal is a low level signal. In some embodiments, the turn-off unit 14 may include a second resistor Rg, off having a first end connected to the first end of the third switch tube T3 and a second end connected to the output end of the driving adjustment unit 12, which is also the second end of the first switch tube T1.

Specifically, a first end of the second resistor Rg, off may be connected to the source of the NMOS transistor, and a second end of the second resistor Rg, off is connected to the emitter of the NPN transistor. Alternatively, the turn-off unit 14 may include a plurality of second resistors Rg, off, and the plurality of resistors may be connected in parallel and/or in series, and the specific connection manner is not limited. For example, the turn-off unit may include two second resistors Rg, off, which are connected in parallel and then connected into the circuit.

In some embodiments, as shown in fig. 3, the driving circuit 10 may further include a filtering unit 15, a first end of the filtering unit 15 is connected to a second end of the current amplifying circuit 121, that is, connected to a path between the first switch tube T1 and the power device 13, and a second end of the filtering unit 15 is grounded, for performing auxiliary filtering processing on the current signal output by the output end of the first switch tube T1.

In some embodiments, as shown in fig. 3, the filtering unit 15 may include a second capacitor C2, a first terminal of the second capacitor C2 is connected to the second terminal of the first switch transistor T1, i.e., between the first switch transistor T1 and the IGBT, and a second terminal of the second capacitor C2 is grounded. In other embodiments, the filtering unit 15 may include a plurality of second capacitors C2, and the plurality of second capacitors C2 may be connected in parallel and/or in series, and the connection manner is not limited. For example, the filtering unit 15 may include two, three, or four second capacitors C2. In some embodiments, the first capacitor C1 and the second capacitor C2 may be variable capacitors, and the specific parameters may be selected according to actual conditions.

In the above solution, the driving circuit includes a switching unit and a driving adjustment unit, for driving the power device, the switching unit is configured to input a power signal and a control signal, and output a driving signal according to the power signal and the control signal, the driving adjustment unit is connected to the switching unit and the power device, and is configured to amplify the driving signal, so as to drive the power device by using the amplified driving signal, wherein the driving adjustment unit includes a first resistor and a current amplification circuit, a first end of the first resistor is connected to the switching unit, a first end of the current amplification circuit is connected to the first resistor, a second end of the current amplification circuit is connected to the power device, and is configured to amplify a current flowing through the first resistor, so as to adjust sizes of the first resistor and the first capacitor, and reduce an occupied area of the first resistor and the first capacitor, the normal driving of the power device is realized, and the driving circuit can be integrated in a chip.

Referring to fig. 4 to 7, fig. 4 is a schematic structural diagram of a fourth embodiment of a driving circuit provided in the present application, fig. 5 is a schematic structural diagram of a fifth embodiment of the driving circuit provided in the present application, fig. 6 is a schematic structural diagram of a sixth embodiment of the driving circuit provided in the present application, and fig. 7 is a schematic structural diagram of a seventh embodiment of the driving circuit provided in the present application.

Both the present embodiment and the above embodiments can provide a driving circuit with a smaller occupied area, but compared with the above embodiments, the driving circuit provided by the present embodiment uses the switching tube in the multiplexing driving circuit as the resistor (i.e., the gate resistor) on the current path of the driving switch, so as to avoid designing an additional resistor in the driving circuit as the gate resistor, and further reduce the occupied area of the driving circuit.

The driving circuit may be configured to amplify the control signal output by the control circuit, so that the driving circuit can drive the power device and implement driving control of the power device. In this embodiment, the driving circuit may include a first switching tube and a second switching tube. The first end of the first switch tube is configured to input a power supply signal, the first end of the second switch tube is connected with the second end of the first switch tube, and the second end of the second switch tube is connected with the power device; wherein, the control terminal of one of the first switch tube and the second switch tube is configured to input a control signal to serve as a driving switch, and the other of the first switch tube and the second switch tube 22 is configured to serve as a resistor on a current path of the driving switch when the driving switch is turned on.

It can be understood that the driving circuit may include a plurality of switching tubes, wherein the plurality of switching tubes may operate as driving switches in a time-sharing manner, that is, one or more idle switching tubes that are not operated exist in a certain period of time, and the present embodiment uses the idle switching tubes as gate resistors to fully utilize the switching tubes in the driving circuit and reduce the occupied area of the gate resistors in the driving circuit.

As shown in fig. 4 and fig. 5, in the present embodiment, the driving circuit 20 may include a first switching tube 21 and a second switching tube 22, wherein the first switching tube 21 is a driving switch, a control terminal of the first switching tube 21 inputs a control signal, a first terminal of the first switching tube 21 inputs a power signal, and a second terminal of the first switching tube 21 is used for outputting a driving signal to drive the power device 25 by the driving signal; the second switch tube 22 connects the second end of the first switch tube 21 and the signal output end to act as a resistor on the current path of the first switch tube 21 when the first switch tube 21 is turned on. At this time, the second switch tube 22 is in a conducting state when the first switch tube 21 is turned on. In this embodiment, the power device 25 can be described by referring to the corresponding position of the above embodiment, and the power device 25 is taken as an IGBT as an example for description.

In other embodiments, the first switch tube 21 and the second switch tube 22 may be switched, that is, the second switch tube 22 may be used as a driving switch, and the first switch tube 21 may be used as a resistor in a current path of the first switch tube 21 when the first switch tube 21 is turned on. Specifically, the first switch tube 21 may be used as a resistance switch at this time, a first end of the first switch tube 21 inputs a power signal, a second end of the first switch tube 21 is connected to a first end of the second switch tube 22, a control end of the second switch tube 22 is used for inputting a control signal, a second end of the second switch tube 22 is connected to a signal output end, and the second switch tube 22 may output a driving signal according to the control signal. At this time, the first switch tube 21 is in a conducting state when the second switch tube 22 is turned on.

When the first switch tube 21 is a driving switch, the number of the second switch tubes 22 may be multiple, and the multiple second switch tubes 22 are connected in series. It is understood that the number of the second switch tubes 22 may be selected according to the required size of the gate resistor, and when there are a plurality of second switch tubes 22, the connection manner of the plurality of second switch tubes 22 may also be designed, for example, the plurality of second switch tubes may be connected in series and/or in parallel to obtain the required resistance value of the gate resistor. In other embodiments, when the second switch tube 22 is a driving switch, the number of the first switch tubes 21 may be multiple, and multiple first switch tubes 21 may be connected in series and/or in parallel. Next, the present embodiment will be further described by taking the first switch tube 21 as a driving switch as an example.

In some specific embodiments, the first switch tube 21 may be a P-type transistor (e.g., a P-type MOS transistor), the control terminal of the first switch tube 21 is a gate of the P-type transistor, the first terminal of the first switch tube 21 may be a source of the P-type transistor, and the second terminal of the first switch tube 21 may be a drain of the P-type transistor. The gate of the P-type transistor can be connected to a control circuit (not shown) for inputting a control signal, the source of the P-type transistor can be connected to a power supply for inputting a power signal (VBX or VCC), and the drain of the P-type transistor can be connected to the second switch tube 22 for outputting a driving signal from the signal output terminal out through the second switch tube 22. The base electrode G of the IGBT is connected with the signal output end out so as to obtain a driving signal output by the signal output end out.

In some embodiments, as shown in fig. 5, the driving circuit 20 further includes a third switching tube 23, and the first switching tube 21 and the third switching tube 23 both serve as driving switches. The switching characteristics of the first switching tube 21 and the third switching tube 23 are opposite. A first end of the first switch tube 21 can input a power signal, a second end of the first switch tube 21 is used for outputting a driving signal, and a control end of the first switch tube 21 can input a control signal; the first end of the third switching tube 23 is connected to the signal output end out, and the second end of the third switching tube 23 is connected to the ground level, i.e. grounded; the control end of the third switch tube 23 inputs a control signal to be used as a driving switch.

In some embodiments, as shown in fig. 5, the driving circuit 20 further includes a fourth switching tube 24, wherein the switching characteristics of the second switching tube 22 and the fourth switching tube 24 are opposite to each other. The first end of the second switch tube 22 is connected to the second end of the first switch tube 21, the second end of the second switch tube 22 is connected to the signal output end out, the first end of the fourth switch tube 24 is connected to the signal output end out, and the second end of the fourth switch tube 24 is connected to the first end of the third switch tube 23. The second switch tube 22 and the fourth switch tube 24 can be used as a resistor in a circuit where the driving switch is located in a conducting state, so as to adjust the driving efficiency.

In some embodiments, the second switch tube 22 and/or the fourth switch tube 24 may be in a normally open state, i.e., in a conducting state all the time. The second switch 22 may be in a normally open state, for example, the second switch 22 may be a P-type transistor, the control terminal of the second switch 22 is grounded, and at this time, the second switch 22 is in the normally open state. In some embodiments, the fourth switching tube 24 may be in a normally-open state, for example, the fourth switching tube 24 is an N-type transistor, and the control terminal of the fourth switching tube 24 inputs the power signal, at this time, the fourth switching tube 24 is in the normally-open state.

In other embodiments, the second switch tube 22 and/or the fourth switch tube 24 may be in a very on state, for example, a control terminal of the second switch tube 22 and/or the fourth switch tube 24 is connected to a control circuit (not shown) to input a control signal, and is turned on or off according to the control signal. The second switch tube 22 may be a P-type transistor, and a gate of the P-type transistor is connected to the control circuit to input the control signal; the fourth switch tube 24 is an N-type transistor, and a gate input of the N-type transistor is connected to the control circuit for inputting the control signal. When the first switch tube 21 and the second switch tube 22 are respectively turned on, correspondingly, the second switch tube 22 and the fourth switch tube 24 are also turned on to form a resistor, and otherwise, the second switch tube 22 and the fourth switch tube 24 may be in an off state.

In the related art, the driving circuit 20 includes a plurality of gate resistors, so as to change the number of the gate resistors in the access circuit according to the requirements of different application scenarios, thereby adjusting the resistance of the gate resistors in the access circuit. Generally, to obtain a gate resistor with a small resistance value, a plurality of gate resistors are generally connected in parallel, and it can be understood that the resistance value after parallel connection is lower than that of any one of the resistors. However, the method of providing a plurality of gate resistors occupies a large area of the drive circuit 20. In addition, the temperature and current capability of the resistors in the driver circuit 20 are highly required.

Therefore, in the present embodiment, the first switch tube 21 and the second switch tube 22 in the idle state in the driving circuit 20 are connected in series, the third switch tube 23 and the fourth switch tube 24 are connected in series, and are used as the resistance on the driving switch path when being turned on, so that the gate resistance can be prevented from being additionally arranged in the driving circuit 20, and in addition, the number of the second switch tube 22 and/or the fourth switch tube 24 in the access circuit can be selected, so as to adjust the resistance value of the gate resistance combined by the second switch tube 22 and/or the fourth switch tube 24 in the access circuit according to the requirements of different application scenarios, and the operation is convenient and the cost is low.

In some embodiments, as shown in fig. 6, the driving circuit 20 may further include a first resistor Rg1, where the first resistor Rg1 is connected between the driving switch (the first switch tube 21 or the second switch tube 22) and the signal output end out. When the number of the second switch tubes 22 that can be used as resistors in the driving circuit 20 is small, that is, the resistance of the gate resistor formed by the plurality of second switch tubes 22 is small, at this time, the first resistor Rg1 can be arranged in the driving circuit 20, and the first resistor Rg1 is connected in series with the second switch tubes 22, so that when the number of the second switch tubes 22 is insufficient, the requirement of the high-resistance gate resistor can be met in the access circuit.

In some embodiments, as shown in fig. 7, the driving circuit 20 may further include a first resistor Rg1 and a second resistor Rg2, a first end of the first resistor Rg1 is connected to the second end of the second switch 22, a second end of the first resistor Rg1 is connected to the signal output end out, a first end of the second resistor Rg2 is connected to the signal output end out, and a second end of the second resistor Rg2 is connected to the first end of the fourth switch 24, that is, the first resistor Rg1 and the second resistor Rg2 are respectively disposed in the charging circuit for charging and the discharging circuit for discharging, that is, the current passes through the first resistor Rg1 during charging and the current passes through the second resistor Rg2 during discharging.

In some embodiments, the first switch tube 21 and the second switch tube 22 are the same switch tube, and/or the third switch tube 23 and the fourth switch tube 24 are the same switch tube. For example, the first switch tube 21 and the second switch tube 22 may be PMOS tubes, and the third switch tube 23 and the fourth switch tube 24 may be NMOS tubes. It can be understood that the same switch is convenient for calculating the resistance of the gate resistor when the resistance is calculated, and is convenient for adjusting the switch tube to form the resistor with the target resistance. The same type of switch is, for example, the type and resistance of the switch tube are the same.

In the above scheme, the driving circuit of the present application is used for driving a power device, and the driving circuit includes: a first switch tube, wherein a first end of the first switch tube is configured to input a power supply signal; the first end of the second switching tube is connected with the second end of the first switching tube, and the second end of the second switching tube is connected with the power device; the control end of one of the first switch tube and the second switch tube is configured to input a control signal to serve as a driving switch, and the other switch tube is configured to serve as a resistor on a current path of the driving switch when the driving switch is turned on. It is thus clear that, because the switch tube has the resistance under the on-state, this application is through configuring first switch tube or second switch tube in the drive circuit as the resistance on the drive switch current path when drive switch opens to can avoid additionally setting up grid resistance in drive circuit, thereby can reduce drive circuit's area.

Further, by adjusting the switching tube to be a resistor, it is consistent with the driving switch due to the temperature performance and current capability of the switching tube, and the driving switch is used as a core part of the driving circuit, which is mature.

Referring to fig. 8 to 11, fig. 8 is a schematic structural diagram of a first embodiment of a fault handling circuit provided in the present application, fig. 9 is a schematic structural diagram of a second embodiment of a fault handling circuit provided in the present application, fig. 10 is a schematic structural diagram of an embodiment of a fault recovery time circuit in fig. 9, and fig. 11 is a schematic structural diagram of an embodiment of a filter shaping circuit in fig. 9.

At present, functions such as overcurrent protection, overtemperature protection, undervoltage protection, input interlock, fault output, soft turn-off and the like are integrated in a chip. The fault output pulse width (i.e., fault recovery time) is generally determined by the resistance R and capacitance C of the RCIN port, and the fault recovery time is calculated as follows:

t_FLTCLR＝-(R·C)·In(1-V_RCIN+/VCC)，

wherein, V_RCIN+Fault recovery threshold voltage, VCC supply voltage, t_FLTCLRAnd in the fault recovery time, R is the resistance value of the resistor, and C is the capacitance value of the capacitor.

For example, when C is 1nF, R is 2.2M Ω, V_RCIN+When VCC is 15V, t can be obtained_FLTCLR＝1.68ms。

Typically, the resistor R and the capacitor C are located outside the chip. To reduce the number of smart power template package components and reduce IPM package complexity, R and C may be integrated into the chip, but in order to allow t_FLTCLRWithin a suitable range, R and C need to be sized. In general, the capacitance of the capacitor in the fault recovery time circuit is large, for example, when C is 1nF, the capacitance integrated in the chip is usually at most ten and several pF, and if a capacitance having a pF capacitance is used in the fault recovery time circuit, t is t_FLTCLRIt is difficult to achieve ms level, generally within tens of us, such t_FLTCLRShorter, which is not conducive to the response of the back-end control circuit. If the resistance value of R in the fail-back time circuit is increased, almost all of the current flows through R, and loss occurs. Thus, the present application provides a fault handling circuit that can extend the fault recovery time, for example, to the order of milliseconds. As can be appreciated, t_FLTCLRMay be determined by at least one of R and C.

In the present embodiment, the failure processing circuit 30 may include a detection circuit 31, a failure recovery time circuit 32, and a logic control circuit 33.

The detection circuit 31 is used for detecting circuit failure and outputting a control signal. For example, when detecting the over-current signal, the detection circuit 31 indicates that an over-current occurs in the chip, so as to output a control signal, where the control signal is used to stop the operation of the chip, thereby implementing the over-current protection function of the chip.

In some embodiments, as shown in fig. 9, the detection circuit 31 may include a comparator, a first input terminal of the comparator is used for inputting the signal to be detected, a second input terminal of the comparator is used for inputting the reference signal, and an output terminal of the comparator is used for outputting the control signal.

Wherein a comparator (comparator) may compare two or more data items to determine whether they are equal or to determine the magnitude relationship and the order between them. Typically, a comparator has five pins, namely a "-" input pin, a "+" input pin, an output pin, a positive side power pin, and a negative side power pin. The positive side power pin may be connected to a power supply and the negative side power pin may be grounded. Any input pin can be selected as a reference pin to fix voltage, the difference between the reference voltage and the voltage input to the other pin is amplified, and high level or low level is output. In this embodiment, the output terminal of the comparator may be an output pin, and the positive power pin may be connected to the power supply to input the power supply voltage VCC, and the negative power pin may be grounded GND.

In this embodiment, as shown in fig. 9, the first input terminal of the comparator may be a "-" input pin, and the second input terminal of the comparator may be a "+" input pin, that is, the "+" input pin is selected as a reference terminal, when the potential of the signal to be detected input by the "-" input pin is greater than the potential of the reference signal, the output terminal of the comparator outputs a low-level signal (e.g., 0V), otherwise, the output terminal of the comparator outputs a high-level signal. It can be understood that when the potential of the signal to be detected is greater than the potential of the reference signal, it indicates that an overcurrent phenomenon occurs at this time, so that a low-level signal needs to be output to enable the logic control circuit 33 to also output a low-level fault signal, and the fault signal can be output to a control circuit at the rear end, so that the control circuit can control the chip to stop working, thereby protecting the chip from being damaged. When the fault is recovered, the potential of the signal to be detected is less than that of the reference signal, the output end of the comparator outputs a high level signal to the fault recovery time circuit 32, and after the fault recovery time circuit 32 performs delay processing, the output end of the comparator outputs a first detection signal to the logic control circuit 33, so that the logic control circuit 33 outputs a high level fault signal, and the back-end control circuit can control the chip to start working according to the high level fault signal.

In some embodiments, the detection circuit 31 may further include a bootstrap capacitor (not shown), a first end of the bootstrap capacitor is connected to the second input terminal of the comparator to input the reference signal to the comparator, and a second end of the bootstrap capacitor is grounded. Optionally, the voltage of the bootstrap capacitor is 0.5V.

In some embodiments, as shown in fig. 9, the detection circuit 31 may further include an ESD (electrostatic discharge) protection circuit. The input end of the ESD protection circuit is used for inputting a signal to be detected, and the output end of the ESD protection circuit is connected with the first input end of the comparator and used for inputting the signal to be detected into the comparator for comparison. The ESD protection circuit may further include a positive-side power supply pin connectable to a power supply to input the supply voltage VCC, and a negative-side power supply pin connectable to the ground GND.

Specifically, the first end of the ESD protection circuit may be connected to an ITRIP input port, and the ITRIP input port may output a signal to be detected to the ESD protection circuit.

When the integrated circuit device works in a certain voltage, current and power consumption limited range, a large amount of accumulated static charges can generate high-voltage discharge under proper conditions, and the high voltage of the static discharge through a device lead is transmitted instantaneously, so that an oxide layer can be disconnected, and the device can be out of order. Among the causes of static electricity, triboelectrification, induction electrification, and contact electrification may be mentioned. Specifically, the ESD protection circuit may include an ESD protection diode for preventing static electricity from affecting the inside of the detection circuit 31. The ESD protection diode is a novel integrated electrostatic protection device, the inside of the ESD protection diode is equivalent to a Zener diode, when the input current exceeds the rated voltage of the Zener diode, the Zener diode can be broken down, and excessive electric energy is conducted back to the ground, so that the ESD protection diode plays a role in protecting a circuit. The ESD protection diode may be a transient suppression diode, which guides static electricity to the ground by using a reverse breakdown operation principle of a P-N junction, thereby functioning as a protection circuit. Alternatively, the ESD protection circuit may also use other elements or combinations of elements to implement the ESD protection, which is not limited in this embodiment.

As shown in fig. 10, the fail-back time circuit 32 may be connected to the detection circuit 31 and configured to input the power signal for outputting the first detection signal according to the power signal and the control signal. The fault recovery time circuit 32 includes a first resistor R1, a first capacitor C1, and a current amplifying circuit 3221, where the current amplifying circuit 3221 is connected to the first resistor R1 and the first capacitor C1, and is configured to amplify a current flowing through the first resistor R1, so that a resistance value of the first resistor R1 may be increased to prolong a fault recovery time of the fault recovery time circuit 21, and meanwhile, the current flowing through the first resistor R1 is amplified by the current amplifying circuit 3221, so that a loss of the current output by the fault recovery time circuit 32 may be achieved.

In some embodiments, the fail-back time circuit 32 may include a first switching unit 321, a delay unit 322, and a first shaping unit 323. Among them, the first switching unit 321 may be configured to input the control signal and the power signal and output the first detection signal according to the control signal and the power signal. The delay unit 322 may be connected to the first switch unit 321, and configured to perform a delay process on the first detection signal. The delay unit 322 may include a resistor R1, a first capacitor C1, and a current amplifying circuit 3221, wherein a first end of the first resistor R1 is connected to the first switching unit 321, a first end of the first capacitor C1 is connected to a second end of the first resistor R1, a second end of the first capacitor C1 is grounded, and a first end of the current amplifying circuit 3221 is connected to a first end of the first resistor R1, and is configured to amplify a current flowing through the first resistor R1. The first shaping unit 323 is connected to the delay unit 322 and the logic control circuit 33, and is configured to shape the first detection signal.

As shown in fig. 10, in particular, a first terminal of the first switch transistor T1 may be connected to a first terminal of the first resistor R1, a second terminal of the first switch transistor T1 may be connected to the first shaping unit 323, and a control terminal of the first switch transistor T1 is connected to a second terminal of the first resistor R1. The first switching tube T1 can amplify the current. If the amplification factor of the first switch tube T1 is a (a >1), the equivalent capacitance of the delay unit formed by the first switch tube T1, the first capacitor C1 and the first resistor R1 is a × C1, and the capacitance is relatively large, so that the corresponding delay effect is relatively good. In this embodiment, the current magnitude of the control terminal of the first switch transistor T1 is determined by the states of the first capacitor C1 and the first resistor R1, so that the current of the control terminal of the first switch transistor T1 can be relatively small, and the first resistor R1 is also a filter resistor, so that the first resistor R1 can be appropriately increased, and the first capacitor C1 can be appropriately decreased, so that the occupied areas of the first capacitor C1 and the first resistor R1 can be reduced. It can be understood that the resistance of the resistor is increased, the volume of the resistor is reduced, and the area of the fault handling circuit 30 can be reduced. The occupied area of the first switch tube T1 is much smaller than that of the driving resistor.

In this embodiment, the first terminal of the first switch transistor T1 is a collector of the transistor, the second terminal of the first switch transistor T1 is an emitter of the transistor, and the control terminal of the first switch transistor T1 is a base of the transistor. The connection relationship between the triode and other devices or units is described as follows: a collector of the NPN transistor may be connected to the first end of the first resistor R1, an emitter of the NPN transistor may be connected to the first shaping unit 323, a base of the NPN transistor may be connected to the first end of the first capacitor C1, and a second end of the first capacitor C1 may be connected to a ground level (i.e., grounded). Correspondingly, a first end of the first resistor R1 may be connected to a collector of the NPN transistor, a second end of the first resistor R1 is connected to a base of the NPN transistor, a first end of the first capacitor C1 is also connected to the base of the NPN transistor, and a second end of the first capacitor C1 is grounded.

Alternatively, the first switching unit 321 may be composed of a switching tube, for example, a MOS tube.

In some embodiments, as shown in fig. 10, the first switching unit 321 may include a second switching tube T2 and a third switching tube T3. The second switching tube T2 and the third switching tube T3 may be different kinds of switching tubes. For example, the switching characteristics of the second switching tube T2 and the third switching tube T3 may be reversed. The control terminal of the second switch tube T2 is connected to the detection circuit 31 for inputting the control signal, the first terminal of the second switch tube T2 is connected to the power supply for inputting the power supply signal, and the second terminal of the second switch tube T2 is connected to the input terminal of the delay unit 322 for outputting the first detection signal to the delay unit 322 according to the control signal. The control terminal of the third switch transistor T3 is connected to the detection circuit 31 for inputting the control signal, the first terminal of the third switch transistor T3 is connected to the output terminal of the delay unit 322, and the second terminal of the third switch transistor T3 is grounded. It is understood that the kinds and parameters (breakdown voltage, power consumption, etc.) of the second switch transistor T2 and the third switch transistor T3 may be selected according to practical situations, and are not limited herein.

The MOS tube has the advantages of high input impedance, low noise, large dynamic range, low power consumption, easy integration and the like. The MOS tube can comprise an N-type MOS tube (NMOS tube) and a P-type MOS tube (PMOS tube). In some embodiments, the first switch unit 321 may be a complementary MOS circuit composed of two transistors, i.e., an NMOS transistor and a PMOS transistor, i.e., a CMOS circuit. The second switch transistor T2 may be a P-type MOS transistor, and the third switch transistor T3 may be an N-type MOS transistor.

In some embodiments, the gate of the PMOS transistor is connected to the detection circuit 31 for inputting the control signal, the source of the PMOS transistor is connected to the power supply for inputting the power signal VCC, and the drain of the PMOS transistor is connected to the collector of the triode; the gate of the NMOS transistor is connected to the detection circuit 31 for inputting the control signal, the source of the NMOS transistor is connected to the emitter of the triode for connecting to the first end of the first shaping unit 323, and the drain of the NMOS transistor is grounded. When the control signal is at a high level, the PMOS transistor is turned on, a power signal VCC is input to a source electrode of the PMOS transistor, a first detection signal is output from a drain electrode of the PMOS transistor, a part of current of the first detection signal passes through the first resistor R1, the first capacitor C1 is charged through the first resistor R1, the first end of the first capacitor C1 is connected to a base electrode of the triode, and the second end of the first capacitor C1 is grounded, so that a base current of the triode can be formed after charging for a period of time, so that a collector electrode and an emitter electrode of the triode are turned on, at this time, another part of current of the first detection signal is amplified by the triode and then output to the first shaping unit 323, and specifically, the triode can amplify the current by a times (a > 1). Under the condition that the current magnitude of the driving signal is unchanged, since the triode passes a part of the current, the first resistor R1 passes a part of the current, and compared with the condition that the whole current directly acts on the first resistor R1, the reliability and the service life of the first resistor R1 in the delay unit 322 provided by the embodiment are better.

In some embodiments, the fault recovery time circuit 32 may further include a bias circuit (not shown) and a current control circuit 324. The bias circuit is configured to provide a bias signal, and the current control circuit 324 may be connected to the bias circuit and the first end of the second switch transistor T2, and configured to control a current magnitude of the power signal according to the bias signal. Wherein the current value of the bias signal is smaller than the current value of the control signal. Specifically, the current control circuit 324 is configured to reduce the current magnitude of the power signal input to the first switch unit 321, so as to reduce the current magnitude of the first detection signal input to the delay unit 322, and the smaller current can reduce the occupied area of T1, R1, C1, and other parameters.

In some embodiments, the current control circuit 324 may include a fourth switching tube (not shown), a first terminal of the fourth switching tube may be connected to the power supply to input the power supply signal, a second terminal of the fourth switching tube is connected to the first terminal of the second switching tube T2, and a control terminal of the fourth switching tube is connected to the bias circuit to input the bias signal, so as to output the power supply signal adjusted by the current control circuit 324 to the second switching tube T2 of the first switching unit 321.

In some embodiments, the comparator may include a bias circuit, and the bias signal output by the programming circuit may be transmitted to the current control circuit 324 through the BLAS line to control the current input to the first switch unit 321. The bias circuit may be a Mirror Current source, also referred to as a Current Mirror. Specifically, the fourth switch tube may be a PMOS tube, and the BLAS line may transmit the bias signal output by the programming circuit to the gate of the PMOS tube.

In some embodiments, as shown in fig. 10, the fault recovery time circuit 32 may further include a first filtering unit 325, a first end of the first filtering unit 325 is connected to the output end of the delay unit 322, and a second end of the first filtering unit 325 is connected to ground, for performing auxiliary filtering processing on the current signal output by the output end of the delay unit 322.

In some embodiments, the first filter unit 325 may include a second capacitor C2, a first terminal of the second capacitor C2 is connected to the second terminal of the first switch transistor T1, i.e., between the first switch transistor T1 and the first shaping unit 323, and a second terminal of the second capacitor C2 is grounded. In other embodiments, the first filtering unit 325 may include a plurality of second capacitors C2, and the plurality of second capacitors C2 may be connected in parallel and/or in series, and the connection manner is not limited. For example, the first filtering unit 325 may include two, three, or four second capacitors C2.

The first shaping unit 32325 may be connected to the delay unit 322 and the logic control circuit 33, and configured to shape the first detection signal and output the shaped first detection signal to the logic control circuit 33. The shaping process may include waveform transformation, pulse shaping, and pulse amplitude qualification. The waveform conversion is to convert a sine wave into a square wave, the pulse shaping is to correct the distortion of pulses in the transmission process, the pulse amplitude identification is to input pulses with different amplitudes into the first shaping unit 323, and only the pulses with the amplitude larger than a preset amplitude threshold value generate signals at the input end of the first shaping unit 323. When the amplitude of the input pulse is smaller than the preset amplitude threshold, it indicates that although the delay unit 322 is in the on state at this time, the amplitude of the first detection signal output by the delay unit 322 has not yet reached the maximum value, that is, has not yet stabilized, and at this time, the first shaping unit 323 does not output the first detection signal to the rear-end logic control circuit 33 for a while.

For example, in this embodiment, the preset amplitude threshold may be 8V, when the amplitude of the first detection signal input by the first shaping unit 323 is greater than 8V, the first shaping unit 323 outputs the first detection signal, otherwise, the first detection signal is not output.

In some embodiments, the first shaping unit 323 may include a schmitt trigger, a first end of the schmitt trigger is connected to the delay unit 322, and a second end of the schmitt trigger is connected to the logic control circuit 33. The schmitt trigger may comprise a gate (e.g., a CMOS inverter), a transistor, or a 555 timer. Specifically, the circuit structure of the schmitt trigger can refer to the related art, and is not described herein.

The logic control circuit 33 may be connected to the fail-back time circuit 32 for outputting a fail signal based on the first detection signal. The logic control circuit 33 may specifically include a T flip-flop.

The fault handling circuit 30 may further comprise a filter shaping circuit 34, the filter shaping circuit 34 may be connected to the detection circuit 31 and configured to input the power supply signal for outputting the second detection signal in dependence on the power supply signal and the control signal.

In some embodiments, as shown in fig. 11, the filter shaping circuit 34 includes a second switching unit 341, a second filtering unit 342, and a second shaping unit 343. Wherein the second switching unit 341 may be configured to input the power signal and the control signal and output the second detection signal according to the power signal and the control signal. The second filtering unit 342 is connected to the second switching unit 341 and is configured to filter the second detection signal, and the second filtering unit 342 may be an RC circuit. The second shaping unit 343 is connected to the second filtering unit 342 and the logic control circuit 33, and is configured to shape the second detection signal.

In some embodiments, the second filter circuit may include a second resistor R2 and a third capacitor C3, a first end of the second resistor R2 is connected to the switching unit, a second end of the second resistor R2 is connected to the second shaping unit 343, a first end of the third capacitor C3 is connected to the second end of the second resistor R2, and a second end of the third capacitor C3 is grounded.

In some embodiments, as shown in fig. 11, the second switching unit 341 may include a fifth switching tube T5 and a sixth switching tube T6. The fifth switch tube T5 and the sixth switch tube T6 may be different kinds of switch tubes. For example, the switching characteristics of the fifth switching tube T5 and the sixth switching tube T6 may be opposite. A control terminal of the fifth switch T5 is connected to the detection circuit 31 for inputting the control signal, a first terminal of the fifth switch T5 is connected to the power supply for inputting the power supply signal, and a second terminal of the fifth switch T5 is connected to the input terminal of the second filtering unit 342 for outputting the first detection signal to the second filtering unit 342 according to the control signal. A control terminal of the sixth switch tube T6 is connected to the detection circuit 31 for inputting the control signal, a first terminal of the sixth switch tube T6 is connected to the output terminal of the second filtering unit 342, and a second terminal of the sixth switch tube T6 is grounded. It is understood that the kinds and parameters (breakdown voltage, power consumption, etc.) of the fifth switch transistor T5 and the sixth switch transistor T6 may be selected according to practical situations, and are not limited herein.

In some embodiments, the fifth switch transistor T5 may be a P-type MOS transistor, and the sixth switch transistor T6 may be an N-type MOS transistor. The control end of the fifth switching tube T5 is the gate of the P-type MOS transistor, the first end of the fifth switching tube T5 is the source of the P-type MOS transistor, and the second end of the fifth switching tube T5 is the drain of the P-type MOS transistor; the control end of the sixth switch tube T6 is the gate of the N-type MOS transistor, the first end of the sixth switch tube T6 is the source of the N-type MOS transistor, and the second end of the sixth switch tube T6 is the drain of the N-type MOS transistor.

In some embodiments, the shaping process of the second shaping unit 343 may include waveform transformation, pulse shaping, and pulse amplitude qualification. The second shaping unit 343 may comprise a schmitt trigger, a first terminal of which is connected to the second filtering unit 342 and a second terminal of which is connected to the logic control circuit 33. For the description of the second shaping unit 343, reference may be made to the corresponding location of the first shaping unit 323, and details are not described here.

In some embodiments, as shown in fig. 9, the logic control circuit 33 may include an RS flip-flop, also called a reset-set flip-flop. The R input of the RS flip-flop is connected to the filter shaping circuit 34 for inputting the first detection signal, and the S input of the RS flip-flop is connected to the fail-back time circuit 32 for inputting the second detection signal for outputting the fail signal based on the first detection signal and the second detection signal. The RS trigger comprises an R input end, an S input end, a Q output end and a non-Q output end. In this embodiment, the output terminal of the logic control circuit 33 is a Q output terminal. Wherein:

when the R input end is connected with a low level and the S input end is connected with the low level, the Q output end outputs 1 and the non-Q output end outputs 1;

when the R input end is connected with a low level and the S input end is connected with a high level, the Q output end outputs 0 and the non-Q output end outputs 1;

when the R input end is connected with a high level and the S input end is connected with a low level, the Q output end outputs 1 and the non-Q output end outputs 0;

the R input end is connected with a high level, when the S input end is connected with the high level, the Q output end is kept unchanged, and the non-Q output end is kept unchanged.

It can be understood that when the first detection signal is at a high level and the second detection signal is at a low level, it indicates that no fault occurs or the fault is recovered in the circuit at this time, and the Q output end outputs a high level, so that the circuit can be controlled to normally operate according to the fault signal; when the first detection signal is at a low level and the second detection signal is at a high level, the Q output end outputs a fault signal at a low level, which indicates that a fault exists in the circuit at the moment, so that the Q output end outputs the low level, and the circuit can be controlled to stop working according to the fault signal; when the first detection signal is at high level and the second detection signal is at low level, the Q output end outputs a fault signal of high level, which indicates that the fault is recovered, so that the high level can be output to control the circuit to start working according to the fault signal.

It can be understood that the RS flip-flop may further include a positive-side power pin and a negative-side power pin, the positive-side power pin may be connected to a power supply to input a supply voltage VCC, and the negative-side power pin may be grounded GND.

In the above scheme, the fault processing circuit includes a detection circuit, a fault recovery time circuit and a logic control circuit, wherein the detection circuit is used for detecting a circuit fault and outputting a control signal; the fault recovery time circuit is connected with the detection circuit and is configured to input a power supply signal for outputting a first detection signal according to the power supply signal and the control signal; the logic control circuit is connected with the fault recovery time circuit and used for outputting a fault signal according to the first detection signal; the fault recovery time circuit comprises a first resistor, a first capacitor and a current amplifying circuit, wherein the current amplifying circuit is connected with the first resistor and the first capacitor and is used for amplifying the current flowing through the first resistor, so that the fault recovery time of the fault recovery time circuit can be prolonged by increasing the resistance value of the first resistor, and meanwhile, the current flowing through the first resistor is amplified through the current amplifying circuit, and the loss of the output current of the fault recovery time circuit can be reduced. Secondly, the first detection signal can be shunted by the current amplification circuit (the first switch tube), so that the current on the first resistor can be reduced, and the loss in the fault time recovery circuit can be further reduced.

Referring to fig. 12, fig. 12 is a schematic structural diagram of an embodiment of a chip provided in the present application.

In this embodiment, the chip 40 may include a control circuit 41 and a driving circuit 42 in any of the above embodiments, the control circuit 41 may provide a control signal for the driving circuit 42, and the driving circuit 42 may output a driving signal according to the control signal to drive the power device. The control circuit 41 is, for example, a microprocessor, the control signal is, for example, a pwm (pulse Width modulation) pulse signal, and the power device is, for example, an IGBT. For the description of the driving circuit 42, refer to the corresponding position in the above embodiments, and the description thereof is omitted.

In some embodiments, the chip 40 may be a High Voltage Integrated Circuit (HVIC) which is an important component of an IPM (Intelligent Power Module). The HVIC plays a role in intelligent protection and high-voltage isolation and power device driving. The HVIC can convert the low-voltage signal of the MCU into a driving signal capable of driving power devices with different specifications.

In some embodiments, the chip 40 may include the driving circuits in the first to third embodiments described above. At present, a driving circuit integrated in a chip does not include a gate resistor and a driving capacitor, but the gate resistor and the gate resistor are designed outside the chip, which results in a complex package, and thus a parasitic capacitor and a parasitic resistor are easily introduced. Since the resistance of the gate resistor is generally small, the area actually occupied by the gate resistor is large, the area of the driving capacitor is also large, and the available area of the chip is limited, so that the gate resistor and the driving capacitor are difficult to design in the chip. And the resistance of the gate resistor is small, which causes the current flowing through the gate resistor to be higher, thereby affecting the performance of the chip.

In the above solution, the chip includes a control circuit and a driving circuit, the driving circuit includes a switch unit and a driving adjustment unit, and is used for driving the power device, the switch unit is configured to input a power signal and a control signal, and output the driving signal according to the power signal and the control signal, the driving adjustment unit is connected to the switch unit and the power device, and is used for amplifying the driving signal, so as to drive the power device by using the amplified driving signal, wherein the driving adjustment unit includes a first resistor and a current amplification circuit, a first end of the first resistor is connected to the switch unit, a first end of the current amplification circuit is connected to the first resistor, a second end of the current amplification circuit is connected to the power device, and is used for amplifying the current flowing through the first resistor, and due to the gain effect of the first switch tube, the sizes of the first resistor and the first capacitor can be adjusted, the occupied area of the first resistor and the first capacitor is reduced, and meanwhile, the normal driving of the power device is realized, and the driving circuit can be integrated in a chip. Secondly, owing to integrate first resistance and first electric capacity in the chip, the chip has integrated the function of adjusting grid drive efficiency promptly to can reduce the area occupied of first resistance and first electric capacity, can also reduce the resonance problem that parasitic inductance clutter and parasitic capacitance introduce, in addition, can also reduce the electric current of first resistance, promote the reliability life-span of first resistance.

In other embodiments, the chip 40 may include the driving circuits in the fourth to seventh embodiments described above.

In the above scheme, the chip includes a driving circuit, the driving circuit is used for driving the power device, and the driving circuit includes: a first switch tube, wherein a first end of the first switch tube is configured to input a power supply signal; the first end of the second switching tube is connected with the second end of the first switching tube, and the second end of the second switching tube is connected with the power device; the control end of one of the first switch tube and the second switch tube is configured to input a control signal to serve as a driving switch, and the other switch tube is configured to serve as a resistor on a current path of the driving switch when the driving switch is turned on. It is thus clear that, because the switch tube has the resistance under the on-state, this application is through configuring first switch tube or second switch tube among the drive circuit as the resistance on the drive switch current path when drive switch opens to can avoid additionally setting up grid resistance in drive circuit, thereby can reduce drive circuit's area, and then reduce chip area.

Referring to fig. 13, fig. 13 is a schematic structural diagram of an embodiment of a chip provided in the present application.

In this embodiment, the chip 50 includes the fault processing circuit 51 and the control circuit 52 in any of the above embodiments, the fault processing circuit 51 is configured to output a fault signal, and the control circuit 52 is connected to the fault processing circuit 51 and configured to start or stop the operation of the chip according to the fault signal.

For the description of the fault processing circuit 51 and the control circuit 52 in this embodiment, reference may be made to corresponding positions in the above-mentioned fault processing circuit embodiment, which is not described herein again.

In the scheme, the chip comprises a fault processing circuit and a control circuit; the fault processing circuit comprises a detection circuit, a fault recovery time circuit and a logic control circuit, wherein the detection circuit is used for detecting circuit faults and outputting control signals; the fault recovery time circuit is connected with the detection circuit and is configured to input a power supply signal for outputting a first detection signal according to the power supply signal and the control signal; the logic control circuit is connected with the fault recovery time circuit and used for outputting a fault signal according to the first detection signal; the fault recovery time circuit comprises a first resistor, a first capacitor and a current amplifying circuit, wherein the current amplifying circuit is connected with the first resistor and the first capacitor and is used for amplifying the current flowing through the first resistor, so that the fault recovery time of the fault recovery time circuit can be prolonged by increasing the resistance value of the first resistor, and meanwhile, the current flowing through the first resistor is amplified through the current amplifying circuit, and the loss of the output current of the fault recovery time circuit can be reduced. Secondly, the first detection signal can be shunted by the current amplification circuit (the first switch tube), so that the current on the first resistor can be reduced, and the loss in the fault time recovery circuit can be further reduced.

Referring to fig. 14, fig. 14 is a schematic structural diagram of an embodiment of an intelligent power module provided in the present application.

In this embodiment, the Intelligent Power Module 60 (IPM) may include the chip 61 and the Power device 62 in the above embodiment, and the chip 61 is connected to the Power device 62 for providing the Power device 62 with operating current.

The smart power module 60 is a power switch device that converts a dc voltage (current) into an ac voltage (current) with variable amplitude and frequency under the action of a control signal, and the output ac voltage is applied to a motor to drive the motor to operate. Due to the advantages of high integration level, good reliability and the like, the intelligent power module 60 is widely applied to frequency conversion speed regulation, metallurgical machinery, electric traction, servo drive and frequency conversion household appliances. The IPM is formed by organically assembling and packaging a High Voltage Integrated Circuit (HVIC), an Insulated Gate Bipolar Transistor (IGBT), a Fast Recovery Diode (FRD), a power semiconductor device (power device), and other resistance and capacitance devices, and mainly realizes power conversion, real-time protection and communication functions. Wherein, the power of IPM is realized by IGBT and FRD, and the current capability of a few A to a few hundred A can be provided. The power devices generally adopt IGBTs and MOSFETs according to different current and voltage levels.

In some embodiments, the smart power module 60 may include 1 or more power devices 62, the number of driving circuits in the chip 61 may correspond to the number of power devices 62, and each driving circuit is connected to one power device 62 to provide an operating current for the power device 62. Although the present application exemplifies one driving circuit and one power device, a plurality of driving circuits may be used to control the on/off of a plurality of power devices.

As can be understood by those skilled in the art, the smart power module not only integrates the power device and the driving circuit, but also integrates an overvoltage protection circuit, an overcurrent protection circuit, an overheat protection circuit, an undervoltage locking circuit, and the like. Smart power modules typically use IGBTs or MOSFETs as power devices.

Referring to fig. 15, fig. 15 is a schematic structural diagram of an embodiment of a household appliance provided in the present application.

In this embodiment, the household appliance 70 may include one or more of the driving circuit (not shown), the fault processing circuit (not shown), the chip (not shown), and the intelligent power module 71 in the above embodiments, that is, the household appliance 70 may include the driving circuit, the fault processing circuit, the chip, or the intelligent power module 71 alone, may further include the driving circuit, the chip, or may include one, two, or three of the driving circuit, the chip, and the intelligent power module 71 at the same time. In some embodiments, the household appliance 70 may include the smart power module 71 of the above embodiments.

In some embodiments, the household appliance 70 may be an air conditioner, and the IPM module may be disposed on an electric control board of the air conditioner. The IPM module may be connected in a main circuit of the air conditioner for a DC-AC conversion function. The IPM module can also be used for household appliances 70 such as washing machines, refrigerators, and the like.

The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims

1. A fault handling circuit, wherein the fault handling circuit comprises:

the detection circuit is used for detecting circuit faults and outputting control signals;

a fault recovery time circuit connected to the detection circuit and configured to input a power signal for outputting a first detection signal according to the power signal and the control signal; the fault recovery time circuit comprises a first resistor, a first capacitor and a current amplification circuit, wherein the current amplification circuit is connected with the first resistor and the first capacitor and is used for amplifying current flowing through the first resistor;

and the logic control circuit is connected with the fault recovery time circuit and is used for outputting a fault signal according to the first detection signal.

2. The fault handling circuit of claim 1, wherein the fault recovery time circuit comprises:

a first switching unit configured to input the power supply signal and the control signal and output the first detection signal according to the power supply signal and the control signal;

the delay unit comprises a first resistor, a first capacitor and a current amplification circuit, wherein the first end of the first resistor is connected with the first switch unit, the first end of the first capacitor is connected with the second end of the first resistor, the second end of the first capacitor is grounded, and the first end of the current amplification circuit is connected with the first end of the first resistor and is used for amplifying the current flowing through the first resistor;

and the first shaping unit is connected with the output end of the delay unit and the logic control circuit and is used for shaping the first detection signal.

3. The fault handling circuit of claim 2, wherein the current amplification circuit comprises:

the first end of the first switch tube is connected with the first end of the first resistor, the second end of the first switch tube is connected with the first shaping unit, and the control end of the first switch tube is connected with the second end of the first resistor.

4. The fault handling circuit according to claim 3, wherein the first switching transistor is an NPN transistor, a collector of the NPN transistor is connected to the first end of the first resistor, an emitter of the NPN transistor is connected to the first shaping unit, and a base of the NPN transistor is connected to the second end of the first resistor.

5. The fault handling circuit of claim 2, wherein the first switching unit comprises:

the control end of the second switch tube is connected with the detection circuit, the first end of the second switch tube inputs the power supply signal, and the second end of the second switch tube is connected with the input end of the delay unit;

and the control end of the third switching tube is connected with the detection circuit, the first end of the third switching tube is connected with the output end of the delay unit, and the second end of the third switching tube is grounded.

6. The fault handling circuit of claim 5,

the fail-over time circuit further comprises:

a bias circuit for providing a bias signal;

the current control circuit is connected with the bias circuit and the first end of the second switching tube and is used for controlling the current of the power supply signal according to the bias signal;

wherein a current value of the bias signal is smaller than a current value of the control signal.

7. The fault handling circuit of claim 6,

the current control circuit comprises a fourth switch tube, the control end of the fourth switch tube is connected with the bias circuit, the first end of the fourth switch tube is inputted with the power signal, and the second end of the fourth switch tube is connected with the first end of the second switch tube.

8. The fault handling circuit according to claim 2, wherein the fault recovery time circuit further comprises a first filtering unit, a first terminal of the first filtering unit is connected to the output terminal of the delay unit, and a second terminal of the first filtering unit is connected to ground.

9. The fault handling circuit of claim 1,

the detection circuit includes:

and a first input end of the comparator is used for inputting a signal to be detected, a second input end of the comparator is used for inputting a reference signal, and an output end of the comparator is used for outputting the control signal.

10. The fault handling circuit of claim 9,

the detection circuit further includes:

and the input end of the ESD protection circuit is used for inputting the signal to be detected, and the output end of the ESD protection circuit is connected with the first input end of the comparator.

11. The fault handling circuit of claim 1,

the fault handling circuit further comprises:

a filter shaping circuit connected to the detection circuit and configured to input a power signal for outputting a second detection signal according to the power signal and a control signal;

the logic control circuit includes:

and the R input end of the RS trigger is connected with the filter shaping circuit, and the S input end of the RS trigger is connected with the fault recovery time circuit and is used for outputting a fault signal according to the first detection signal and the second detection signal.

12. A chip, comprising: a control circuit and a fault handling circuit according to any of claims 1-11, said fault handling circuit being adapted to output a fault signal, said control circuit being connected to said fault handling circuit for turning on or off the operation of the chip in dependence on the fault signal.

13. A smart power module, comprising: the chip of claim 12.

14. A household appliance, characterized in that it comprises: the smart power module as recited in claim 13.